One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.
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1. An integrated circuit product, comprising:
a gate structure for a transistor;
a conductive source/drain contact structure;
an insulating source/drain cap structure positioned above said conductive source/drain contact structure, said insulating source/drain cap structure comprising a first notch;
a sidewall spacer, a portion of which is positioned laterally between said gate structure and said conductive source/drain contact structure, said sidewall spacer comprising a second notch in an upper portion of said sidewall spacer, wherein a first portion of said insulating source/drain cap structure is positioned in said second notch; and
a conductive gate contact structure comprising first and second portions, said first portion of said conductive gate contact structure being positioned in said first notch, said second portion of said conductive gate contact structure being in contact with said gate structure.
14. An integrated circuit product, comprising:
a gate structure for a transistor;
a conductive source/drain contact structure;
an insulating source/drain cap structure positioned above said conductive source/drain contact structure, said insulating source/drain cap structure comprising a first notch;
a sidewall spacer, a portion of which is positioned laterally between said gate structure and said conductive source/drain contact structure, said sidewall spacer comprising a second notch in an upper portion of said sidewall spacer that is at least partially defined by a tapered portion, wherein a first portion of said insulating source/drain cap structure is positioned in said second notch and physically contacts said sidewall spacer; and
a conductive gate contact structure comprising first and second portions, wherein said first portion of said conductive gate contact structure is positioned in said first notch and physically contacts said insulating source/drain cap structure, said second portion of said conductive gate contact structure is in contact with an upper surface of said gate structure and wherein said tapered portion of said sidewall spacer is positioned laterally between a part of said conductive gate contact structure and a part of said insulating source/drain cap structure.
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The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various embodiments of a gate contact structure that is positioned above an active region of a transistor device.
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are formed and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
Typically, due to the large number of semiconductor devices (i.e., circuit elements such as transistors, resistors, capacitors, etc.) and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual semiconductor devices, e.g., transistors, capacitors, etc., cannot be established within the same device level on which the semiconductor devices are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the IC product are formed in a metallization system that comprises a plurality of stacked “metallization layers” that are formed above the device level of the product. These metallization layers are typically comprised of layers of insulating material with conductive metal lines or conductive vias formed in the layers of insulating material. Generally, the conductive lines provide the intra-level electrical connections, while the conductive vias provide the inter-level connections or vertical connections between different levels of the conductive lines. These conductive lines and conductive vias may be comprised of a variety of different materials, e.g., copper, tungsten, aluminum, etc. (with appropriate barrier layers). The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer. Normally, a plurality of conductive vias (typically referred to as “V0” vias) are used to establish electrical connection between the M1 layer and lower level conductive structures that are generally referred to as device-level contacts (explained more fully below). In some more advanced devices, another metallization layer comprised of conductive lines (sometimes called the “M0” layer) is formed between the device level contacts and the V0 vias.
There are also device level contacts positioned below the lowermost layer of the metallization system on an IC product. For example, such device level contacts include a plurality of so-called “CA contact” structures for establishing electrical connection to the source/drain regions of a transistor device, and a gate contact structure, which is sometimes referred to as a “CB contact” structure, for establishing electrical connection to the gate structure of the transistor device. The CB gate contact is typically positioned vertically above isolation material that surrounds the transistor device, i.e., the CB gate contact is typically not positioned above the active region, but it may be in some advanced architectures.
The CB gate contact is typically positioned above the isolation region so as to avoid or reduce the chances of creating an electrical short between the CB gate contact and the conductive source/drain structures (e.g., trench silicide (TS) structures) formed in the source/drain regions of the transistor adjacent the gate structure of the transistor. Insulating material, typically in the form of at least a sidewall spacer, is positioned between the gate structure and the conductive source/drain structures. Typically, there are also design rules that set a minimum spacing that must be maintained between the CB gate contact and the conductive source/drain structures in an attempt to prevent such electrical shorts. Unfortunately, there is an area penalty associated with the requirement that the CB gate contact only be positioned above the isolation region.
Efforts have been made to create process flows whereby the CB contact is formed entirely over the active area. Unfortunately, such process flows typically involve many additional process steps and may require the use of new materials. Such complex processing also inherently increases the chances of reduced product yields. What is needed is a method for forming the CB gate contact so as to conserve valuable plot space on an IC product that is less complex than the processes whereby the CB contact is formed entirely over the active region. What is further needed is a less complex process flow for forming the CB contact entirely over the active area. Some IC products include CB contacts that are formed entirely over the active region as well as other CB contacts that are formed above isolation material. What is also needed is an efficient process flow for forming all of these device level contacts on advanced IC products with densely packed transistor devices.
The following presents a simplified summary of illustrative embodiments of the invention in order to provide a basic understanding of some aspects of the illustrative embodiments of the invention specifically disclosed herein. This summary is not an exhaustive overview of the various illustrative embodiments of the inventions disclosed herein. It is not intended to identify key or critical elements of the illustrative embodiments of inventions disclosed herein or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various embodiments of a gate contact structure that is positioned above an active region of a transistor device and various methods of making such a gate contact structure. One illustrative integrated circuit product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, the insulating source/drain cap structure having a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer, a portion of which is positioned laterally between the gate structure and the conductive source/drain contact structure, the sidewall spacer having a second notch formed in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch, the second portion of the conductive gate contact structure being in contact with the gate structure.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific and illustrative embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various embodiments of a gate contact structure that is positioned above an active region of a transistor device and various methods of making such a gate contact structure. The various methods disclosed herein are described in the illustrative context of forming device level contact structures, such as source/drain contact structures and gate contact structures, on IC products. However, as will be appreciated by those skilled in the art after a complete reading of the present application, the various methods and devices disclosed herein are not limited to the formation of device level contacts. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory products, logic products, ASICs, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, the inventions disclosed herein may be employed in forming integrated circuit products using transistor devices in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. In the illustrative examples depicted herein, the transistor devices will be FinFET devices. The gate structures for the transistor devices may be formed using either “gate first” or “replacement gate” manufacturing techniques. Thus, the presently disclosed inventions should not be considered to be limited to any particular form of transistors or the manner in which the gate structures of the transistor devices are formed. Of course, the illustrative embodiments of the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. The various layers of material described below may be formed by any of a variety of different known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. Moreover, as used herein and in the attached claims, the word “adjacent” is to be given a broad interpretation and should be interpreted to cover situations where one feature actually contacts another feature or is in close proximity to that other feature.
With reference to
As indicated in
The substrate 102 may have a variety of configurations, such as the depicted bulk silicon configuration. The substrate 102 may also have a semiconductor-on-insulator (SOI) configuration that includes a bulk semiconductor layer, a buried insulation layer and an active semiconductor layer positioned on the buried insulation layer, wherein semiconductor devices are formed in and above the active layer. The substrate 102 may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. Additionally, various doped regions, e.g., halo implant regions, well regions and the like, are not depicted in the attached drawings.
Still with reference to
Still referencing
After formation of the epi semiconductor material 116, a layer of insulating material 113 (e.g., silicon dioxide) was blanket-deposited across the substrate. Thereafter a CMP process was performed to planarize the layer of insulating material 113 using the original gate caps (not shown) positioned above the sacrificial gate structures as a polish-stop layer. At that point, traditional replacement gate manufacturing processes were performed to remove the original gate caps and the sacrificial gate structures and to form the final gate structures 108 within the gate cavities defined by removing the sacrificial gate structures. Thereafter, in this particular embodiment, the materials of the final gate structures were recessed and the final gate caps 111 were formed on the product 100 by depositing gate cap material and performing a CMP process operation to planarize the upper surface of the gate caps 111 with the upper surface of the layer of insulating material 113.
The materials of construction for the gate caps 111, the spacers 112 and the layer of insulating material 113 may be specifically selected so as to achieve the objectives set forth below. Of course, the materials of construction for the gate caps 111, the spacers 112 and the layer of insulating material 113 may vary depending upon the particular application. In terms of relative etch selectivity during this common etching process 114, the material of the gate caps 111 will exhibit the slowest etch rate among the three materials, while the material of the layer of insulating material 113 will exhibit the fastest etch rate among the three materials. The material of the sidewall spacers 112 will exhibit an etch rate that is intermediate the etch rate of the gate caps 111 and the etch rate of the layer of insulating material 113 when subjected to this common etching process 114. In one example, the material of the spacers 112 exhibits an etch rate that is closer to the etch rate of the layer of insulating material 113 than it is to the etch rate of the material for the gate caps 111 when subjected to this common etching process 114. In one illustrative embodiment, the layer of insulating material 113 may be comprised of silicon dioxide, the sidewall spacers 112 may be comprised of silicon carbon oxynitride (SiCON) or silicon carbon oxide (SiCO), and the gate caps 111 may be comprised of silicon nitride. As a result, at the completion of the common etching process 114, the layer of insulating material 113 is essentially cleared from above the epi semiconductor material 116 in the source/drain regions of the transistor devices, a portion of the upper part of the spacers 112 was removed and a portion of the thickness of the gate caps 111 was removed.
More specifically, due to the selection of the appropriate materials, a notch 111Y is formed in the gate caps 111 positioned on the gates 1 and 4, i.e., in the gate caps 111 on the outermost gates (1 and 4) of the array of gates 1-4, while the gate caps 111 on gates 2 and 3 have a substantially planar upper surface 111X. Additionally, during this common etching process 114, the spacers 112 are etched in such a manner so as to form a notch 112W in the spacers 112. The notch 112W is not formed in the outermost spacers 112P and 112Q since those spacers are covered by the patterned etch mask 115. The notch 112W in each of the etched spacers 112 extends axially into and out of the plane of the drawing page for a distance that corresponds approximately to the axial length (in the gate width direction of the transistor devices) of the conductive source/drain contact structure 120 positioned adjacent each of the particular spacers 112. In the depicted example, the notch 112W is defined by a tapered surface 112Z and a substantially horizontally oriented surface 112X. At this point in the process flow, the etched portion of the spacers 112 (other than the two outermost spacers 112P and 112Q) comprises an upwardly extending tapered portion 112Y.
The CB gate contact structure 130 and the CA contact structures 132 may be comprised of a variety of different materials and they may be formed by performing various manufacturing techniques. In one illustrative example, one or more conformal barrier layers and/or seed layers (not separately shown) were formed so as to line the gate contact opening 135 and the CA contact openings 133 with the barrier material(s). Next, one or more conductive materials (e.g., copper, a metal-containing material, a metal compound, etc.) was then formed on the product 100 so as to overfill the gate contact opening 135 and the CA contact openings 133. At that point, a CMP process was performed to remove excess portions of the conductive materials from above the upper surface of the layer of insulating material 127. These process operations result in the formation of a CB gate contact structure 130 and two CA contact structures 132. The CB gate contact structure 130 is positioned above the active region and it conductively contacts the gate structure 108-2 of gate 2 and the gate structure 108-3 of gate 3. Each of the CA contact structures 132 conductively contacts an underlying source/drain contact structure 120. Note that, in the illustrative process flow above, the CA contact openings 133 were formed before the gate contact opening 135 was formed, but the order of formation of the gate contact opening 135 and the CA contact openings 133 may be reversed if desired.
As will be appreciated by those skilled in the art after a complete reading of the present application, the insulating source/drain cap structures 125A and 125C positioned adjacent the outer edges of the CB gate contact structure 130 (or 130A) have a very unique cross-sectional configuration (when viewed in a cross-section taken through the insulating source/drain cap structures 125 in the gate length direction of the transistor devices). Similarly, the spacers 112 positioned adjacent the insulating source/drain cap structures 125A and 125C, such as the spacer 112S, also have a very unique configuration.
With reference to
One illustrative integrated circuit product disclosed herein includes a gate structure 108 for a transistor, a conductive source/drain contact structure 120 and an insulating source/drain cap structure 125A positioned above the conductive source/drain contact structure 120, wherein a first notch 125Y is formed in the insulating source/drain cap structure 125A. In one illustrative example, the product also includes a sidewall spacer 112, a portion (below the notch 112W) of which is positioned laterally between the gate structure 108 and the conductive source/drain contact structure 120. A second notch 112W is formed in an upper portion of the sidewall spacer 112. A first portion of the insulating source/drain cap structure 125A is positioned in the second notch 112W. In this example, a first portion of the conductive gate contact structure 130 is positioned in the first notch 125Y while a second portion of the conductive gate contact structure 130 is in contact with the gate structure 108.
Another illustrative integrated circuit product disclosed herein includes a gate structure 108 for a transistor, a conductive source/drain contact structure 120 and an insulating source/drain cap structure 125A positioned above the conductive source/drain contact structure 120. The insulating source/drain cap structure 125A has a first notch 125Y formed therein. In this example, the product also includes a sidewall spacer 112, a lower portion of which is positioned laterally between the gate structure 108 and the conductive source/drain contact structure 120, wherein a second notch 112W is formed in the upper portion of the sidewall spacer 112. A first portion of the insulating source/drain cap structure 125A is positioned in the second notch 112W and physically contacts the sidewall spacer 112. In this embodiment, a first portion of the conductive gate contact structure 130 is positioned in the first notch 125Y and physically contacts the insulating source/drain cap structure 125A while a second portion of the conductive gate contact structure 130 is in contact with an upper surface of the gate structure. In this example, a tapered portion 112Y of the sidewall spacer 112 is positioned laterally between a part of the conductive gate contact structure 130 and a part of the insulating source/drain cap structure 125A.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Xie, Ruilong, Park, Chanro, Labonte, Andre
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