A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.
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11. A method for manufacturing a semiconductor device, comprising:
forming a fin structure including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
oxidizing side walls of the intermediate layer;
after the oxidizing, forming a protective layer over the lower layer, the intermediate layer and the upper layer of the fin structure;
reducing a height of the protective layer such that the partially oxidized intermediate layer remains covered by the protective layer;
forming an isolation insulating layer so that the fin structure, including the lower layer, the intermediate layer, the upper layer and with the protective layer with the reduced height is embedded in the isolation insulating layer; and
forming a gate structure over the upper layer.
1. A method for manufacturing a semiconductor device, comprising:
forming a fin structure including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
forming a protective layer on at least side walls of the fin structure to cover side walls of the intermediate layer and the lower layer, the protective layer being made of a material that prevents an underlying layer from oxidation;
forming an isolation insulating layer so that the fin structure, including the lower layer, the intermediate layer, the upper layer and the protective layer, is embedded in the isolation insulating layer;
removing a part of the upper layer and the isolation insulating layer, thereby forming an opening in the isolation insulating layer; and
forming a channel layer in the opening.
18. A method for manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, each of which includes a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
oxidizing side walls of the intermediate layer of the second fin structure, while the first fin structure is covered by a cover layer;
forming a protective layer to fully cover the first fin structure and the second fin structure with partially oxidized intermediate layer;
reducing a height of the protective layer such that the intermediate layer of the first fin structure and the partially oxidized intermediate layer of the second fin structure remain covered by the protective layer;
forming an isolation insulating layer so that the first and second fin structures with the protective layer with the reduced height are embedded in the isolation insulating layer;
removing a part of the upper layer of the first fin structure and the isolation insulating layer, thereby forming an opening in the isolation insulating layer; and
forming a channel layer on the upper layer of the first fin structure in the opening.
2. The method of
removing a part of the protective layer covering the upper layer so that the protective layer remains on side walls of the lower layer, the side walls of the intermediate layer and a side wall of a bottom part of the upper layer,
wherein a bottom of the opening is spaced apart from the protective layer.
3. The method of
forming a sacrificial layer so that the fin structure with the protective layer is embedded in the sacrificial layer;
reducing a thickness of the sacrificial layer;
removing the part of the protective layer covering the upper layer so that the protective layer remains on the side walls of the lower layer, the side walls of the intermediate layer and the side walls of the bottom part of the upper layer; and
removing the sacrificial layer of which thickness has been reduced.
5. The method of
the removing the part of the protective layer includes:
forming a first insulating layer;
reducing a thickness of the first insulating layer; and
removing the part of the protective layer covering the upper layer so that the protective layer remains on the side walls of the lower layer, the side walls of the intermediate layer and the side walls of the bottom part of the upper layer, and
the forming the isolation insulating layer includes:
forming a second insulating layer on the first insulating layer of which thickness has been reduced.
7. The method of
9. The method of
10. The method of
12. The method of
forming a sacrificial layer so that the fin structure with the protective layer is embedded in the sacrificial layer;
reducing a thickness of the sacrificial layer;
removing the part of the protective layer exposed from the sacrificial layer with the reduced thickness; and
removing the sacrificial layer with the reduced thickness.
14. The method of
the reducing the height of the protective layer includes:
forming a first insulating layer;
reducing a thickness of the first insulating layer; and
removing the part of the protective layer exposed from the first insulating layer with the reduced thickness, and
the forming the isolation insulating layer includes forming a second insulating layer on the first insulating layer with the reduced thickness.
16. The method of
19. The method of
exposing the formed channel layer and the upper layer of the second fin structure; and
forming a first gate structure over the exposed channel layer and a second gate structure over the exposed upper layer.
20. The method of
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This application is a divisional of U.S. patent application Ser. No. 14/579,708 filed on Dec. 22, 2014, the entire contents of which applications are incorporated herein by reference.
The disclosure relates to a semiconductor integrated circuit, more particularly to a semiconductor device with a fin field effect transistor (PET) and its manufacturing process.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin PET). Fin PET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions of semiconductor transistor devices are formed. A gate is formed over and along the sides of the fin devices (e.g., wrapping) utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. In addition, strained materials in source/drain (S/D) portions of the Fin PET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility. For example, compressive stress applied to a channel of a PMOS device advantageously enhances hole mobility in the channel. Similarly, tensile stress applied to a channel of an NMOS device advantageously enhances electron mobility in the channel.
However, there are challenges to implementation of such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.”
A first fin structure 110 of the p-channel Fin PET 100 includes a first base layer 111 protruding from a substrate 10. In this embodiment, the substrate 10 is a silicon substrate. Alternatively, the substrate 10 may comprise another elementary semiconductor, such as germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe, III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GainAs, GainP, and/or GainAsP; or combinations thereof. In one embodiment, the substrate 10 is a silicon layer of an SOI (silicon-on insulator) substrate. An amorphous substrate such as amorphous Si or amorphous SiC, or insulators such as silicon oxide may also be used as the substrate 10. The substrate 10 may include various regions that have been suitably doped (e.g., p-type or n-type conductivity).
A first intermediate layer 114 is disposed over the first base layer 111 and a first channel layer 115 (p-channel layer) is disposed over the first intermediate layer 114. The first base layer 111 may be made of the same material as the substrate 10 and may continuously extend from the substrate 10. The first intermediate layer 114 includes a first semiconductor layer 112 disposed over the first base layer 111 and a second semiconductor layer 113, which is a first strain layer, disposed over the first semiconductor layer 112. In some embodiments, the first semiconductor layer 112 is a SiGe layer and the second semiconductor layer 113 is a Si layer. The width W1 of the second semiconductor layer 113 is in a range of about 8 nm to about 28 nm in some embodiments. The first channel layer 115 is made of SiGe in some embodiments. Because of the hetero structure of the Si strain layer 113 and the SiGe channel layer 115, a compressive stress is applied to a channel of the p-channel Fin PET. The thickness T1 of the first SiGe layer is in a range of about 2 nm to about 40 nm in some embodiments. The average width of the channel layer 115 is greater than the average width of the first strain layer 113 in some embodiments. At the interface between the first strain layer 113 and the channel layer 115, the width of the channel layer 115 is greater than the width of the first strain layer 113. In some embodiments, the average width of the channel layer 115 may be equal to or smaller than the average width of the first strain layer 113.
A second fin structure 210 of the n-channel Fin PET 200 includes a second base layer 211 protruding from the substrate 10, a second strain layer 212 disposed over the second base layer 211 and a second channel layer 213 (n-channel layer) disposed over the second strain layer
212. The first base layer 211 may be made of the same material as the substrate 10 and may continuously extend from the substrate 10. The second strain layer 212 is made of SiGe and the second channel layer 213 is made of Si in some embodiments. The width W3 of the channel layer 213 is in a range of about 8 nm to about 28 nm in some embodiments. Because of the hetero structure of the SiGe strain layer 212 and the Si channel layer 213, a tensile stress is applied to a channel of the n-channel Fin PET. The thickness T2 of the second strain layer 212 is in a range of about 2 nm to about 40 nm in some embodiments.
In the n-channel Fin PET 200 of the present disclosure, the second strain layer 212 further includes SiGe oxide layers 214 disposed over the side walls of the second strain layer 212. The SiGe oxide layers 214 induce an additional tensile stress to the second channel layer 213. The thickness T3 of the SiGe oxide layer 214 is in a range of about 1 nm to about 10 nm in some embodiments. In certain embodiment, the thickness T3 of the SiGe oxide layer 214 is in a range of about 2 nm to about 5 nm. Since oxygen diffuses faster at the center of the SiGe layer, and thus the center of the SiGe layer is oxidized faster, the SiGe oxide layer 214 becomes an “eye” shape as shown in
In the present disclosure, the shape of the fin structure in the cross section is a tapered shape (e.g., trapezoid). However, the shape is not limited to trapezoid. In some embodiments, the shape of the fin structure in the cross section may be reverse trapezoid, rectangular, mesa, or mixture thereof. A part of the fin structure (e.g., base layer, intermediate layer, strain layer and/or channel layer) may be tapered and/or rectangular. Further, the corners of the fin structures, for example the corners of channel layers, may be rounded.
Each layer of the fin structures is doped with appropriate impurities. For p-channel Fin PET 100, the channel layer 115 is doped with boron (B) or BF2, and for n-channel Fin PET 200, the channel layer 213 is doped with arsenic and/or phosphorous.
The side walls of the first fin structure 110 of the p-channel Fin PET 100 and the side walls of the second fin structure 210 of the n-channel Fin PET 200 are covered by protective layers 140, respectively. The protective layers are made of a material that prevents an underlying layer from oxidizing. In some embodiments, the protective layers are made of silicon nitride (SiN). The thickness T4 of the protective layers is in a range of about 1 nm to about 10 nm in some embodiments. In certain embodiments, the thickness T4 of the protective layers 140 is in a range of about 2 nm to about 5 nm in some embodiments. A height of the first protective layer 140 measured from the substrate is smaller than a height of the second protective layer 240 by a distance in a range of about 10 nm to about 50 nm in some embodiments.
The first fin structure 110 of the p-channel Fin PET 100 and the second fin structure 210 of the n-channel Fin PET 200 are electrically isolated from each other and from adjacent devices by isolation insulating layers 130, respectively. This isolation is called an STI (shallow trench isolation). The isolation insulating layers 130 includes silicon dioxide formed by, for example, a flowable chemical vapor deposition (CVD) in some embodiments.
The p-channel Fin PET 100 further includes a gate dielectric layer 121 and a first gate electrode 120 disposed over the first channel layer 115. A width W2 of the first channel layer 115 covered by the gate electrode 120 may be in a range of about 5 nm to about 40 nm in some embodiments. The n-channel Fin PET 200 also includes the gate dielectric layer 121 and a second gate electrode 220 disposed over the second channel layer 213. A width W3 of the second channel (n-channel) layer 213 covered by the gate electrode 220 may be in a range of about 2 nm to about 20 nm in some embodiments. The material of the gate dielectric layer for the p-channel PET and n-channel PET may be different in some embodiments.
The gate dielectric layer 121 includes a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof.
The gate electrodes 120 and 220 include any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate structure may be formed using a gate-last or replacement gate methodology.
In certain embodiments of the present disclosure, work function adjustment layers 122 and 222 may be interposed between the gate dielectric layers 121 and the gate electrode 120, 220. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel Fin PET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel Fin PET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer.
As shown in
As shown in
By using a patterning process, hard mask patterns 345 of the pad oxide layer 330 and the silicon nitride mask layer 340 are formed, as shown in
As shown in
As shown in
As shown in
The thickness of the protective layers is in a range of about 1 nm to about 10 nm in some embodiments. In certain embodiments, the thickness of the protective layers is in a range of about 2 nm to about 5 nm.
As long as the side walls of the SiGe layers 112 and 212 are fully covered by the protective layers 140, the protective layers do not necessarily cover the entire side walls of the Si base layer 111, 211 and the Si upper layer 113, 213. In other words, the protective layers may partially cover the side walls of the Si base layer 111, 211 and the Si upper layer 113, 213.
Next, as shown in
remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted. The flowable film is cured and annealed more than once at temperatures, such as in a range from about 1000° C. to about 1200° C., and for an extended period, such as 30 hours or more in total. The isolation insulating layers 130 may be formed by SOG. SiO, SiON, SiOCN or fluoride-doped silicate glass (FSG) may be used as the isolation insulating layer in some embodiments.
After forming the isolation insulating layers 130, a thermal process, for example, an anneal process, is performed to improve the quality of the isolation insulating layers. Since the side walls of the SiGe layers 112 and 212 are covered by the protective layers 140, respectively, the SiGe layers 112 and 212 are not oxidized during the thermal process for forming the isolation insulating layers 130.
As shown in
Next, as shown in
Then, a SiGe layer 115 is epitaxially grown on the exposed surface of the Si layer 113 so as to fill the opening 116. The epitaxial growth of the SiGe layer may be performed by using SiH4 and/or SiH2Cl2 and GeH4 as source gases at a temperature in a range of about 500 C to 700 C and at a pressure in a range of about 10 to 100 Torr (about 133 Pa to about 1333 Pa).
The SiGe layer 115 is expressed as SixGe(1-x), where x is in a range of about 0.1 to about 0.9 in some embodiments. Subsequently, an unnecessary SiGe layer and the protective hard mask 350 are removed by, for example, a CMP method, as shown in
After the fin structures 110, 210 are formed, as shown in
The gate dielectric layer 121 is formed by CVD, PVD, ALD e-beam evaporation, or other suitable process. When the gate dielectric layer 121 is silicon oxide, SiH4, Si2H6 and/or Si2Cl6 is used as a source gas. When the gate dielectric layer 121 is silicon nitride, SiH4, Si2H6 and/or Si2Cl6 and NH3 are used as source gases. When the gate dielectric layer 121 is hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide, metal hydride, metal chloride and/or organic metal including Hf, Zr, Al or Ti is used as a source gas.
The gate electrodes 120 and 220 may be formed by a film forming process by using ALD, PVD, CVD, e-beam evaporation, electroplating or other suitable process, and a patterning process. Metal hydride, metal chloride and/or organic metal including Ti, Ta, Co, Si, Zr, Al or W is used as a source gas. Further, the gate electrodes 120 and 220 may be formed separately for the n-channel Fin PET 200 and the p-channel Fin PET 100 which may use different metal layers. The gate structure may be formed using a gate-last or replacement gate methodology.
As shown in
The distance (length L1) that the first protective layer covers the part of the side walls of the strain layer 113 is in a range of about 1 nm to about 10 nm to effectively protect the SiGe layer in some embodiments. In certain embodiments, the distance L1 is in a range of about 2 to about 5 nm. The distance (space L2) between the first protective layer 140A and the first channel layer 115A is in a range of about 2 nm to about 20 nm in some embodiment, allowing the width of the channel layer to be smaller. In certain embodiments, the distance L2 is in a range of about 4 nm to about 10 nm.
In this embodiment, a width W1 of the first channel layer covered by the gate electrode 120 is at most about 40 nm in some embodiments. In certain embodiments, the width W is at most about 30 nm. At the interface between the strain layer 113 and SiGe channel layer 115A, the width of the SiGe channel layer 115A is greater than the width of the strain layer 113. In some embodiments, the average width of the channel layer 115A may be equal to or smaller than the average width of the strain layer 113.
Similarly, in the n-channel Fin PET 200A, the protective layer 214 covers only the bottom portion of the strain layer 213 by a distance in a range of about 1 nm to about 10 nm in some embodiments. In certain embodiments, this distance is in a range of about 2 to about 5 nm.
In this embodiment, the height of the first protective layer 140A is substantially equal to the height of the second protective layer 240A. Here, “substantially equal” means that a difference is less than 2-3 nm. When the depths of the fin structures are not uniform, the height from the substrate may be measured from the plane that corresponds to the average depths of the fin structures.
The manufacturing method of the Fin PET of the second embodiment includes the same steps shown in
After the fin structures shown in
Then, as shown in
Instead of etching-back the thick resist layer, it may be possible to form a thin sacrificial layer of the photo resist having the thickness T1 directly by adjusting, for example, the spin coating condition. The photo resist layer may be replaced with any organic resin (e.g., non-photosensitive resins) layer or inorganic layer. A material for a bottom anti-reflection coating may be used.
Next, as shown in
The remaining sacrificial layer 360 is removed by, for example, an ashing process and/or a wet cleaning process. Similar to
After the removal of the part of the protecting layer, a height of the first protective layer 140A and a height of the second protective layer 240A are substantially equal to each other.
Then, similar to
In this embodiment, since it is not necessary to etch the SiN protective layer when forming the opening 117, the width of the opening 117 can be made smaller.
Then, a SiGe layer 117 is epitaxially grown on the exposed surface of the Si layer 113 so as to fill the opening 117. Subsequently, an unnecessary SiGe layer and the protective hard mask 350 are removed by, for example, a CMP method, as shown in
After the fin structures 110A, 210A are formed as shown in
After the fin structures shown in
Then, similar to
In another embodiment, a thin insulating layer having the thickness T1 is formed directly by adjusting, for example, the deposition condition in LPCVD, plasma CVD, flowable CVD or an SOG method.
Next, as shown in
After the SiN protective layers are partially removed, an additional insulating layer 380 is deposited on the remaining insulating layer 370, by and a planarization process by using a CMP process is performed, as shown in
After the completion of the process shown in
In this embodiment, as shown in
The various embodiments described herein offer several advantages over the existing art. For example, in the present disclosure, since the intermediate SiGe layers in the fin structures are covered by protective layers (e.g., SiN) for preventing oxidation, oxidation of the SiGe layers in the subsequent heating process such as annealing can be effectively prevented. In addition, it is possible to prevent strain relaxation and fin bending which would occur in the subsequent heating process. Further, by removing the protective layers before forming an opening for the p-channel SiGe layer, it is possible to further reduce the width of the fin structure for the p-channel Fin PET.
It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments, and other embodiments may offer different advantages.
In accordance with one aspect of the present disclosure, a semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a protective layer made of a material that prevents an underlying layer from oxidizing. The intermediate layer includes a first semiconductor layer disposed over the base layer (the lower layer), and the protective layer covers at least side walls of the first semiconductor layer and the base layer.
In accordance with another aspect of the present disclosure, a semiconductor device includes a first fin structure for a first PET and a second fin structure for a second fin PET. The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure also includes a first protective layer made of a material that prevents an underlying layer from oxidizing. The second fin structure includes a second base layer protruding from the substrate, a second intermediate layer disposed over the second base layer and a second channel layer disposed over the second intermediate layer. The second fin structure also includes a second protective layer covering side walls of the second base layer, side walls of the second intermediate layer and side walls of the second channel layer. The first channel layer is made of SiGe. The first intermediate layer includes a first semiconductor layer disposed over the first base layer and a second semiconductor layer disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of a part of the second semiconductor layer.
In accordance with yet another aspect of the present disclosure, a method for manufacturing a semiconductor device includes the following steps. A fin structure including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer is formed. A protective layer is formed over at least side walls of the fin structure to cover side walls of the intermediate layer and the lower layer. The protective layer is made of a material that prevents an underlying layer from oxidation. An isolation insulating layer is formed so that the fin structure, including the lower layer, the intermediate layer, the upper layer and the protective layer is embedded in the isolation insulating layer. A part of the upper layer and the isolation insulating layer are removed so that an opening is formed in the isolation insulating layer. A channel layer is formed in the opening.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Tsai, Teng-Chun, Yang, Feng-Cheng, Hsu, Chia-Jung, Huang, Gin-Chen, Hsu, Tzu-Hsiang
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
7425740, | Oct 07 2005 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
7667271, | Apr 27 2007 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
8048723, | Dec 05 2008 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
8053299, | Apr 17 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
8183627, | Dec 01 2004 | Taiwan Semiconductor Manufacturing Company, Ltd | Hybrid fin field-effect transistor structures and related methods |
8362575, | Sep 29 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling the shape of source/drain regions in FinFETs |
8367498, | Oct 18 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
8415718, | Oct 30 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming epi film in substrate trench |
8440517, | Oct 13 2010 | MOSAID TECHNOLOGIES INC | FinFET and method of fabricating the same |
8497177, | Oct 04 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
8497528, | May 06 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
8609518, | Jul 22 2011 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-growing source/drain regions from un-relaxed silicon layer |
8610240, | Oct 16 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit with multi recessed shallow trench isolation |
8618556, | Jun 30 2011 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design and method of fabricating same |
8633516, | Sep 28 2012 | Taiwan Semiconductor Manufacturing Company, Ltd | Source/drain stack stressor for semiconductor device |
8680576, | May 16 2012 | Taiwan Semiconductor Manufacturing Company, Ltd | CMOS device and method of forming the same |
8703565, | Feb 09 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-notched SiGe FinFET formation using condensation |
8723272, | Oct 04 2011 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
8729627, | May 14 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
8729634, | Jun 15 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
8742509, | Mar 01 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for FinFETs |
8776734, | May 19 2008 | Innovative Environmental Solutions, LLC; INNOVATIVE ENVIRONMENTAL SOLUTIONS, LLC DBA REMEDIATION SERVICE, INT L | Remedial system: a pollution control device for utilizing and abating volatile organic compounds |
8785285, | Mar 08 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
8796666, | Apr 26 2013 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
8796759, | Jul 15 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
8809139, | Nov 29 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-last FinFET and methods of forming same |
8815712, | Dec 28 2011 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
8828823, | Oct 13 2011 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
8836016, | Mar 08 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
8841701, | Aug 30 2011 | Taiwan Semiconductor Manufacturing Company, Ltd.; Taiwan Semiconductor Manufacturing Company, Ltd | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
8847293, | Mar 02 2012 | Taiwan Semiconductor Manufacturing Company, Ltd | Gate structure for semiconductor device |
8853025, | Feb 08 2013 | Taiwan Semiconductor Manufacturing Company | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
20050035391, | |||
20070221956, | |||
20110068407, | |||
20110108920, | |||
20130011983, | |||
20130196478, | |||
20130285153, | |||
20140138770, | |||
20140183600, | |||
20140197457, | |||
20140252412, | |||
20140264590, | |||
20140264592, | |||
20140335673, | |||
20150097239, | |||
20150228499, | |||
20150279734, | |||
20160035872, | |||
KR100496891, |
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