The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.
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1. A method for forming a semiconductor device, comprising:
etching a first and a second source/drain structures on a first and a second fin structures in a first and a second active region, respectively, on a substrate by an etching gas mixture including a sulfur containing passivation gas, wherein the etching gas mixture etches the first source/drain structure at a faster etching rate than etching the second source/drain structure, the etching forming the first source/drain structure in the first active region having a first vertical height less than a second vertical height formed in the second source/drain structure in the second active region, wherein the first source/drain structure is n-type and the second source/drain structure is p-type.
8. A method for forming a semiconductor device, the method comprising:
forming a first fin on a substrate;
forming a second fin on the substrate;
epitaxially growing a first source/drain region on the first fin;
epitaxially growing a second source/drain region on the second fin, wherein the first source/drain region has a first vertical height greater than a second vertical height of the second source/drain region;
forming a first dielectric layer over the first source/drain region and the second source/drain region; and
etching the first dielectric layer, the first source/drain region and the second source/drain region, wherein the etching etches the first source/drain region at a faster rate than the second source/drain region, wherein the etching exposes an outer sidewall of the first source/drain region.
15. A method for forming a semiconductor device, the method comprising:
forming a first fin on a substrate;
forming a second fin on the substrate;
epitaxially growing a first source/drain region on the first fin;
epitaxially growing a second source/drain region on the second fin;
forming a first dielectric layer over the first source/drain region and the second source/drain region;
forming a first opening and a second opening in the first dielectric layer, wherein forming the first opening and the second opening comprises etching the first dielectric layer, the first source/drain region and the second source/drain region, wherein the etching etches the first source/drain region at a faster rate than the second source/drain region; and
forming a first contact in the first opening and a second contact in the second opening, wherein a first contact area between the first contact and the first source/drain region is greater than a second contact area between the second contact and the second source/drain region, wherein the first contact has a point that abuts the first source/drain region, the point being above the first fin, wherein the first contact extends laterally from the point to an outermost edge of the first source/drain region in a direction perpendicular to the first fin.
2. The method of
4. The method of
prior to etching the first and the second source/drain structures, forming a third source/drain structure neighboring the first source/drain structure in the first active region, and forming a fourth source/drain structure neighboring the second source/drain structure in the second active region, wherein the third source/drain structure has a third vertical height greater than a fourth vertical height of the fourth source/drain structure.
5. The method of
6. The method of
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
the carbon fluorine gas is CF4,
the oxygen containing gas is O2,
the inert gas is Ar, and
and the passivation gas is COS.
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
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This application claims the benefit of U.S. Provisional Application No. 62/591,265, filed on Nov. 28, 2017, which application is hereby incorporated herein by reference.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three dimensional designs, such as fin field effect transistors (FinFETs). A typical FinFET is fabricated with a fin structure extending from a substrate, for example, by etching into a silicon layer of the substrate. The channel of the FinFET is formed in the vertical fin. A gate structure is provided over (e.g., overlying to wrap) the fin structure. It is beneficial to have a gate structure on the channel allowing gate control of the channel around the gate structure. FinFET devices provide numerous advantages, including reduced short channel effects and increased current flow.
As the device dimensions continue scaling down, FinFET device performance can be improved by using a metal gate electrode instead of a typical polysilicon gate electrode. One process of forming a metal gate stack is forming a replacement-gate process (also called as a “gate-last” process) in which the final gate stack is fabricated “last”. However, there are challenges to implement such IC fabrication processes in advanced process nodes. Inaccurate and improper control of the deposition and patterning process during the device structure fabrication may adversely deteriorate electrical performance of the device structures.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure is generally related to semiconductor devices, and more particularly to replacement gates formed in semiconductor devices. The present disclosure provides methods for forming source/drain structures with asymmetric profiles at different locations of the semiconductor device so as to engineer electrical performance of the semiconductor devices. In one example, the asymmetric profiles of the source/drain structures may be obtained by forming the source/drain structures with different dimensions and profiles. In another example, the asymmetric profiles of the source/drain structures may be obtained by patterning the source/drain structures using etchants with high selectivity so as to selectively trim and/or pattern the source/drain structures at different active regions with different patterning rates, rendering different resultant profiles of the source/drain structures at different locations after the patterning process. Asymmetric profiles of the source/drain structures allow different electrical performance in different active regions (e.g., p-type or n-type regions) of the semiconductor devices so as to provide a flexible engineering window for device electrical performance adjustment and alternation. Implementations of some aspects of the present disclosure may be used in other processes, in other devices, and/or for other layers. For example, other example devices can include planar FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other devices. Some variations of the example methods and structures are described. A person having ordinary skill in the art will readily understand other modifications that may be made that are contemplated within the scope of other embodiments. Although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein.
In a replacement gate process for forming a metal gate for a transistor, a dummy gate stack is formed over a substrate as a placeholder for an actual gate stack later formed thereon. A spacer structure is formed surrounding the dummy gate stack. After source/drain features are formed, a contact etch stop layer (CESL) and interlayer dielectric (ILD) layer are formed adjacent to the spacer structure, the dummy gate stack is removed, leaving an opening surrounded by the spacer structure, CESL and ILD layer. Then, a metal gate is formed in the opening defined by the spacer structure, CESL, and ILD.
The metal gate structure includes a gate dielectric layer, such as a high-k dielectric layer, an optional barrier layer, a work-function tuning layer, and a gate metal electrode. Multiple deposition and patterning processes may be used to form the work-function tuning layer, for example, to fine tune threshold voltage (Vt) of the transistor. In some embodiments, the work-function tuning layer may utilize different materials for different types of transistors, such as p-type FinFET or n-type FinFET, so as to enhance device electrical performance as needed. The barrier layer is optionally used to protect the gate dielectric layer during the patterning processes.
The simplified FINFET device structure 201 depicted in
Each fin structure 24 provides an active region where one or more devices are formed. The fin structures 24 are fabricated using suitable processes including masking, photolithography, and/or etch processes. In an example, a mask layer is formed overlying the substrate 20. The photolithography process includes forming a photoresist layer (resist) overlying the mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to pattern the photoresist layer. The pattern of the photoresist layer is transferred to the mask layer using a suitable etch process to form a masking element. The masking element may then be used to protect regions of the substrate 20 while an etch process forms recesses 25 in the substrate, leaving an extending fin, such as the fin structures 24. The recesses 25 may be etched using reactive ion etch (RIE) and/or other suitable processes. Numerous other embodiments of methods to form a fin structure on a substrate may be utilized.
In an embodiment, the fin structures 24 are approximately 10 nanometer (nm) wide and in a range from approximately 10 nm to 60 nm in height, such as about 50 nm high. However, it should be understood that other dimensions may be used for the fin structures 24. In one example, the fin structures 24 comprise a silicon material or another elementary semiconductor, such as germanium, or a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. The fin structures 24 may also be an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. Further, the fin structures 24 may be doped using n-type and/or p-type dopants as needed.
As described, in an example, the plurality of fin structures 24 may be formed by etching a portion of the substrate 20 away to form the recesses 25 in the substrate 20. The recesses 25 may then be filled with isolating material that is recessed or etched back to form isolation structures 26. Other fabrication techniques for the isolation structures 26 and/or the fin structure 24 are possible. The isolation structures 26 may isolate some regions of the substrate 20, e.g., active areas in the fin structures 24. In an example, the isolation structures 26 may be shallow trench isolation (STI) structures and/or other suitable isolation structures. The STI structures may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating material. The STI structures may include a multi-layer structure, for example, having one or more liner layers.
A dummy gate structure 50 is formed over the fin structures 24. In the example depicted in
The term, “dummy”, as described here, refers to a sacrificial structure which will be removed in a later stage and will be replaced with another structure, such as a high-k dielectric and metal gate structure in a replacement gate process. The replacement gate process refers to manufacturing a gate structure at a later stage of the overall gate manufacturing process. The gate dielectric layer 28 can be a dielectric oxide layer. For example, the dielectric oxide layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. The gate electrode layer 30 may be a poly-silicon layer or other suitable layers. For example, the gate electrode layer 30 may be formed by suitable deposition processes such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD). The hard mask 32 may be any material suitable to pattern the dummy gate structure 50 with desired features/dimensions on the substrate.
In an embodiment, the various layers of the dummy gate structure 50 are first deposited as blanket layers. Then, the blanket layers are patterned through a process including photolithography and etching processes, removing portions of the blanket layers and keeping the remaining portions over the isolation structures 26 and the fin structures 24 to form the dummy gate structure 50.
In an example, the semiconductor device structure 201 includes a n-type region 202a and an p-type region 202b. One or more p-type devices, such as p-type FinFETs, may be formed in the n-type region 202a, and one or more n-type devices, such as n-type FinFETs, may be formed in the p-type region 202b. The semiconductor device structure 201 may be included in an IC such as a microprocessor, memory device, and/or other IC.
Referring back to the process 100 depicted in
At operation 104, an isolation structure 26 is formed in each recess 25, as shown in
At operation 106, upper portions of the fin structures 24 in the p-type region 202b are removed and replaced with another material, as shown in
In one example, the heteroepitaxial fin structures 602 have a thickness between about 30 nm and about 100 nm.
In one example, the heteroepitaxial fin structures 602 may be silicon germanium (SixGe1-x, where x can be between approximately 0 and 100), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. In one specific example, the heteroepitaxial fin structures 602 include a SiGe material.
At operation 108, the insulation structures 26 are recessed to form recesses 702 above the insulation structures 26, as shown in
At operation 110, a dummy gate structure 50 is formed on the substrate, as depicted in
In some embodiments, after forming the dummy gate structure 50, lightly doped drain (LDD) regions (not specifically illustrated) may be formed in the active areas. For example, dopants may be implanted into the active areas (e.g., fin structures 24 or heteroepitaxial fin structures 602) using the dummy gate structures 50 as masks. Example dopants can include or be, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. The LDD regions may have a dopant concentration in a range from about 1015 cm−3 to about 1017 cm−3.
At operation 112, a first mask layer 902 is formed on a first region, such as the p-type region 202b, of the substrate 20, as shown in
In one example, the first mask layer 902 may be formed by any suitable deposition process. In one specific example, the first mask layer 902 may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. A photoresist may then be formed over the first mask layer 902 in the p-type region 202b, and an anisotropic etch process may be performed on the first mask layer 902 in the n-type region 202a to form the spacer features and expose portions of the fin structures 24 in the n-type region 202a while maintaining the first mask layer 902 in the p-type region 202b. The photoresist may then be removed in an ashing or wet strip processes, for example.
At operation 114, an epitaxial deposition process is performed to grow an n-type epi-material 304 onto the fin structure 24 in the n-type region 202a, as shown in
In some examples, the n-type epi-material 304 formed on each fin structure 24 may or may not be merged. Although the example depicted in
In one example, the n-type epi-material 304 may include n-type doped silicon material formed on the fin structures 24 in the n-type region 202a. Suitable example n-type dopants that may be utilized for the n-type epi-material 304 include phosphorus (P), arsenic (As), antimony (Sb), or the like. The n-type epi-material 304 is formed by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. The n-type epi-material 304 may be in situ doping during epitaxial growth and/or by implanting dopants into the epitaxy source/drain regions. The n-type epi-material 304 may have a dopant concentration in a range from about 1019 cm−3 to about 5×1022 cm−3. Hence, a source/drain region may be delineated by doping (e.g., by implantation and/or in situ during epitaxial growth, if appropriate) and/or by epitaxial growth, if appropriate, which may further delineate the active area in which the source/drain region is delineated.
In one specific example, the n-type epi-material 304 is a silicon material or phosphorus (P) doped silicon material (SixPy) or the like.
In one embodiment, the n-type epi-material 304 may be formed having a first vertical height 302 from a surface 306 of the isolation structure 26 to a top 305 of the n-type epi-material 304, as shown in
At operation 116, the first mask layer 902 is removed from the substrate 20, as shown in
At operation 118, similar to the first mask layer 902, a second mask layer 310 is formed on the n-type region 202a of the substrate 20, as shown in
It is noted that the second hard mask 310 as well as the first hard mask 902 may be mostly and/or entirely removed from the substrate, thus leaving no spacer features formed on the substrate at this stage. In this particular embodiment, new spacer features with desired conformality may be later formed after operation 122 but prior to the operation 124. New spacer features may be formed by suitable deposition techniques prior to forming an contact etching stop layer (CESL) 318 and a first interlayer dielectric (ILD) layer 342 at operation 124, which will be described in greater detail below in
At operation 120, an epitaxial deposition process is performed to grow a p-type epi-material 312 onto the heteroepitaxial fin structures 602, as shown in
In some examples, the p-type epi-material 312 formed on each heteroepitaxial fin structures 602 may or may not be merged. Although the example depicted in
In one example, the p-type epi-material 312 may include p-type doped silicon material formed on the heteroepitaxial fin structures 602 in the p-type region 202b. Suitable example p-type dopants or suitable dopants that may be utilized for p-type epi-material 312 include boron (B), gallium (Ga), aluminum (Al), germanium (Ge) or the like. The p-type epi-material 312 is formed by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. The p-type epi-material 312 may be in situ doping during epitaxial growth and/or by implanting dopants into the epitaxy source/drain regions. The p-type epi-material 312 may have a dopant concentration in a range from about 1019 cm−3 to about 5×1022 cm−3. Hence, a source/drain region may be delineated by doping (e.g., by implantation and/or in situ during epitaxial growth, if appropriate) and/or by epitaxial growth, if appropriate, which may further delineate the active area in which the source/drain region is delineated.
In one specific example, the p-type epi-material 312 is a silicon germanium (SiGe) or boron (B) doped silicon material (SixBy) or the like.
In one embodiment, the p-type epi-material 312 may be formed having a second vertical height 320 from the surface 306 of the isolation structure 26 to a top 314 of the p-type epi-material 312, as shown in
It is noted that the first vertical height 302 and the second vertical height 320 of the n-type epi-material 304 and the p-type epi-material 312 may be individually controlled to be formed at different ranges for different electrical performance requirements. For example, the first vertical height 302 of the n-type epi-material 304 may be configured to be greater (e.g., higher) than the second vertical height 320 of the p-type epi-material 312. It is believed that the greater height of the first vertical height 302 of the n-type epi-material 304 in the n-type region 202a may provide a semiconductor device with higher electron mobility, device speed and lower RC (e.g., lower contact resistance), as the electrical performance of the n-type region 202a is controlled by electrons (e.g., typically have greater conductivity), rather than the holes in the p-type region 202b. Thus, by forming the n-type epi-material 304 having the first vertical height 302 greater than the second vertical height 320 of the p-type epi-material 312, the electrical device performance of the semiconductor devices may be adjusted and altered as needed. In one example, the greater height of the first vertical height 302 of the n-type epi-material 304 may be obtained by adjusting deposition time during the epitaxial deposition process at operation 114 and 120.
In one example, the first vertical height 302 of the n-type epi-material 304 is controlled to be in a range from about 8% to about 20%, such as about 10%, greater than the second vertical height 320 of the p-type epi-material 312.
Furthermore, the greater height (e.g., dimension) of the n-type epi-material 304 is also believed to provide a greater contact surface area (e.g., greater conductive surface area) when later in contact with a conductive feature in a contact trench fabrication process. Details regarding the conductive feature in the contact trench fabrication process will be described later below with reference to
At operation 122, similar to the removal of the first mask layer 902, the second mask layer 310 is removed from the substrate 20, as shown in
At operation 124, a contact etching stop layer (CESL) 318 and a first interlayer dielectric (ILD) layer 342 are sequentially formed on the substrate 20, as shown in
The first ILD layer 342 is formed over the CESL 318, as shown in
At operation 126, subsequently, the dummy gate structure 50 is removed from the substrate 20 to allow a replacement gate structure 55, such as a metal gate structure, to be formed therein to continue manufacturing the semiconductor device structure 201, as shown in
At operation 128, a second interlayer dielectric (ILD) layer 344 is formed on the first ILD layer 342 covering the replacement gate structure 55, as depicted in
At operation 130, a contact trench 57 is formed through the second ILD layer 344, the first ILD layer 342 and the CESL 318 to expose at least portions of a portion of the p-type epi-material 312 (shown as 312a, 312b, 312c, 312d in
In one example, the contact trench 57 may be formed by an etching process that may efficiently control the selective etching rate to the p-type epi-material 312a, 312b, 312c, 312d over the n-type epi-material 304a, 304b, 304c, 304d. The etching process is controlled to etch a portion of the p-type epi-material 312b, 312c and n-type epi-material 304b, 304c away from the substrate 20, as shown particularly in
It is believed that the recesses 62b, 62c, 64b, 64c increase the overall surface area (e.g., from a facet top 314 or a round top 305 to substantially flat top surfaces 72b, 72c, 74b, 74c) in contact with a conductive feature later formed therearound, so that the electrical performance of the semiconductor device may be adjusted and altered as needed. The greater epi-material loss often creates the greater surface area exposed for the source/drain structures to be contact with the conductive feature, thus enhancing the electrical performance of the semiconductor device, such as low contact resistance (RC). Thus, a step height 352, 354 is defined between the top 305, 314 and a top surface 72b, 74b of the n-type and p-type epi-materials 304b, 312b respectively in
As discussed above, higher flow flux of the electrons in the n-type region 202a (from the n-type dopants) often creates higher electron mobility, current flow and low contact resistance in the semiconductor device, thus enhancing the electrical performance, particularly in NMOS. As a result, a higher step height 352 over the n-type epi-material 304b in the n-type region 202a is desired. In one example, the step height 352 in the n-type region 202a is at least about 5% higher, such as about at least 10% higher, than the step height 354 in the p-type region 202b. In one specific example, the step height 352 in the n-type region 202a is at least about 10%, and more particularly, at least about 20%, higher than the step height 354 in the p-type region 202b. As the step height 352 in the n-type region 202a is higher than the step height 354 in the p-type region 202b, the remaining height 353 (in vertical direction) of the n-type epi-material 304b in the n-type region 202a is less than the remaining height 355 (in vertical direction) of the p-type epi-material 312b in the p-type region 202b.
In one example, the step height 352 in the n-type region 202a is in a range from about 10 nm to about 20 nm and the step height 354 in the p-type region 202b is in a range from about 0.1 nm to about 5 nm.
In one example, the step height 352 (Hn) and the step height 354 (Hp) may have a height ratio (Hn/Hp) greater than 1.1 when the first height 302 (H1) and the second height 320 (H2) have a height ratio (H1/H2) in a range from 0.9-1.1. In another example, the step height 352 (Hn) and the step height 354 (Hp) may have a height ratio (Hn/Hp) in a range from 0.9-1.1 when the first height 302 (H1) and the second height 320 (H2) have a height ratio (H1/H2) greater than 1.1. In yet another example, the step height 352 (Hn) and the step height 354 (Hp) may have a height ratio (Hn/Hp) greater than 1.1 when the first height 302 (H1) and the second height 320 (H2) have a height ratio (H1/H2) greater than 1.1. It is noted that the height ratio between the step heights 352, 354 (Hn, Hp) or between the first and the second height 302, 320 (H1, H2) may be in any ratio combinations as described above.
In one example, step height 352 (Hn) and the step height 354 (Hp) may have a height ratio (Hn/Hp) greater than 1.1. In another example, the step height 352 (Hn) and the step height 354 (Hp) may have a height ratio (Hn/Hp) in a range from 0.9-1.1. In yet another example, the first height 302 (H1) and the second height 320 (H2) have a height ratio (H1/H2) in a range from 0.9-1.1. In still another example, the first height 302 (H1) and the second height 320 (H2) have a height ratio (H1/H2) greater than 1.1. It is noted that the height ratio between the step heights 352, 354 (Hn, Hp) or between the first and the second height 302, 320 (H1, H2) may be in any ratio combinations as described above.
In one embodiment, the etching process utilized to form the contact trench 57 may be a plasma etching process. The plasma etching process may be performed by supplying an etching gas mixture into a plasma processing chamber in which the substrate 20 may be placed. The etching gas mixture may include a carbon fluorine gas, an oxygen containing gas, an inert gas, and a passivation gas. The passivation gas supplied in the etching gas mixture is configured to form a passivation layer over the p-type epi-materials 312b while etching predominately the n-type epi-materials 304b so that the n-type epi-materials 304b may be etched at an etching rate greater than the etching rate for etching the p-type epi-materials 312b. In one example, the passivation gas is a sulfur containing gas. It is believed that the sulfur elements from the passivation gas may react with the germanium elements in the SiGe from the p-type epi-materials 312b, 312c so as to form the passivation layer on the p-type epi-materials 312b, 312c during the patterning process. As a result, the aggressive etchants from the carbon fluorine gas may predominately etch the n-type epi-materials 304b, 304c in the n-type region 202a, resulting in the greater step height 352 in the n-type region 202a, while leaving the p-type epi-materials 312b, 312c in the p-type region 202b protected by the sulfur containing passivation layer. In one example, the passivation gas in the etching gas mixture is carbonyl sulfide (COS) and the like. Suitable examples of the carbon fluorine gas include CF4, C2F2, CHF3, CH3F, C2F6, C4F6, C4F8 and the like. In one example, the etching gas mixture includes CF4, O2, Ar and COS.
During the etching process, the substrate temperature may be controlled at greater than room temperature, such as greater than 60 degrees Celsius, such as in a range from 60 degrees Celsius to 150 degrees Celsius, for example, particular from 80 degrees Celsius and about 140 degrees Celsius.
As discussed above, it is noted that the electrical performance of the semiconductor device may be adjusted in the operation 130 by utilizing a patterning gas mixture with high selectivity that provides different etch rates to etch the n-type and p-type epi-materials 304, 312 respectively. As a result, the recesses 62b, 62c, 64b, 64c are formed in portions of the n-type and p-type epi-materials 304, 312. The recesses 62b, 62c, 64b, 64c formed on the n-type and p-type epi-materials 304, 312 create greater exposed contact surface area to be in contact with the conductive feature later formed thereon so as to enhance electrical performance of the semiconductor devices. Similarly, as discussed above in operation 114 and 120, different deposition times may be utilized at operations 114 and 120 respectively to grow the n-type and p-type epi-materials 304, 312 with different first and the second vertical heights 302, 320 so that the electrical performance may also be enhanced by grow a greater first vertical height 302 (e.g., greater dimension of the epi-materials that create greater contact surface area) of the n-type epi-material 304 to increase electron mobility, electron current density and reduce contact resistance.
In some examples, the first vertical height 302 and the second vertical height 320 of the n-type and p-type epi-materials 304, 312 may be configured to be substantially similar at operations 114 and 120 while providing a selective etching process at operation 130 to predominately etching the n-type epi-material 304 to provide the recess 62b, 62c with the step height 352 in the n-type region 202a greater than the step height 354 in the p-type region 202b so as to provide a greater surface contact area (e.g., greater loss in the n-type epi-material 304) to the conductive feature later formed thereon.
In other examples, the etching process at operation 130 may be configured to have a substantially similar etching rate over the n-type and p-type epi-materials 304, 312 so that the step heights 352, 354 are substantially similar while the first height 302 of the n-type epi-material 304 formed from operation 114 is configured to be greater than the second height 320 of the p-type epi-material 312 formed from the operation 120 by different deposition time management. Thus, a greater contact surface area in the n-type epi-material 304 may also be obtained due to the greater first vertical height 302 in the n-type epi-material 304 compared to the second vertical height 320 in the p-type epi-materials 312 due to the different dimension/profile of the n-type and p-type epi-material 304, 312.
In yet another example, the electrical performance may be adjusted and enhanced by doing both above, including adjusting the deposition time at operation 112 and 120 to grow first vertical height 302 of the n-type epi-material 304 greater than the second vertical height 320 of the p-type epi-material 312 (e.g., increase of the surface contact area) and also forming the step height 352 in the n-type region 202a greater than the step height 354 in the p-type region 202b (e.g., also increase of the surface contact area).
At operation 132, a first metal silicide layer 398 is then formed on the n-type epi-material 304b, 304c, and a second metal silicide layer 399 is formed on the p-type epi-material 312b, 312c. A conductive feature 60 is then formed on the first and second metal silicide layers 398, 399 filling the contact trench 57, as shown in
It is noted that after the first and second metal silicide layers 398, 399 are formed, the conductive feature 60 formed in the contact trench 57 may include an adhesion layer (not shown), a barrier layer (not shown) on the adhesion layer, and a conductive material (not shown) on the barrier layer, for example, in total referred as the conductive feature 60 in the contact trench 57. The first and second metal silicide layers 398, 399 may be formed on the exposed surface defined by the recesses 62b, 62c, 64b, 64c defined on the n-type and p-type epi-materials 304b, 304c, 312b, 312c of the epitaxy source/drain regions by reacting upper portions of the n-type and p-type epi-materials 304b, 304b, 312b, 312c with the adhesion layer (not shown) and possibly, the barrier layer (not shown). The conductive material can be deposited on the barrier layer and fill the contact trench 57, forming the conductive feature 6o. After the conductive material is deposited, excess conductive material, barrier layer, and adhesion layer may be removed by using a planarization process, such as a CMP, for example. The planarization process may remove excess conductive material, barrier layer, and adhesion layer from above a top surface of the second ILD layer 344. Hence, top surfaces of the conductive feature 60 and the second ILD layer 344 may be substantially coplanar. The conductive feature 60 may be or may be referred to as contacts, plugs, etc.
Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure can provide methods for forming asymmetric source/drain structures in different regions of the substrate so as to enhance the electrical performance of the semiconductor devices. The asymmetric source/drain structures may be obtained by epi-growing n-type epi-material in the n-type region with different profiles from the p-type epi-material in the p-type region. Furthermore, the asymmetric source/drain structures may also be obtained by utilizing a selective etching process to predominantly etch n-type epi-material in the n-type region to create greater etch n-type epi-material loss (e.g., greater surface area exposed to the conductive feature in the contact trench) so as to enhance the electrical performance. The asymmetric source/drain structures may be obtained by performing either one of the above process or both as needed.
In one embodiment, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures. In an embodiment, the first group of the source/drain structures further includes a third source/drain structure having a third vertical less than the first vertical height of the first source/drain structure. In an embodiment, the second group of the source/drain structures further includes a fourth source/drain structure having a fourth vertical height less than the second vertical height of the second source/drain structure. In an embodiment, the third vertical height of the third source/drain structure is less than the fourth vertical height of the fourth source/drain structure. In an embodiment, a first step height is defined between the first vertical height and the third vertical height and a second step height is defined between second vertical height and the fourth vertical height, wherein the first step height is at least about 5% higher than the second step height. In an embodiment, a first metal silicide layer is on the third source/drain structures and a second metal silicide layer on the fourth source/drain structures, wherein the first metal silicide layer has a contact surface area greater than a contact surface area of the second metal silicide layer. In an embodiment, a first and a second conductive features is formed on the first and the second metal silicide layers respectively. In an embodiment, the third source/drain structure has a surface area greater than a surface area of the fourth source/drain structure. In an embodiment, the first vertical height of the first source/drain structure is about 8% and about 20% greater than the second vertical height of the second source/drain structure. In an embodiment, the first group of source/drain structures comprises n-type epi-material, and the second group of the source/drain structures comprises p-type epi-material.
In another embodiment, a semiconductor device includes a first active area and a second active area on a substrate, wherein the first active area comprises a first source/drain structure formed over a first fin structure, and the second active area comprises a second source/drain structure over a second fin structure, a gate structure over the first and the second fin structures, the first and second source/drain structures being proximate the gate structure, a first metal silicide layer on the first source/drain structure in the first active area, a second metal silicide layer on the second source/drain structure in the second active area and a first and second conductive features on the first and the second metal silicide layers respectively, wherein the first metal silicide layer has a first contact surface area to the conductive feature greater than a second contact surface area of the second metal silicide layer to the conductive feature. In an embodiment, the first source/drain structure has a first surface area contacting the first metal silicide layer greater than a second surface area of the second source/drain structure contacting the second metal silicide layer. In an embodiment, the second source/drain structure in the second active area has a second vertical height greater than a first vertical height of the first source/drain structure in the first active area. In an embodiment, a third source/drain structure is formed neighboring the first source/drain structure in the first active area and a fourth source/drain structure is formed neighboring the second source/drain structure in the second active area, wherein the third source/drain structure has a third vertical height greater than a fourth vertical height of the fourth source/drain structure. In an embodiment, a first step height is defined between the third vertical height and the first vertical height in the first active area and a second step height is defined between the fourth vertical height and the second vertical height in the second active area, wherein the first step height is at least about 5% higher than the second step height.
In yet another embodiment, a method for forming a semiconductor device includes etching a first and a second source/drain structures on a first and a second fin structures in a first and a second active region, respectively, on a substrate by an etching gas mixture including a sulfur containing passivation gas, wherein the etching gas mixture etches the first source/drain structure at a faster etching rate than etching the second source/drain structure, the etching forming the first source/drain structure in the first active region having a first vertical height less than a second vertical height formed in the second source/drain structure in the second active region. In an embodiment, the sulfur containing passivation gas selectively reacts with the second source/drain structure in the second active region, forming a passivation layer on the second source/drain structure while patterning the first source/drain structure in the first active region. In an embodiment, the sulfur containing passivation gas is carbonyl sulfide. In an embodiment, prior to etching the first and the second source/drain structures, a third source/drain structure is formed neighboring the first source/drain structure in the first active region, and a fourth source/drain structure is formed neighboring the second source/drain structure in the second active region, wherein the third source/drain structure has a third vertical height greater than a fourth vertical height of the fourth source/drain structure. In an embodiment, a first step height is defined between the third vertical height and the first vertical height in the first active area, and a second step height is defined between the fourth vertical height and the second vertical height in the second active area, wherein the first step height is at least about 5% higher than the second step height.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
5376234, | Jun 29 1992 | Sony Corporation | Dry etching method |
7923784, | Dec 30 2008 | Hynix Semiconductor Inc. | Semiconductor device having saddle fin-shaped channel and method for manufacturing the same |
9093530, | Dec 28 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
9171929, | Apr 25 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
9214555, | Mar 12 2013 | TAIWAN SEMICONDUCTOR MANUFACTURING CO , LTD | Barrier layer for FinFET channels |
9564489, | Jun 29 2015 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple gate field-effect transistors having oxygen-scavenged gate stack |
9601342, | Mar 08 2013 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with strained well regions |
9608116, | Feb 12 2015 | Taiwan Semiconductor Manufacturing Company, Ltd | FINFETs with wrap-around silicide and method forming the same |
20120289050, | |||
20140085966, | |||
20140252477, | |||
20150035023, | |||
20150262827, | |||
20160351570, | |||
20170221906, | |||
20170271462, | |||
20180090583, | |||
20180190810, | |||
20180286810, | |||
20180350821, | |||
KR20160141034, | |||
KR20170090996, |
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