An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.
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17. A device, comprising:
a non-volatile memory including a plurality of non-volatile memory cells arranged in a plurality of memory units, wherein the non-volatile memory comprises a first memory chip and a second memory chip; and
a controller configured to:
measure a plurality of threshold voltage distributions respectively corresponding to the plurality of memory units of the non-volatile memory;
measure a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; and
dynamically determine operation parameters for the non-volatile memory for each of the plurality of memory units, based on the measured distribution variation,
wherein the dynamically determining comprises dynamically determining, by the controller, first operation parameters corresponding to the first memory chip, and dynamically determining, by the controller, second operation parameters corresponding to the second memory chip.
1. An operating method of a storage device including a non-volatile memory and a controller controlling the non-volatile memory, the operating method comprising:
receiving, by the controller, read data from the non-volatile memory;
measuring, by the controller, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data;
measuring, by the controller, a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions;
dynamically determining, by the controller, operation parameters for the non-volatile memory, based on the measured distribution variation; and
transmitting, by the controller to the non-volatile memory, an operate command, an address, and at least one of the operation parameters, corresponding to the address,
wherein the non-volatile memory comprises a first memory chip and a second memory chip, and
wherein the dynamically determining comprises determining, by the controller, first operation parameters corresponding to the first memory chip, and determining, by the controller, second operation parameters corresponding to the second memory chip.
14. An operating method of a storage device including a non-volatile memory and a controller controlling the non-volatile memory, the operating method comprising:
receiving, by the controller, read data from the non-volatile memory;
measuring, by the controller, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data;
measuring, by the controller, a distribution variation metric between the plurality of memory units, based on the measured plurality of threshold voltage distributions;
dynamically grouping, by the controller, the plurality of memory units into a plurality of groups through clustering based on the measured distribution variation metric; and
dynamically determining, by the controller, operation parameters for the non-volatile memory for each of the plurality of groups,
wherein the non-volatile memory comprises a first memory chip and a second memory chip, and
wherein the dynamically determining comprises dynamically determining, by the controller, first operation parameters corresponding to the first memory chip, and dynamically determining, by the controller, second operation parameters corresponding to the second memory chip.
2. The operating method of
3. The operating method of
4. The operating method of
5. The operating method of
wherein the dynamically determining comprises dynamically determining, by the controller, the operation parameters for each of the plurality of groups.
6. The operating method of
the dynamically grouping of the plurality of memory units into the plurality of groups is further based on a plurality of read voltage levels for respectively determining a plurality of different program states, and
a first memory unit of the plurality of memory units is grouped into a first group for a first read voltage level and is grouped into a second group for a second read voltage level, wherein at least one of the memory units included in the first group is not included in the second group or at least one of the memory units included in the second group is not included in the first group.
7. The operating method of
ascertaining a distribution variation metric corresponding to the measured distribution variation; and
grouping the plurality of memory units into the plurality of groups through clustering based on the distribution variation metric.
8. The operating method of
9. The operating method of
10. The operating method of
11. The operating method of
12. The operating method of
the first memory chip comprises a first memory block and a second memory block, and
the dynamically determining of the first operation parameters comprises:
determining, by the controller, first operation parameters corresponding to the first memory block; and
determining, by the controller, operation parameters corresponding to the second memory block.
13. The operating method of
the first memory chip comprises a first word line and a second word line, and
the dynamically determining of the first operation parameters comprises:
determining, by the controller, operation parameters corresponding to the first word line; and
determining, by the controller, operation parameters corresponding to the second word line.
15. The operating method of
the storage device further includes a volatile memory, and
the operating method further comprises storing, in the volatile memory, the operation parameters respectively corresponding to the plurality of groups.
16. The operating method of
18. The device of
dynamically grouping the plurality of memory units into a plurality of groups through clustering based on the measured distribution variation; and
dynamically determining the operation parameters for each of the plurality of groups based on the measured distribution variation.
19. The device of
20. The operating method of
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This application claims the benefit of Korean Patent Application No. 10-2017-0134811, filed on Oct. 17, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The inventive concept relates to a storage device, and more particularly, to a storage device having a parameter calibration function, and an operating method of the storage device.
As a type of non-volatile memory, flash memory maintains stored data even when power is cut off. Flash memory stores data by shifting threshold voltages of memory cells and reads the data by using a predetermined read level. However, the threshold voltages of the memory cells may shift unintentionally, for example due to physical locations or deterioration of the memory cells. Thus, in order to prevent a read error from being caused by the unintentional shift of the threshold voltages, the read level should be dynamically shifted and stored, causing an increase in overhead. Considering the possibility that a plurality of read requests are generated for programmed memory cells, it is necessary to develop an operating method for decreasing overhead of the read operation.
The inventive concept provides a storage device having a parameter calibration function, and an operating method of the storage device.
According to an aspect of the inventive concept, there is provided an operating method of a storage device including receiving, by a controller, read data from the non-volatile memory, measuring, by the controller, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data, measuring, by the controller, a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions, dynamically determining, by the controller, operation parameters for the non-volatile memory, based on the measured distribution variation, and transmitting, by the controller, an operate command, an address, and at least one operation parameter corresponding to the address, to the non-volatile memory.
According to another aspect of the inventive concept, there is provided an operating method of a storage device, the operating method including receiving, by a controller, read data from the non-volatile memory, measuring, by the controller, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data, measuring, by the controller, a distribution variation metric between the plurality of memory units, based on the measured plurality of threshold voltage distributions, dynamically grouping, by the controller, the plurality of memory units into a plurality of groups through clustering based on the measured distribution variation metric, and dynamically determining, by the controller, operation parameters for the non-volatile memory for each of the plurality of groups.
According to another aspect of the inventive concept, there is provided an operating method of a storage device, the operating method including receiving, by a controller, read data from the non-volatile memory, measuring, by the controller, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data, measuring, by the controller, a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions, dynamically grouping, by the controller, the plurality of memory units into a plurality of groups, based on the measured distribution variation, dynamically determining, by the controller, operation parameters for the non-volatile memory for each of the plurality of groups, based on the measured distribution variation, and transmitting, by the controller, an operate command, an address, and at least one operation parameter corresponding to the address, to the non-volatile memory.
According to another aspect of the inventive concept, there is provided a storage device including a non-volatile memory, the storage device including a plurality of memory cells respectively connected to a plurality of word lines; and a controller configured to measure a distribution variation between the plurality of word lines based on a plurality of threshold voltage distributions respectively corresponding to the plurality of word lines, based on read data received from the non-volatile memory, determine operation parameters for the plurality of memory cells for each of groups, based on the measured distribution variation, and transmit an operate command, an address, and at least one operation parameter corresponding to the address, to the non-volatile memory.
According to yet another aspect of the inventive concept, a device comprises: a non-volatile memory including a plurality of non-volatile memory cells arranged in a plurality of memory units; and a controller. The controller is configured to: measure a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory; measure a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; and determine operation parameters for the non-volatile memory for each of the plurality of memory units, based on the measured distribution variation.
Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Referring to
NVM 200 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may each include a plurality of pages PG1 to PGm. Here, z and m may each be a positive integer and may be variously changed according to embodiments. For example, a memory block may be a unit of erasure (i.e., a unit of memory cells which are erased together in a single erase operation), and a page may be a unit of program and read (i.e., a unit of memory cells which are programmed together in a single program operation and read together in a single read operation). In some embodiments, NVM 200 may include a plurality of planes, a plurality of dies, or a plurality of chips. In an embodiment, NVM 200 may be a NAND flash memory device. However, the present embodiment is not limited thereto, and NVM 200 may be a resistive memory device such as resistive random access memory (ReRAM), phase change random access memory (PRAM), or magnetic random access memory (MRAM).
Controller 100 may control NVM 200 to read data DATA stored in NVM 200 in response to the read request from host 20, or to write the data DATA in NVM 200 in response to the program request from host 20. In the present embodiment, controller 100 may include a calibration module CM and a parameter buffer PB.
The calibration module CM may perform a read operation on NVM 200 to measure a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of NVM 200. Also, the calibration module CM may ascertain or measure a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions and may dynamically ascertain or determine operation parameters for NVM 200, based on the measured distribution variation. In an embodiment, the plurality of memory units may correspond to a plurality of word lines, a plurality of memory blocks, a plurality of memory chips, or a plurality of packages. The parameter buffer PB may store the operation parameters dynamically ascertained or determined by the calibration module CM.
In an embodiment, the calibration module CM may dynamically ascertain or determine, by groups, the operation parameters for NVM 200. In an embodiment, the plurality of word lines may be grouped into a plurality of word line groups. In an embodiment, the plurality of memory blocks may be grouped into a plurality of memory block groups. In an embodiment, the plurality of chips may be grouped into a plurality of chip groups. The parameter buffer PB may store the operation parameters ascertained or determined by the calibration module CM so as to respectively match a plurality of groups.
Controller 100 may transmit a command set including a command CMD, an address ADDR, and an operation parameter PM to NVM 200 to control an operation of NVM 200. Controller 100 may select the operation parameter PM corresponding to the address ADDR from among the operation parameters stored in the parameter buffer PB and may transmit the selected operation parameter PM, the command CMD, and the address ADDR to NVM 200. In a program operation, controller 100 may transmit data to NVM 200, and in a read operation, NVM 200 may provide the data to controller 100. The command CMD, the address ADDR, the operation parameter PM, and the data DATA may be transmitted or received between controller 100 and NVM 200 through an input/output (I/O) bus.
The storage system SS may be implemented with, for example, a personal computer (PC), a data server, a network-attached storage (NAS), an Internet of things (IoT) device, or a portable electronic device. The portable electronic device may be, for example, a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a portable navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, or the like. In some embodiments, storage device 10 may be an internal memory embedded into an electronic device. For example, storage device 10 may be a solid state drive (SSD), universal flash storage (UFS) memory device, embedded multi-media card (eMMC), or the like. In some embodiments, storage device 10 may be an external memory attachable/detachable on/from an electronic device. For example, storage device 10 may be a UFS memory card, compact flash (CF), secure digital (SD), micro-SD, mini-SD, extreme digital (xD), memory stick, or the like. In an embodiment, storage device 10 may comprise a key-value storage device or a key-value store, and for example, may be a key-value SSD. The key-value storage device may be a device which quickly and simply processes data by using a key-value pair. Here, the key-value pair may denote a pair consisting of a key having uniqueness and a value which is data corresponding to the key.
First and second threshold voltage distributions 21 and 22 may differ from each other, and a difference between first and second threshold voltage distributions 21 and 22 may be referred to as a distribution variation. In an embodiment, the distribution variation may occur before releasing storage device 10, that is, before selling storage device 10, and for example, may occur due to a physical location difference between the first and second memory units. In an embodiment, the distribution variation may occur while storage device 10 is operating after storage device 10 is released, and for example, may occur due to a program/erase cycle, a retention time, program disturbance, and read disturbance of each of the first and second memory units.
Due to the distribution variation, in a case of reading data from the second memory cells included in the second memory unit of NVM 200 by using read voltages Vr1, Vr2, and Vrn, a read error can occur. Therefore, controller 100 should ascertain or determine the read voltages Vr1, Vr2, and Vrn for the first memory cells and read voltages Vr1′, Vr2′, and Vrn′ for the second memory cells and store and manage the ascertained or determined read voltages Vr1, Vr2, and Vrn and read voltages Vr1′, Vr2′, and Vrn′, For this reason, overhead may be very large in some storage devices. Particularly, once a plurality of read requests are generated for programmed memory cells, read voltages should be calibrated every time, and the calibrated read voltages should be managed, causing a large increase in overhead.
According to the present embodiment, the calibration module CM may measure a distribution variation between the first memory cells included in the first memory unit of NVM 200 and the second memory cells included in the second memory unit of NVM 200, and may dynamically ascertain or determine operation parameters, based on the measured distribution variation. Therefore, the calibration module CM may calibrate the distribution variation before releasing storage device 10, or may calibrate the distribution variation while storage device 10 is operating after storage device 10 is released. Therefore, the calibration module CM flexibly copes with stress which occurs when storage device 10 is being assembled or is operating, thereby enhancing the performance and reliability of storage device 10.
In an embodiment, the calibration module CM may ascertain or determine first operation parameters for the first memory unit and second operation parameters for the second memory unit which are different from the first operation parameters, and may store the ascertained or determined first and second operation parameters in the parameter buffer PB. Subsequently, NVM 200 may perform a program/erase operation on the second memory cells by using the second operation parameters, and thus, a threshold voltage distribution of the second memory cells may be changed from second threshold voltage distribution 22 to a corrected second threshold voltage distribution 22′. Therefore, a distribution variation between second threshold voltage distribution 22 and corrected second threshold voltage distribution 22′ is reduced, and data may be read from the first and second memory cells by using the same read voltages Vr1, Vr2, and Vrn, thereby decreasing overhead of storage device 10.
Referring to
A calibration module CMa may be implemented as firmware or software and may be loaded into memory 120a. In an embodiment, the calibration module CMa may be implemented in a flash translation layer (FTL) and may be loaded into memory 120a. However, the present embodiment is not limited thereto, and the calibration module CMa may be implemented as hardware. In an embodiment, the calibration module CMa may include a variation metric measurement module 121 and a parameter calculation module 123.
Variation metric measurement module 121 may measure a distribution variation metric from a plurality of threshold voltage distributions. In an embodiment, the distribution variation metric may correspond to a first threshold voltage level, at which the number of “on” cells of programmed memory cells in each of memory units of NVM 200 corresponds to a first number, or a second threshold voltage level at which the number of “off” cells of the programmed memory cells in each of the memory units of NVM 200 corresponds to a second number. In an embodiment, the distribution variation metric may correspond to the number of “on” cells of memory cells, which are programmed by using a first word line voltage level in each memory unit of NVM 200, or the number of “off” cells of the memory cells which are programmed by using the first word line voltage level in each memory unit of NVM 200. In an embodiment, the distribution variation metric may correspond to a read voltage level for minimizing an error bit in each memory unit of NVM 200. Parameter calculation module 123 may calculate the operation parameters for NVM 200, based on the distribution variation metric.
The parameter buffer PBa may store the operation parameters calculated by parameter calculation module 123 and may be implemented as a portion of memory 120a. In an embodiment, the calibration module CMa and the parameter buffer PBa may be implemented as one chip. However, the present embodiment is not limited thereto, and the calibration module CMa and the parameter buffer PBa may be implemented as different chips. Also, a mapping table for changing a logical address, received from host 20, to a physical address of NVM 200 may be loaded into memory 120a.
Host interface 130 may provide an interface between host 20 and controller 100a, and for example, may provide an interface based on universal serial bus (USB), MMC, PCI express (PIC-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), integrated drive electronics (IDE), or the like. NVM interface 140 may provide an interface between controller 100a and NVM 200. For example, a command, an address, an operation parameter, program data, and read data may be transmitted or received between controller 100a and NVM 200 through NVM interface 140. ECC engine 150 may perform an ECC operation on data received from NVM 200 to detect one or more bit errors in the data and may correct the detected error bit(s). In an embodiment, ECC engine 150 may be implemented as hardware. In an embodiment, ECC engine 150 may be implemented as firmware or software and may be loaded into memory 120a.
In an embodiment, a memory unit may be a memory chip, and controller 100 may measure threshold voltage distributions of the first to eighth memory chips CH1 to CH8, measure a distribution variation between the first to eighth memory chips CH1 to CH8, and dynamically ascertain or determine operation parameters for the first to eighth memory chips CH1 to CH8, based on the measured distribution variation. For example, first operation parameters for the first memory chip CH1 may differ from second operation parameters for the second memory chip CH2.
In an embodiment, the memory unit may be a memory block, and controller 100 may measure threshold voltage distributions of the plurality of memory blocks BLK1 to BLKz, measure a distribution variation between the plurality of memory blocks BLK1 to BLKz, and dynamically ascertain or determine operation parameters for the plurality of memory blocks BLK1 to BLKz, based on the measured distribution variation. For example, first operation parameters for a first memory block BLK1 may differ from second operation parameters for a second memory block BLK2.
In an embodiment, a memory unit may comprise a word line and the memory cells (MC) which are connected to that word line, and controller 100 may measure threshold voltage distributions of the memory cells connected to the plurality of word lines WL1 to WL8, measure a distribution variation between the memory cells connected to the plurality of word lines WL1 to WL8, and dynamically determine operation parameters for the plurality of word lines WL1 to WL8, based on the measured distribution variation. For example, first operation parameters for a first word line WL1 may differ from second operation parameters for a second word line WL2.
Referring to
Referring to
Referring to
In an embodiment, first threshold voltage distribution 91 may correspond to an erase state E of
Referring to
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In some embodiments, the operating method may further include a process of receiving, by a controller, read data from an NVM before operation S110. Therefore, operations S110 to operations S170 may be performed by the controller, based on the read data received from the NVM.
In operation S110, a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units may be measured. For example, controller 100 may transmit a first read command and a first address corresponding to a first memory unit to NVM 200, and in response to the first read command, NVM 200 may perform a read operation on memory cells corresponding to the first address to measure a first threshold voltage distribution corresponding to a first memory unit. Subsequently, controller 100 may transmit a second read command and a second address corresponding to a second memory unit to NVM 200, and in response to the second read command, NVM 200 may perform a read operation on memory cells corresponding to the second address to measure a second threshold voltage distribution corresponding to a second memory unit.
In operation S130, a distribution variation between the plurality of memory units may be measured. For example, a distribution variation may be obtained by measuring a difference between the first threshold voltage distribution corresponding to the first memory unit and the second threshold voltage distribution corresponding to the second memory unit. In an embodiment, a distribution variation metric representing the distribution variation may correspond to a first threshold voltage level, where the number of “on” cells of programmed memory cells in each of the memory units corresponds to a first number, or a second threshold voltage level at which the number of “off” cells of the programmed memory cells in each of the memory units corresponds to a second number. In an embodiment, the distribution variation metric may include the number of “on” cells of memory cells, which are programmed by using a first word line voltage level in each memory unit of NVM 200, or the number of “off” cells of the memory cells which are programmed by using the first word line voltage level in each memory unit. In an embodiment, the distribution variation metric may correspond to a read voltage level for minimizing bit errors in each memory unit of NVM 200.
In operation S150, operation parameters may be dynamically ascertained or determined. For example, the calibration module CM included in controller 100 may dynamically ascertain or determine first operation parameters for memory cells included in the first memory unit and may dynamically ascertain or determine second operation parameters for memory cells included in the second memory unit. In an embodiment, the first and second operation parameters may be stored in the parameter buffer PB included in controller 100. For example, the parameter buffer PB may be implemented with SRAM. In an embedment, the first and second operation parameters may be stored in a volatile memory (for example, DRAM) outside controller 100. In an embodiment, the first and second operation parameters may be stored in NVM 200.
In operation S170, an operate command, an address, and an operation parameter may be transmitted. In an embodiment, controller 100 may generate a program command set including a program command, a program address, a program operation parameter, and program data, and may transmit the generated program command set to NVM 200. This will be described below with reference to
Referring to
In operation S230, controller 100 may transmit a read command to NVM 200. In an embodiment, controller 100 may transmit a read command and a first address corresponding to a first memory unit, and then, may transmit the read command and a second address corresponding to a second memory unit. In operation S240, NVM 200 may perform a read operation in response to the read command In an embodiment, for example, NVM 200 may sequentially apply a read voltage to a word line at intervals of 0.1V to generate a threshold voltage distribution. In an embodiment, NVM 200 may perform a read operation on memory cells corresponding to the first address, and then, may perform a read operation on memory cells corresponding to the second address. In operation S250, NVM 200 may transmit read data to controller 100.
In operation S260, controller 100 may measure a distribution variation metric of threshold voltage distributions between a plurality of memory units. In operation S270, controller 100 may calculate operation parameters (for example, program operation parameters), based on the measured distribution variation metric. In operation S280, controller 100 may transmit a program command and one or more program operation parameters to NVM 200. In operation S290, NVM 200 may perform a program operation, based on the transmitted program operation parameter(s). In operation S295, NVM 200 may transmit a response message representing a program end to controller 100.
The first command CMD1 may be a program sequence start command, for example, 80 h. The second command CMD2 may be a program sequence end command, for example, 10 h. The address ADDR may include, for example, column addresses having two clock cycles and row addresses having three clock cycles. The operation parameter PM may include a program start voltage VPGM, a loop count, and a program verify voltage VVFY. However, the present embodiment is not limited thereto, and in some embodiments, a transmission sequence of the operation parameter PM and the data DATA may be changed. When the second command CMD2 is received, a ready/busy signal RnBx of NVM 200 may be shifted from a high level to a low level, and thus, an operation of programming the data DATA in memory cells having the received address ADDR may be performed during a program time tPRGM.
Program command set 141 may be transmitted through an I/O bus IOx between controller 100 and NVM 200. Program command set 141 may correspond to a modified example of program command set 131 of
The operation parameter PM may include first to nth verify offsets VP1 to VPn. Here, each of the verify offsets VP1 to VPn may represent an offset for a reference program verify voltage. The parameter buffer PB may store verify offset table 142. For example, verify offset table 142 may include a verify offset set corresponding to each of a plurality of word lines WL1 to WL64, and the verify offset set may include the verify offsets VP1 to VPn respectively corresponding to first to nth program states. Controller 100 may select a verify offset set corresponding to an address ADDR in verify offset table 142 and may generate program command set 141 including the selected verify offset set.
In operation S300, controller 100 may transmit an erase command to NVM 200. In operation S310, NVM 200 may perform an erase operation in response to the erase command In operation S320, NVM 200 may transmit a response message representing an erase end to controller 100. In operation S330, controller 100 may transmit a read command to NVM 200. In operation S340, NVM 200 may perform a read operation in response to the read command In operation S350, NVM 200 may transmit read data to controller 100.
In operation S360, controller 100 may measure a distribution variation metric of threshold voltage distributions between a plurality of memory units. In operation S370, controller 100 may calculate operation parameters (for example, erase operation parameters), based on the measured distribution variation metric. In operation S380, controller 100 may transmit an erase command and erase operation parameters to NVM 200. In operation S390, NVM 200 may perform an erase operation, based on the transmitted erase operation parameters. In operation S395, NVM 200 may transmit a response message representing an erase end to controller 100.
The first command CMD1 may be an erase sequence start command, for example, 60 h. The second command CMD2 may be an erase sequence end command, for example, 70 h. The address ADDR may include, for example, row addresses having three clock cycles. The operation parameter PM may include an erase start voltage VBERs, a loop count, and a program verify voltage VVFY. When the second command CMD2 is received, a ready/busy signal RnBx of NVM 200 may be shifted from a high level to a low level, and thus, an operation of erasing a memory block corresponding to the received address ADDR may be performed during an erase time tERS.
Referring to
The first command CMD1 may be a read sequence start command, for example, ooh. The second command CMD2 may be a read sequence end command, for example, 30 h. The address ADDR may include, for example, column addresses having two cycles and row addresses having three cycles. The operation parameter PM may include a plurality of read start voltages Vr1 to Vr3. When the second command CMD2 is received, a ready/busy signal RnBx of NVM 200 may be shifted from a high level to a low level, and thus, an operation of reading data DATA from memory cells having the received address ADDR may be performed during a read time tREAD.
Referring to
In an embodiment, clustering module 122 may perform clustering based on a plurality of distribution variation metrics through machine learning and may group the plurality of memory units into the plurality of groups, based on a result of the clustering. For example, clustering module 122 may perform the clustering by using at least one of a k-means clustering algorithm, a K-medoids clustering algorithm, a hierarchical clustering algorithm, a density-based clustering algorithm, and a neural network algorithm. Hereinafter, an operation of clustering module 122 will be described in more detail with reference to
In an embodiment, a parameter calculation module 123 of the calibration module CMb may ascertain or determine a plurality of verify offsets VP1 to VPn for the plurality of word line groups WGR1 to WGRa, and the parameter buffer PB may store verify offset table 211 which includes the plurality of verify offsets VP1 to VPn for the plurality of word line groups WGR1 to WGRa. For example, the same verify offsets may be applied for each of the word lines included in a first word line group WGR1, and thus, a program operation on the word lines included in the first word line group WGR1 may be performed by using the same verify offsets. Also, a program operation on each of word lines included in a second word line group WGR2 may be performed by using verify offsets which are different from the verify offsets which are used in the program operation on the word lines included in the first word line group WGR1. As described above, a program operation may be performed by using different verify offsets for different word line groups, thereby decreasing a distribution variation between the different word line groups.
In an embodiment, parameter calculation module 123 may ascertain or determine a plurality of read voltage Vr1 to Vr3 for the plurality of word line groups WGR1 to WGRa, and the parameter buffer PB may store the read voltage table 212. For example, the same read voltages may be applied for each of the word lines included in the first word line group WGR1, and thus, a read operation on each of the word lines included in the first word line group WGR1 may be performed by using the same read voltages. Also, a read operation on each of the word lines included in the second word line group WGR2 may be performed by using read voltages which are different from the read voltages which are used in the read operation on the word lines included in the first word line group WGR1. As described above, a read operation may be performed by using different read voltages for different word line groups, thereby decreasing a read error caused by a distribution variation between the different word line groups.
In an embodiment, clustering module 122 may group the plurality of word lines WL1 to WL64 into first to fourth word line groups WGR1 to WGR4 with respect to a first program state P1. Also, clustering module 122 may group the plurality of word lines WL1 to WL64 into the first to third word line groups WGR1 to WGR3 with respect to a second program state P2. Also, clustering module 122 may group the plurality of word lines WL1 to WL64 into first to fifth word line groups WGR1 to WGR5 with respect to an nth program state Pn. Therefore, the same word lines may be grouped into different word line groups, based on a program state. For example, a tenth word line WL10 may be included in the first word line group WGR1 with respect to the first program state P1 and may be included in the second word line group WGR2 with respect to the second program state P2.
In an embodiment, parameter calculation module 123 may ascertain or determine first verify offsets VP1 for the plurality of word line groups WGR1 to WGR4 with respect to the first program state P1, ascertain or determine second verify offsets VP2 for the plurality of word line groups WGR1 to WGR3 with respect to the second program state P2, and ascertain or determine nth verify offsets VPn for the plurality of word line groups WGR1 to WGR5 with respect to the nth program state Pn. The parameter buffer PB may store first to nth program verify offset tables 221 to 223. For example, a first verify offset (for example, −10) corresponding to the first word line group WGR1 may be used for programming the tenth word line WL10 to the first program state P1. Also, a second verify offset (for example, −70) corresponding to the second word line group WGR2 may be used for programming the tenth word line WL10 to the second program state P2. As described above, a program operation may be performed on the same word lines by using different verify offsets for different program states, thereby decreasing a distribution variation between different word line groups.
In an embodiment, parameter calculation module 123 may determine a first read voltage Vr1 for determining the first program state P1 with respect to a plurality of word lines WL1 to WL4, determine a second read voltage Vr2 for determining the second program state P2 with respect to a plurality of word lines WL1 to WL3, and determine an nth read voltage Vrn for determining the nth program state Pn with respect to a plurality of word lines WL1 to WL5. The parameter buffer PB may store first to nth read voltage tables 224 to 226.
The various operations of methods described above may be performed by any suitable means capable of performing the operations, such as various hardware and/or software component(s), circuits, and/or module(s).
The software may comprise an ordered listing of executable instructions for implementing logical functions, and can be embodied in any “processor-readable medium” for use by or in connection with an instruction execution system, apparatus, or device, such as a single or multiple-core processor or processor-containing system.
The blocks or steps of a method or algorithm and functions described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a tangible, non-transitory computer-readable medium. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD ROM, or any other form of storage medium known in the art.
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Lee, Jin-Wook, Lee, Yun-Jung, Lee, Hee-Won, Lee, Dong-Gi, Jang, Joon-Suc, Kim, Ji-su, Kim, Chan-Ha, Kang, Suk-Eun, Ro, Seung-Kyung, Choi, Young-Ha
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