A method includes depositing a first layer on a portion of a first surface of a quantum hardware, the portion of the first surface comprising a set of wirebonds. The method further includes coupling the set of wirebonds to the first layer. The method further includes removing the first layer and the set of wirebonds from the first surface of the quantum hardware. In an embodiment, the first layer is an inert polymer in solution.
|
1. A method comprising:
depositing a first layer on a portion of a first surface of a quantum hardware, the portion of the first surface comprising a set of wirebonds;
bonding the set of wirebonds mechanically to the first layer; and
removing the first layer and the set of wirebonds from the first surface of the quantum hardware.
4. The method of
securing, prior to depositing the first layer, the quantum hardware in place on a vacuum device.
5. The method of
sealing a second surface of the quantum hardware, the second surface being opposite the first surface.
6. The method of
depositing a second layer on a portion of the second surface of the quantum hardware.
7. The method of
8. The method of
curing the first layer to mechanically bond the set of wirebonds to the first layer.
|
The present invention relates generally to a method for fabrication of quantum hardware. More particularly, the present invention relates to a method for removal of wirebonds in quantum hardware.
Hereinafter, a “Q” prefix in a word of phrase is indicative of a reference of that word or phrase in a quantum computing context unless expressly distinguished where used.
Molecules and subatomic particles follow the laws of quantum mechanics, a branch of physics that explores how the physical world works at the most fundamental levels. At this level, particles behave in strange ways, taking on more than one state at the same time, and interacting with other particles that are very far away. Quantum computing harnesses these quantum phenomena to process information.
The computers we use today are known as classical computers (also referred to herein as “conventional” computers or conventional nodes, or “CN”). A conventional computer uses a conventional processor fabricated using semiconductor materials and technology, a semiconductor memory, and a magnetic or solid-state storage device, in what is known as a Von Neumann architecture. Particularly, the processors in conventional computers are binary processors, i.e., operating on binary data represented in 1 and 0.
A quantum processor (q-processor) uses the odd nature of entangled qubit devices (compactly referred to herein as “qubit,” plural “qubits”) to perform computational tasks. In the particular realms where quantum mechanics operates, particles of matter can exist in multiple states—such as an “on” state, an “off” state, and both “on” and “off” states simultaneously. Where binary computing using semiconductor processors is limited to using just the on and off states (equivalent to 1 and 0 in binary code), a quantum processor harnesses these quantum states of matter to output signals that are usable in data computing.
Conventional computers encode information in bits. Each bit can take the value of 1 or 0. These 1s and 0s act as on/off switches that ultimately drive computer functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement.
Superposition means that each qubit can represent both a 1 and a 0 at the same time. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is a 1 or a 0 or both) can depend on the state of another, and that there is more information that can be ascertained about the two qubits when they are entangled than when they are treated individually.
Using these two principles, qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. IBM has successfully constructed and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines corporation in the United States and in other countries.)
A superconducting qubit includes a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers by a non-superconducting material. When the conductor in the superconducting layers is caused to become superconducting—e.g. by reducing the temperature of the conductor to a specified cryogenic temperature—pairs of electrons can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In certain qubit designs, referred to as a transmon qubit, the Josephson junction—which functions as a dispersive nonlinear inductor—is electrically coupled in parallel with one or more capacitive devices forming a nonlinear microwave oscillator. The oscillator has a resonance/transition frequency determined by the value of the inductance and the capacitance in the qubit circuit. Any reference to the term “qubit” is a reference to a superconducting qubit circuitry that employs a Josephson junction, unless expressly distinguished where used.
The information processed by qubits is carried or transmitted in the form of microwave signals/photons in the range of microwave frequencies. The microwave signals are captured, processed, and analyzed to decipher the quantum information encoded therein. A readout circuit is a circuit coupled with the qubit to capture, read, and measure the quantum state of the qubit. An output of the readout circuit is a classical output that represents the projection of the qubit state.
A superconducting qubit has two quantum states—|0> and |1>. These two states may be two energy states of atoms, for example, the ground (|g>) and first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nuclear or electronic spins, two positions of a crystalline defect, and two states of a quantum dot. Since the system is of a quantum nature, any combination of the two states are allowed and valid.
For quantum computing using qubits to be reliable, quantum hardwares, e.g., the qubits themselves, the readout circuitry associated with the qubits, and other parts of the quantum processor, must not alter the energy states of the qubit, such as by injecting or dissipating energy, in any significant manner or influence the relative phase between the |0> and |1> states of the qubit. This operational constraint on any circuit that operates with quantum information necessitates special considerations in fabricating semiconductor and superconducting structures that are used in such circuits.
The connection lines or wirebonds on a quantum device, route signals around the quantum device, between the quantum device and the external circuit, and vice versa. Oftentimes, wirebonds may need to be removed from the quantum device. Some non-limiting reasons for removing the wirebonds include (1) broken or incomplete wirebonds, (2) incorrect wirebond pattern, (3) residue around wirebonds from fabrication, (4) removal of all wirebonds for post-processing. The presently available methods for removing wirebonds include manually removing wirebonds one at a time using tweezers.
The illustrative embodiments recognize certain disadvantages with the presently available methods for removing wirebonds on quantum hardwares. Manually removing wirebonds is (1) time-consuming and inefficient, (2) risks damaging the quantum device through contact with the removal tool, and (3) risk debris and residue remaining on the quantum device.
The illustrative embodiments provide a method for removal of wirebonds on quantum hardwares. A method of an embodiment includes depositing a first layer on a portion of a first surface of a quantum hardware, the portion of the first surface comprising a set of wirebonds. In an embodiment, the method includes bonding the set of wirebonds mechanically to the first layer. In an embodiment, the method includes removing the first layer and the set of wirebonds from the first surface of the quantum hardware.
In an embodiment, the first layer comprises an inert polymer in solution. In an embodiment, the portion covers the entirety of the first surface. In an embodiment, the method includes securing, prior to depositing the first layer, the quantum hardware in place on a vacuum device.
In an embodiment, the method includes sealing a second surface of the quantum hardware, the second surface being opposite the first surface. In an embodiment, the method includes depositing a second layer on a portion of the second surface of the quantum hardware.
In an embodiment, the second layer is a thin film configured to seal the second surface from the first layer. In an embodiment, the method includes curing the first layer to mechanically bond the set of wirebonds to the first layer. In an embodiment, the first layer is cured at room temperature.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of the illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
The illustrative embodiments used to describe the invention generally address and solve the above-described needs for removal of wirebonds on quantum hardwares. The illustrative embodiments provide a method for removal of wirebonds on quantum hardwares, which address the above-described need or problem.
An operation described herein as occurring with respect to a frequency of frequencies should be interpreted as occurring with respect to a signal of that frequency or frequencies. All references to a “signal” are references to a microwave signal unless expressly distinguished where used.
An embodiment provides a method for removal of wirebonds on quantum hardwares, such that the method can be implemented as a software application. The application implementing a method embodiment can be configured to operate in conjunction with an existing semiconductor fabrication system—such as a packaging system, or a circuit assembly system.
For the clarity of the description, and without implying any limitation thereto, the illustrative embodiments are described using some example configurations. From this disclosure, those of ordinary skill in the art will be able to conceive many alterations, adaptations, and modifications of a described configuration for achieving a described purpose, and the same are contemplated within the scope of the illustrative embodiments.
Furthermore, simplified diagrams of the example wirebonds, polymers, qubits, resonators, and other circuit components are used in the figures and the illustrative embodiments. In an actual fabrication or circuit, additional structures or component that are not shown or described herein, or structures or components different from those shown but for a similar function as described herein may be present without departing the scope of the illustrative embodiments.
Furthermore, the illustrative embodiments are described with respect to specific actual or hypothetical components only as examples. The steps described by the various illustrative embodiments can be adapted for removal of wirebonds using a variety of components that can be purposed or repurposed to provide a described function within a quantum device, and such adaptations are contemplated within the scope of the illustrative embodiments.
The illustrative embodiments are described with respect to certain types of materials, electrical properties, steps, numerosity, frequencies, circuits, components, and applications only as examples. Any specific manifestations of these and other similar artifacts are not intended to be limiting to the invention. Any suitable manifestation of these and other similar artifacts can be selected within the scope of the illustrative embodiments.
The examples in this disclosure are used only for the clarity of the description and are not limiting to the illustrative embodiments. Any advantages listed herein are only examples and are not intended to be limiting to the illustrative embodiments. Additional or different advantages may be realized by specific illustrative embodiments. Furthermore, a particular illustrative embodiment may have some, all, or none of the advantages listed above.
With reference to the figures and in particular with reference to
Clients or servers are only example roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Server 104 and server 106 couple to network 102 along with storage unit 108. Software applications may execute on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. A data processing system, such as server 104 or 106, or client 110, 112, or 114 may contain data and may have software applications or software tools executing thereon.
Device 132 is an example of a mobile computing device. For example, device 132 can take the form of a smartphone, a tablet computer, a laptop computer, client 110 in a stationary or a portable form, a wearable computing device, or any other suitable device. Any software application described as executing in another data processing system in
Application 105 implements an embodiment described herein. Fabrication system 107 is any suitable system for fabricating a semiconducting or superconducting device. Application 105 provides instructions to system 107 for a fabrication process in a manner described herein
With reference to
In an embodiment, first layer 210 comprises a material with high elongation (above a threshold). In an embodiment, first layer 210 is formed using a material that exhibits an elongation of at least 140%, threshold level of elongation. Elongation is a measure of the percentage of strain before failure of a material. In an embodiment, first layer 210 comprises a material with high elastic modulus (above a threshold). In an embodiment, first layer 210 is formed using a material that exhibits an elastic modulus of at least 1 MPa, threshold level of elastic modulus. Elastic modulus is a measure of a material's resistance to deformation due to an applied stress. In an embodiment, first layer 210 comprises a material with high tensile strength (above a threshold). In an embodiment, first layer 210 is formed using a material that exhibits a tensile strength of at least 7.1 MPa, threshold level of tensile strength. Tensile strength is the maximum amount of stress applied to a material before failure.
With reference to
Configuration 300 depicts quantum hardware 308. An embodiment causes the fabrication system to deposit material 304, thus forming first layer 306. First layer 306 is an example of first layer 210 in
With reference to
Configuration 400 depicts quantum hardware 402. Quantum device 402 is an example of quantum device 308 in
An embodiment causes a fabrication system, such as fabrication system 107 in
With reference to
Configuration 500 comprises quantum hardware 502, qubit 504, and material 506. An embodiment causes a fabrication system, such as fabrication system 107 in
With reference to
Configuration 600 comprises quantum hardware 602, qubit 604, a set of wirebonds, such as wirebond 608, and a material 610. An embodiment causes a fabrication system, such as fabrication system 107 in
An embodiment causes a fabrication system, such as fabrication system 107 in
An embodiment causes a fabrication system, such as fabrication system 107 in
With reference to
Configuration 700 comprises quantum hardware 702. Quantum hardware 702 includes qubit 704 and a portion 706 of a first surface. An embodiment causes a fabrication system, such as fabrication system 107 in
With reference to
The application causes a fabrication system to seal a first surface of a quantum hardware (block 802). The application causes a fabrication system to deposit a first layer on a portion of a second surface of a quantum hardware (block 804). The application causes a fabrication system to couple (mechanically bond) a set of wirebonds to the first layer (block 806). The application causes a fabrication system to remove the first layer from the second surface of the quantum hardware (block 808). The application ends process 800 thereafter.
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “illustrative” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “illustrative” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
Sandberg, Martin O., Adiga, Vivekananda P., Connelly, Robert
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
5836071, | Dec 26 1996 | Texas Instrument Incorporated | Method to produce known good die using temporary wire bond, die attach and packaging |
6518161, | Mar 07 2001 | Bell Semiconductor, LLC | Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die |
20140110461, | |||
20140263584, | |||
20170110437, | |||
WO2012148967, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jan 02 2019 | International Business Machines Corporation | (assignment on the face of the patent) | / | |||
Jan 02 2019 | SANDBERG, MARTIN O | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 047882 | /0574 | |
Jan 02 2019 | ADIGA, VIVEKANANDA P | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 047882 | /0574 | |
Jan 02 2019 | CONNELLY, ROBERT | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 047882 | /0574 |
Date | Maintenance Fee Events |
Jan 02 2019 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Oct 17 2023 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Date | Maintenance Schedule |
Jul 14 2023 | 4 years fee payment window open |
Jan 14 2024 | 6 months grace period start (w surcharge) |
Jul 14 2024 | patent expiry (for year 4) |
Jul 14 2026 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 14 2027 | 8 years fee payment window open |
Jan 14 2028 | 6 months grace period start (w surcharge) |
Jul 14 2028 | patent expiry (for year 8) |
Jul 14 2030 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 14 2031 | 12 years fee payment window open |
Jan 14 2032 | 6 months grace period start (w surcharge) |
Jul 14 2032 | patent expiry (for year 12) |
Jul 14 2034 | 2 years to revive unintentionally abandoned end. (for year 12) |