Disclosed is an apparatus and method for generating virtual inspection channels mid-way between the physical inspection channels of an eddy current array probe, thereby reducing the coverage loss and improving defect sizing and imaging. The method is based upon a calibration to determine the mid-channel coverage loss for parallel defects having their long axis parallel to the scanning direction. Based on the coverage loss measurement, a vector analysis system is constructed enabling generation of virtual channel signals which are available for processing in the same way as physical channels, with impedance plane representation including real and/or imaginary signal components. The system differentiates between parallel and perpendicular defects and employs different algorithms to generate virtual channel signals for parallel and perpendicular defect orientations.
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11. A method of conducting an eddy current (ec) inspection for detecting a possible defect in a test object, the method comprising the steps of,
acquiring ec response signals from at least two adjacent ec sensors, wherein respective positions of the two ec sensors form two adjacent inspection channels at the times when the sensors form a test scanning path near a surface of the test object;
generating, digitally, a virtual channel according to a vector combination of digitized ec response signals of the two ec sensors and generating virtual signal data based on the ec response signals and the virtual channel; and
processing the ec response signals and the virtual signal data to generate a defect signal indicative of the possible defect.
1. An eddy current (ec) system for detecting a possible defect in a test object, the system comprising:
an acquisition unit configured to receive ec response signals from at least two adjacent ec sensors, and wherein respective positions of the two ec sensors form two adjacent inspection channels at the times when the sensors form a test scanning path near a surface of the test object;
a virtual channel generator configured to digitally generate a virtual channel according to a vector combination of digitized ec response signals of the two ec sensors; and
a data processor configured to generate virtual signal data derived from the ec response signals and the virtual channel, and process the ec response signals and the virtual signal data to generate a defect signal indicative of the possible defect.
2. The ec system of
3. The ec system of
4. The ec system of
5. The ec system of
6. The ec system of
7. The ec system of
8. The ec system of
9. The ec system of
10. The ec system of
12. The method of
acquiring a first calibration signal from a calibration defect having a long axis parallel to the scanning path and positioned along a first of the two adjacent inspection channels;
acquiring a second calibration signal from the calibration defect positioned in the mid-way between the two inspection channels;
acquiring a third calibration signal from the calibration defect having a long axis parallel to the scanning path and positioned along a second of the two adjacent inspection channels;
calculating a first coverage loss by using the second calibration signal divided by the first calibration signal, and calculating a second coverage loss by using the second calibration signal divided by the third calibration signal, wherein the first and the second coverage loss are indicative of the ec characteristics of the two ec sensors in response to the calibration defect.
13. The method of
14. The method of
15. The method of
16. The method of
calculating an average of the ec response signals for a perpendicular defect;
calculating an average of the ec response signals divided by a coverage loss for a parallel defect calculated according to a reduction in a calibration signal from a defect mid-way between the at least two adjacent inspection channels.
17. The method of
18. The method of
19. The method of
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The invention relates to an eddy current (EC) array inspection system used for non-destructive test and inspection (NDT/NDI), and more particularly to an apparatus and method for improving the reproducibility of EC array systems by generating virtual channels between the physical channels of the EC array.
The use of EC array probes for NDT/NDI is well known in existing practice. Generally, an EC array probe comprises a multiplicity of individual EC sensors, each individual EC sensor comprising eddy current coils. Some of the coils are configured as driver coils, creating a variable magnetic field in a test object, while other coils are configured as sensing coils which detect magnetic fields generated by eddy currents in the test object. In some embodiments, the same coil can simultaneously serve both driver and sensing functions. Each individual EC sensor has a center point where there is maximum sensitivity to eddy currents, and therefore maximum sensitivity for detection of defects. This center point is hereinafter referred to as the center of a physical channel of the individual EC sensor. In operation, the EC array probe is scanned near the surface of the test object, and each individual EC sensor is most sensitive to defects in an inspection channel represented by the trajectory path of the center point of the physical channel.
A common problem in EC array testing is the signal amplitude variation due to the limited channel coverage of each probe. The variation, usually referred to as “coverage loss”, is caused by reduction in sensitivity to defects which are not directly under the center point of any sensor, but are located in the space between adjacent sensors where sensitivity is reduced. Consequently the received signal from a given defect, particularly a defect oriented parallel to the direction of motion of the array, will depend on the location of the defect relative to the individual EC sensors.
U.S. Pat. No. 8,125,219 by Jungbluth et al discloses synthetic crack signals which may be positioned between channels in order to reduce coverage loss. However, the interpretation of such signals is based on very specific knowledge of the flaw, and no method is disclosed for creating intermediate virtual channels whose generation is based solely on the physical properties of the coils with no a priori knowledge of the defect being required.
Therefore there exists a need for a general method to reduce the signal variability due to coverage loss, and thereby to enhance the probe resolution and provide better defect imaging.
Accordingly, it is a general objective of the present disclosure to provide a system and method in Eddy Current Array applications to reduce coverage loss by providing one or more virtual channels, calculated based on the properties of the physical channels.
It is a further objective of the present disclosure to provide one or more virtual channels which are represented in the same way as physical channels in an impedance plane representation having both real and imaginary components, but having maximum sensitivity mid-way between adjacent physical channels.
It is a further objective of the present disclosure to provide one or more virtual channels by using vector interpolation of EC signals from pairs of adjacent physical channels, with the vector system being based on measurements of coverage loss for calibration defects located mid-way between physical channels.
It is yet another objective of the present disclosure to provide virtual channels for EC array application located mid-way between physical channels, wherein the virtual channels are available for interpolation of signals from defects located at any position between the physical channels. Since the virtual channels compensate for coverage loss, their use provides improved probe sensitivity and defect imaging.
Referring again to
Virtual channel generator 6 may optionally further comprise an orientation determination unit 12, whose purpose is to determine the orientation of the one or more defects which are responsible for the EC signals received by virtual channel generator 6. As described below, virtual channel generator 6 is thereby able to use different algorithms to generate virtual channel data for defects having different orientation.
Note that an important aspect of the present invention is that the virtual channels are available to data processor 8 in the same way as physical channels, with impedance plane representation including real and/or imaginary signal components. Data processor 8 may therefore process the data as though the number of channels has been doubled, with resulting improvement in the resolution and sensitivity of the EC measurement.
It should be noted that the coil configuration of individual EC sensor 18 is presented as an exemplary embodiment. The number, shape and geometric configuration of the coils may be varied to be any number of coils of any shape and any geometric configuration. The coils may be wound in a three dimensional configuration, such as a cube or a polygonal prism. Alternatively, the coils may be planar metallic traces constructed in layers on a printed circuit board. All such variations of the sensor and its coils are within the scope of the present disclosure.
Note that measurement of sensitivity curve 32 and determination of coverage loss according to equation (1) is done when array probe 2 is in calibration mode scanning near the surface of calibration sample 3. In calibration mode, parallel defect 54 is a machined calibration defect at the surface of calibration sample 3. Note also that the conditions of scanning, such as the lift-off of the probe above the surface, should be the same in calibration mode as in testing mode.
Note that in
θ=cos−1(coverage loss) (2)
{right arrow over (E)}*{right arrow over (S(n))}=M(n) (3)
{right arrow over (E)}*{right arrow over (S(n+1))}=M(n+1) (4)
In existing practice, the size of the defect is represented by the maximum channel response, which is given by M(n) for the exemplary defect E illustrated in
{right arrow over (E)}*{right arrow over (S(n+0.5))}=M(n+0.5) (5)
Since the data for virtual channel S(n+0.5) is available to data processor 8 in the same way as data for physical channels S(n) and S(n+1), the size of the defect may be represented by the maximum value of S(n), S(n+0.5) or S(n+1). For the exemplary defect E illustrated in
The advantage of generating a virtual channel is further illustrated in
In deriving the vector representation shown in
The vector analysis of
Based on the vector analysis of
Equations (6) and (7) are applied continuously for all adjacent individual EC sensor pairs throughout scan 50 of array probe 2, thereby generating a set of continuously available virtual channels having greatly reduced coverage loss as shown in
Referring to
It should be noted that coverage loss may be calculated using measurements of a single physical channel and a single mid-way position as illustrated in
Referring now to
In step 118, virtual channel generator 6 determines whether M(n) and/or M(n+1) is greater than zero. If yes, virtual channel M(n+0.5) is generated at step 120 according to the vector analysis given by equation (6), with the value of cos θ taken from the calibration mode measurement shown in
Although the present invention has been described in relation to particular embodiments thereof, it can be appreciated that various designs can be conceived based on the teachings of the present disclosure, and all are within the scope of the present disclosure.
In example embodiments of the present invention, processing by the processor may be implemented in hardware, firmware, software, or a combination of any of them. For example, processing may be implemented in computer programs executed on programmable computers/machines that each includes a processor, a storage medium or other article of manufacture that is readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. In certain embodiments of the present invention, program code may be applied to data entered using an input device to perform processing and to generate output information.
Example embodiments of the present invention may be embodied by one or more programmable processors executing one or more computer programs to perform the functions of the system. Other example embodiments of the present invention may be implemented as special purpose logic circuitry (e.g., a field-programmable gate array (FPGA) and/or an application-specific integrated circuit (ASIC)). Yet other example embodiments of the present invention may be implemented using electronic hardware circuitry that include electronic devices such as, for example, at least one of a processor, a memory, a programmable logic device or a logic gate.
Some embodiments of the present invention may be implemented, at least in part, via a computer program product (e.g., in a non-transitory machine-readable storage medium such as, for example, a non-transitory computer-readable medium) for execution by, or to control the operation of, a data processing apparatus (e.g., a programmable processor, a computer, or multiple computers). In certain embodiments, each such program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. In certain other embodiments, however, the programs may be implemented in assembly or machine language. In some embodiments, the language may be a compiled or an interpreted language and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. In some other embodiments, a computer program may be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
The methods and apparatus of this invention may take the form, at least partially, of program code (i.e., instructions) embodied in tangible non-transitory media, such as floppy diskettes, CD-ROMs, hard drives, random access or read only-memory, or any other machine-readable storage medium. At times the program code is loaded into and executed by a machine, the machine becomes an apparatus for practicing the invention. At times the program code is implemented on one or more general-purpose processors, the program code combines with such a processor to provide a unique apparatus that operates analogously to specific logic circuits. As such, a general-purpose digital machine can be transformed into a special purpose digital machine. In some other embodiment, a non-transitory machine-readable medium may include but is not limited to a hard drive, compact disc, flash memory, non-volatile memory, volatile memory, magnetic diskette and so forth but does not include a transitory signal per se.
The flowcharts and block diagrams in the figures may illustrate the apparatus, method, as well as architecture, functions, and operations executable by a computer program product according to various embodiments of the present disclosure. Each block in the flowcharts or block diagrams may represent a module, a program segment, or a part of code, which may contain one or more executable instructions for performing specified logic functions. Therefore, the methods described herein are not limited to the specific examples described; rather, any of the method steps may be re-ordered, combined, removed, or performed in parallel or in serial, as necessary, to achieve the results embodying the claims. Further, each block and a combination of blocks in the block diagrams or flowcharts may be implemented by a dedicated, hardware-based system for performing specified functions or operations or by a combination of dedicated hardware and computer instructions.
Various exemplary embodiments of the present invention have been described with reference to the preceding drawings only as exemplary embodiments and the scope of the invention is limited only by the claims. These exemplary embodiments are provided only for enabling those skilled in the art to better understand and then further implement the present invention and are not intended to limit the scope of the present invention in any manner.
Further, example embodiments of the present invention may be practiced according to the claims without some or all of the specific details of the described embodiments. Therefore, the invention encompasses numerous alternatives, modified, and equivalent embodiments that may be conceived having a structure and method disclosed as herein and such alternative embodiments may be used without departing from the principles of and within the scope of the appended claims.
For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. Accordingly, the above embodiments of the present invention are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details of the example embodiments given herein but may be modified within the scope and equivalents of the appended claims.
The terms “comprise(s),” “include(s)”, their derivatives and like expressions used herein should be understood to be open (i.e., “comprising/including, but not limited to”). The term “based on” means “at least in part based on”, the term “one embodiment” means “at least one embodiment”, and the term “another embodiment” indicates “at least one further embodiment”. Relevant definitions of other terms have been provided in the present disclosure.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
8125219, | May 20 2008 | SIEMENS ENERGY GLOBAL GMBH & CO KG | Method for determining and evaluating eddy-current displays, in particular cracks, in a test object made from an electrically conductive material |
20010052905, | |||
20060132123, | |||
20080040053, | |||
20140198824, | |||
20160356743, | |||
20170059683, |
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