A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.
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19. An operation method of a data transceiver device, wherein the data transceiver device comprises a buffer circuit and a storage circuit, the operation method comprising steps of:
receiving an input data and storing the input data in the buffer circuit;
processing the input data to generate an output data;
storing the output data in the storage circuit;
generating a time-out signal based on a set time;
transmitting the output data based on an output data threshold value and the time-out signal; and
adjusting the set time and/or the output data threshold value based on an initial condition and a state of the buffer circuit;
wherein the initial condition is selected from a group comprising a type of a data transmission interface, whether there is a hub on the data transmission interface, a data flow of the output data, amount of the output data per unit time, a data flow of the input data, and amount of the input data per unit time, and the state of the buffer circuit is a size of remaining or available space of the buffer circuit and/or whether the size of the remaining or available space of the buffer circuit is less than or greater than a threshold value.
1. A data transceiver device for receiving an input data and transmitting an output data, comprising:
a buffer circuit configured to store the input data;
a storage circuit configured to store the output data;
a timing circuit configured to generate a time-out signal based on a set time; and
a control circuit configured to process the input data to generate the output data and to transmit the generated output data based on an output data threshold value and the time-out signal;
wherein the control circuit adjusts the set time and/or the output data threshold value based on an initial condition and a state of the buffer circuit;
wherein the initial condition is selected from a group comprising a type of a data transmission interface, whether there is a hub on the data transmission interface, a data flow of the output data, amount of the output data per unit time, a data flow of the input data, and amount of the input data per unit time, and the state of the buffer circuit is a size of remaining or available space of the buffer circuit and/or whether the size of the remaining or available space of the buffer circuit is less than or greater than a threshold value.
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The present disclosure generally relates to electronic devices, and, more particularly, to a data transceiver device and its operation methods.
The threshold value and the preset time play important roles in the performance of the electronic device 100. A threshold value that is too large hinders the host 110 from receiving the data timely, and a threshold value that is too small lowers the transmission efficiency (i.e., low bandwidth utilization rate). The threshold value is hard to design due to its high dependence on the memory size of the host 110, in which the memory size is not standardized. In addition, the settings of the preset time and the threshold value are also dependent on the variety of the host 110 and the data transmission interface 130, e.g., USB2.0, USB3.0, or USB type-C. As a result, adaptive adjustments on the threshold value and the preset time are crucial to the performance of the electronic device.
In view of the issues of the prior art, an object of the present disclosure is to provide a data transceiver device and its operation methods, so as to improve the performance of an electronic device.
A data transceiver device for receiving an input data and transmitting an output data is provided. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store the input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal based on a set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data based on an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and a state of the buffer circuit. The initial condition may be related to the type of a data transmission interface, to whether there is a hub on the data transmission interface, to the data flow of an output data and/or the amount of the output data per unit time, and/or to the data flow of an input data and/or the amount of the input data per unit time. The state of the buffer circuit may refer to the size of the remaining or available space of the buffer circuit and/or whether the size of the remaining or available space of the buffer circuit is less than or greater than a threshold value.
An operation method of a data transceiver device is provided. The data transceiver device includes a buffer circuit and a storage circuit. The operation method includes the following steps: receiving an input data and storing the input data in the buffer circuit; processing the input data to generate an output data; storing the output data in the storage circuit; generating a time-out signal based on a set time; transmitting the output data based on an output data threshold value and the time-out signal; and adjusting the set time and/or the output data threshold value based on an initial condition and a state of the buffer circuit.
A network interface card for receiving an input data and transmitting an output data is provided. The network interface card includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store the input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data based on the time-out signal. The control circuit adjusts a pause packet transmission timing parameter based on an initial condition and a state of the buffer circuit.
According to this disclosure, the data transceiver device and its operation methods can adaptively adjust the data transmission parameters for various environments to improve the transmission efficiency. In comparison with the conventional technology, the data transceiver device and its operation methods provided in this disclosure have the adaptive adjustment capability, which saves the circuit designers a lot of human resources in the customization for various hardware specifications and/or application environments.
These and other objectives of the present disclosure no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings.
The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be interpreted accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said “indirect” means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events.
The disclosure herein includes a data transceiver device and its operation method. On account of that some or all elements of the data transceiver device could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure, and that this omission nowhere dissatisfies the specification and enablement requirements. Some or all of the processes of the operation methods of the data transceiver device may be implemented by software and/or firmware and can be performed by the data transceiver device or its equivalent. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present disclosure, which means that the scope of this disclosure is not limited to the embodiments in the specification.
The control circuit 221 receives the input data Din (step S310) and stores the input data Din in the buffer circuit 224 (step S320). The buffer circuit 224 can be a first-in first-out (FIFO) register or memory. The control circuit 221 then processes the input data Din to generate the output data Dout (step S330). For example, when the data transceiver device 220 is a network interface card (NIC), the input data Din can be a network packet containing a header, and the output data Dout can be the content of the network packet. In other words, the processing in step S330 includes setting the corresponding parameter or value at the specific header position. After generating the output data Dout, the control circuit 221 stores the output data Dout in the storage circuit 225 (step S340). In some embodiments, the storage circuit 225 may be implemented by the dynamic random access memory (DRAM). The timing circuit 223 is configured to generate a time-out signal according to the set time (step S350), and the control circuit 221 transmits the output data Dout to the host 210 based on an output data threshold value and the time-out signal (step S360). The set time may be stored in a register (not shown) of the timing circuit 223 and/or in the non-volatile memory 226, and the output data threshold value may be stored in the memory 222 and/or the non-volatile memory 226. The control circuit 221 adjusts the set time and/or the output data threshold value based on an initial condition and a state of the buffer circuit 224 (step S370).
In some embodiments, the initial condition (such as the initial condition Cini in
In other embodiments, step S510 determines whether a further adjustment on the set time and/or the output data threshold value is needed based on the size of the remaining or available space of the buffer circuit 224. More specifically, if the remaining or available space of the buffer circuit 224 becomes larger as a result of an increase (or decrease) in the set time and/or the output data threshold value, the control circuit 221 continues to increase (or decrease) the set time and/or the output data threshold value in the next adjustment. On the contrary, if the remaining or available space of the buffer circuit 224 becomes less as a result of an increase (or decrease) in the set time and/or the output data threshold value, the control circuit 221 decreases (or increases) the set time and/or the output data threshold value in the next adjustment.
When step S510 is negative, the control circuit 221 may store the adjusted value(s) (i.e., the adjusted set time and/or the adjusted output data threshold value) in the non-volatile memory 226 (step S520), applies the adjusted value(s) to the set time and/or the output data threshold value (step S530), and then returns to
When step S510 is positive, the control circuit 221 checks whether the adjusted value(s) meets the boundary condition (step S540). If the adjusted value(s) meets or exceeds the boundary condition, step S540 is determined positive; otherwise, negative.
In some embodiments, the boundary condition (such as the boundary condition Cbdr in
In some embodiments, the boundary condition Cbdr may be related to the type of the data transmission interface 230, to whether there is a hub on the data transmission interface 230, to the data flow of the output data Dout and/or the amount of the output data Dout per unit time, and/or to the data flow of the input data Din and/or the amount of the input data Din per unit time.
If the boundary condition is met (YES branch in step S540), the control circuit 221 finishes adjusting the set time and/or the output data threshold value (step S550), and sets the set time and/or the output data threshold value to the default value or the boundary condition (step S560). The default value is, for example, unadjusted set time and/or an unadjusted output data threshold value and can be stored in the non-volatile memory 226. After step S560 finishes, the control circuit 221 proceeds to perform steps S310 to S370 in
If the boundary condition is not met (NO branch in step S540), the control circuit 221 determines whether the adaptive adjustment should be stopped (step S570 or S580). In step S570, the host 210 controls the stop of the adaptive adjustment, whereas in step S580, the data transceiver device 220 determines whether to stop the adaptive adjustment on its own. In some embodiments, step S580 can be performed before step S570. In some embodiments, steps S570 and S580 can be performed simultaneously. When step S570 or step S580 is positive, the control circuit 221 performs step S550 and step S560 and then proceeds to perform steps S310 to S370 in
In some embodiments, when the data transceiver device 220 is restarted (YES branch in step S810), the flow can go to the flow of
In some embodiments, the control circuit 221 may be a circuit or an electronic component with program execution capability, such as a central processing unit (CPU), microprocessor, or micro-processing unit. The control circuit 221 executes the program code or program instructions stored in the memory 222 to perform the steps in
The control circuit 221 can perform the adjustment process of
In some embodiments, the timing circuit 223 is a counter that operates according to the system clock of the electronic device 200, and issues a time-out signal and resets the count value when the count value reaches the target value. Adjusting the set time is equivalent to adjusting the target value of the counter.
In some embodiments, when the data transceiver device 220 is a NIC, the control circuit 221, in the adjustment process of
The above-mentioned data transceiver device which processes the network packets is intended to illustrate this disclosure by way of examples, rather than to limit the scope of this disclosure. People having ordinary skill in the art can apply this disclosure to other types of data transceiver devices according to the embodiments discussed above.
Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method embodiment through the disclosure of the device embodiment, repeated and redundant description is thus omitted. Please note that there is no step sequence limitation for the method embodiments as long as the execution of each step is applicable. Furthermore, the shape, size, and ratio of any element and the step sequence of any flow chart in the disclosed figures are exemplary for understanding, not for limiting the scope of this disclosure.
The aforementioned descriptions represent merely the preferred embodiments of this disclosure, without any intention to limit the scope of this disclosure thereto. Various equivalent changes, alterations, or modifications based on the claims of this disclosure are all consequently viewed as being embraced by the scope of this disclosure.
Lin, Chun-Hao, Chu, Shih-Chiang, Huang, Zhen-Ting, Wong, Er-Zih
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