A film patterning method, an array substrate, and a manufacturing method of an array substrate are disclosed. The film patterning method includes: applying photoresist on a film to be patterned; performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region; post-baking the photoresist, so that the photoresist is melted and collapsed to change the region corresponding to the completely removed portion into a second region, the photoresist after post-baking forms into a mask pattern; and patterning the film by using the mask pattern as a mask.
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1. A film patterning method, comprising:
applying photoresist on a film to be patterned;
performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region;
post-baking the photoresist, so that the photoresist is melted and collapsed to change the region corresponding to the completely removed portion into a second region, the second region exposing the film, wherein the photoresist, after the post-baking, forms into a mask pattern; and
patterning the film by using the mask pattern as a mask,
wherein a size of the first region in a direction parallel to a plane where the film is located is a first size, a size of the second region in the direction parallel to the plane where the film is located is a second size, the second size is smaller than the first size, and a planar shape of the first region and the second region comprises at least one selected from the group consisting of a circle and a line.
2. The film patterning method according to
3. The film patterning method according to
4. The film patterning method according to
5. The film patterning method according to
6. The film patterning method according to
upon the planar shape of the second region being the line, the second size is a size of a short edge of the line, and the second size is 1 μm-2.9 μm.
7. The film patterning method according to
upon the planar shape of the first region being the line, the first size is a size of a short edge of the line, and the first size is not less than 3 μm.
8. The film patterning method according to
9. The film patterning method according to
10. The film patterning method according to
11. A manufacturing method of an array substrate, comprising:
providing a base substrate;
forming a film to be patterned on the base substrate; and
patterning the film by using the film patterning method according to
12. An array substrate, manufactured by the manufacturing method of the array substrate according to
13. The array substrate according to
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The present application claims priority of China Patent application No. 201710585224.7 filed on Jul. 18, 2017, the content of which is incorporated in its entirety as portion of the present application by reference herein.
At least one embodiment of the present disclosure relates to a film patterning method, an array substrate, and a manufacturing method thereof.
In a manufacturing method of an array substrate, a process for patterning a film generally patterns the film by using photoresist as a mask. Therefore, the precision of the manufactured photoresist mask has a large impact on a pattern with small size to be formed on the film.
At least one embodiment of the present disclosure provides a film patterning method, an array substrate and a manufacturing method thereof.
At least one embodiment of the present disclosure provides a film patterning method, including: applying photoresist on a film to be patterned; performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region; post-baking the photoresist, so that the photoresist is melted and collapsed at a high temperature to change the region corresponding to the completely removed portion into a second region, the photoresist after post-baking forms into a mask pattern; and patterning the film by using the mask pattern as a mask.
For example, in some examples, a minimum size of the first region in a direction parallel to a plane where the film is located is a first size, a minimum size of the second region in the direction parallel to the plane where the film is located is a second size, and the second size is smaller than the first size.
For example, in some examples, the photoresist is positive photoresist.
For example, in some examples, a planar shape of the second region includes at least one selected from the group consisting of a circle and a line.
For example, in some examples, during the post-baking, the post-baking has a temperature of 150° C.-300° C. to cause the photoresist to melt and collapse at a high temperature.
For example, in some examples, during the post-baking, a time for the post-baking is 10 s-500 s.
For example, in some examples, during the post-baking, the time for the post-baking is 10 s-50 s.
For example, in some examples, the second size is 1 μm-2.9 μm.
For example, in some examples, the first size is not less than 3 μm.
For example, in some examples, the photoresist has a thickness of 0.5 μm-10 μm in a direction perpendicular to the film.
For example, in some examples, the thickness of the photoresist is 1.5 μm-2.2 μm in the direction perpendicular to the film.
For example, in some examples, a light intensity used in the exposure is 10 J/cm3-500 J/cm3.
At least one embodiment of the present disclosure provides a manufacturing method of an array substrate, including: providing a base substrate; forming a film to be patterned on the base substrate; and patterning the film by using the film patterning method according to any one of the abovementioned embodiments.
At least one embodiment of the present disclosure provides an array substrate, manufactured by the abovementioned manufacturing method of the array substrate.
For example, in some examples, a surface of the film included in the array substrate has a film pattern has a same planar shape as the second region.
In order to clearly illustrate the technical solution of embodiments of the present disclosure, the drawings of the embodiments will be briefly described in the following, it is obvious that the drawings in the description are only related to some embodiments of the present disclosure and not limited to the present disclosure.
In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.
Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. “On,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.
In study, the inventor(s) of the present application notices that: in a manufacturing method of an array substrate, the requirement on the critical dimension (DICD) to develop an opening with a small size in photoresist mask is very high. Exposure equipment used to manufacture the opening with a small size in the photoresist mask generally has limit precision. A normal mask method cannot meet the requirements in a case of preparing an opening with a size smaller than the limit precision, and purchase of an exposure equipment with higher precision and manufacture of a mask with higher precision will largely increase the manufacturing costs.
Embodiments of the present disclosure provide a film patterning method, an array substrate and a manufacturing method thereof. The film patterning method includes: applying photoresist on a film to be patterned; performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region; post-baking the photoresist, so that the photoresist is melted and collapsed at a high temperature to change the region corresponding to the completely removed portion into a second region, and the photoresist after post-baking forms into a mask pattern; and patterning the film by using the mask pattern as a mask. The film patterning method utilizes characteristics of a hot-melt photoresist that melts and collapses at a high temperature after the development and the post-baking, to provide a possibility to form a pattern with a size smaller than the limit precision of an exposure equipment on a film to be patterned. The patterning method is simple in process, and has low costs.
Hereinafter, the film patterning method, the array substrate, and the manufacturing method thereof provided by the embodiments of the present disclosure are described with reference to the accompanying drawings.
An embodiment of the present disclosure provides a film patterning method.
S101: applying photoresist on a film to be patterned.
For example, as illustrated by
For example, the base substrate 100 may be made of one or more materials selected from the group consisting of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The present embodiment includes but is not limited thereto.
For example, the film 110 may be an insulating layer. For example, the film 110 may be a gate insulating layer, an interlayer insulating layer, a passivation layer, or an etch barrier layer, and the like, which is not limited in the present embodiment.
For example, the film 110 may include an inorganic material such as an oxide, a sulfide, or a nitride, which is not limited in the present embodiment.
For example, the oxide may include calcium oxide, zinc oxide, copper oxide, titanium dioxide, tin dioxide, etc.; the sulfide may include iron sulfide, copper sulfide, zinc sulfide, tin disulfide, sulfur dioxide, etc.; and the nitride may include silicon nitride, aluminum nitride or the like. The present embodiment includes but is not limited thereto.
For example, the film 110 may also be selected as an organic material, for example, the organic material may be one or a combination of ones selected from the group consisting of polyimide, polyamide, polycarbonate, and epoxy resin. The present embodiment is not limited thereto.
For example, the film 110 may also be a metal layer. For example, a material of the film 110 may be one or more materials selected from the group consisting of aluminum, silver, molybdenum, titanium, platinum, gold, and chromium, which is not limited in the present embodiment. The film 110 can also be other films.
For example, as illustrated by
For example, a coating temperature of the photoresist is generally the same as a room temperature to minimize a temperature fluctuation of the photoresist, thereby reducing a process fluctuation.
S102: performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region.
For example, a mask (not shown) is covered on the photoresist layer 120, and the photoresist layer 120 covered with the mask is exposed.
For example, the photoresist layer 120 may be irradiated with an electron beam, an ion beam, an X-ray, an ultraviolet ray, or the like. The present embodiment is not limited thereto. For example, the ultraviolet ray may be an ordinary ultraviolet ray having a wavelength in a range of 200 nm to 400 nm, or may be an extreme ultraviolet ray having a wavelength in a range of 10 nm to 14 nm. The present embodiment is not limited thereto.
The present embodiment is described by taking a case where the photoresist layer 120 is exposed by using an ultraviolet ray as an example. For example, an illumination intensity used in the exposure of the photoresist layer 120 is 10 J/cm3-500 J/cm3.
For example, the illumination intensity used in the exposure of the photoresist layer 120 may be 50 J/cm3-80 J/cm3, so as to sufficiently expose the photoresist layer 120, but the present embodiment is not limited thereto.
For example, the illumination intensity used in the exposure of the photoresist layer 120 may be 80 J/cm3-200 J/cm3, 250 J/cm3-500 J/cm3 or 10 J/cm3-40 J/cm3, etc. The illumination intensity in the practical process can be determined according to the thickness of the photoresist layer 120.
For example, the photoresist includes a resin, a photosensitizer, a solvent, and an additive agent. Before the exposure, the photoresist layer 120 is required to be pre-baked, such that the solvent in the photoresist layer 120 can be sufficiently evaporated to dry the photoresist layer 120, enhance the adhesion between the photoresist layer 120 and a surface of the film 110, and improve the line resolution after the exposure. Generally, a temperature of the pre-baking may be set to about 90° C.-120° C. The present embodiment is not limited thereto, but the temperature of the pre-baking cannot be too high to prevent the photoresist layer 120 from melting and collapsing at a high temperature. Therefore, the temperature of the pre-backing in the present embodiment is not greater than 140° C. The pre-baked photoresist layer 120 can be more strongly bonded to the film 110 after the pre-baking.
For example, positive photoresist can be pre-baked in air, while negative photoresist needs to be pre-baked in a nitrogen atmosphere.
For example, the photoresist included in the photoresist layer 120 provided by the present embodiment is positive photoresist, and the positive photoresist includes, for example, a novolac. Upon no dissolution inhibitor being present, the novolac is dissolved in the developer; the photosensitizer in the positive photoresist includes a photo active compound (PAC). For example, the photo active compound may include diazonaphthoquinone (DNQ) or the like, which is not limited in the present embodiment. Before the exposure, diazonaphthoquinone is a strong dissolution inhibitor that reduces the dissolution rate of the resin.
For example, in an ultraviolet exposure process, the photo active compound such as diazonaphthoquinone is chemically decomposed in the positive photoresist by a photochemical reaction, to cut the relationship between a main chain and a dependent chain of the resin polymer, so as to achieve a purpose of weakening the polymer. Such that the photo active compound can become a solubility enhancer. Diazonaphthoquinone will produce a carboxylic acid in the exposure reaction, and the solubility of the carboxylic acid in the developer is high, so that the solubility of the exposed photoresist is increased in the subsequent development process, and solubility rate of the positive photoresist after the exposure is almost 10 times that of the unexposed photoresist. Therefore, after the positive photoresist layer 120 is exposed, the positive photoresist layer 120 in an exposed region is completely removed to form a blank region (a first region 121), and the photoresist layer 120 in an unexposed region remains on the film 110 as a subsequent protective film, and a pattern replicated onto a surface of the film 110 is the same as a pattern on a mask located above the photoresist layer 120.
For example, upon the time for development being insufficient, the photoresist layer 120 in the exposed region is unable to be completely dissolved during the development; upon the development time being too long, the photoresist layer 120 in the unexposed region may be dissolved from an edge of the pattern during the development, such that the edge of the pattern is deteriorated. Therefore, the time for developing the photoresist layer 120 in the present embodiment may be 10 s-500 s, and the present embodiment includes but is not limited thereto.
For example, the developer provided in the present embodiment may be a medium alkali solution. For example, the developer may include one or more materials selected from the group consisting of potassium hydroxide, tetramethylammonium hydroxide, ketone and acetazolamide, which is not limited in the present embodiment.
For example, as illustrated by
For example, as illustrated by
For example, the first size L1 is not less than 3 μm. It should be noted that, the first size L1 cannot be too large, generally, the first size L1 is in the micrometer range. For example, the first size L1 may be 6 μm-10 μm, and the present embodiment includes but is not limited thereto.
For example, a shape of an orthographic projection of a plane of the first region 121 having the first size L1 on the film 110 may include at least one selected from the group consisting of a circle and a line. That is, a planar pattern of the first region 121 may include at least one selected from the group consisting of a circle and a line. The present embodiment includes but is not limited thereto.
S103: post-baking the photoresist, so that the photoresist is melted and collapsed at a high temperature to change the region corresponding to the completely removed portion into a second region, and the photoresist after the post-baking forms into a mask pattern.
In the present embodiment, the photoresist coated on the film to be patterned is a hot-melt photoresist, and the heat-resistant composition in the hot-melt photoresist is less than that of an ordinary photoresist, so that the photoresist melts and collapses at a high temperature in a case of post-baking, without affecting the performance of the photoresist.
For example, as illustrated by
For example, the photoresist layer 120 having the first region 121 is post-baked, and the post-baking process may be performed at a temperature of 150° C.-200° C., or may be 250° C.-300° C., etc. The present embodiment is not limited herein.
For example, as illustrated by
For example, as illustrated by
For example, the second size 122 of the second region 122 may be 1 μm-2.5 μm, or may be 1.5 μm-2 μm, which is not limited in the present embodiment.
For example, a shape of the plane of the second region 122 having the second size L2 may include at least one selected from the group consisting of a circle and a line; that is, a planar shape of the second region 122 may include at least one selected from the group consisting of a circle and a line. It should be noted that, the circle may be an approximately circular shape, and for example, the shape of the plane of the second region 122 having the second size L2 may also be an ellipse or the like.
For example, as illustrated by
For example, the thickness of the photoresist layer 120 in the direction perpendicular to the film 110 may be 1.5 μm-2.2 μm, so that partial photoresist of the photoresist layer 120 around the first region 121 collapses and flows into the first region 121, and the second region 122 having a desired second size L2 is formed.
For example, the thickness of the photoresist layer 120 in the X direction may be 3 μm-5 μm, or the thickness of the photoresist layer 120 in the X direction may also be 7 μm-10 μm, which is not limited in the present embodiment.
For example, the time for post-baking the photoresist layer 120 in the present embodiment is 10 s-500 s.
For example, the photoresist layer 120 is post-baked for 10 s-50 s to cause the photoresist layer 120 around the first region 121 to melt and collapse to form the second region 122 having the desired second size L2.
For example, the time for post-baking the photoresist layer 120 in the present embodiment may be 100 s-200 s or 300 s-500 s, which is not limited in the present embodiment.
For example, an example of the present embodiment is described by taking a case where the film 110 is patterned to form an opening pattern as an example. In the present embodiment, the exposure equipment used for exposing the photoresist layer 120 before forming a pattern having an aperture size of 1 μm-2.9 μm on the film 110 generally has a limit precision of 3 μm, and the partial steps of forming the photoresist layer 120 having the second region 122 include: using a mask plate having an aperture size of 5 μm as a mask of a photoresist layer 120 with a thickness of 0.5 μm-10 μm (for example, the thickness may be 1.5 μm-2.2 μm); performing exposure to the photoresist layer 120, and light intensity during the exposure being 10 J/cm3-500 J/cm3, for example, the light intensity during the exposure may be 50 J/cm3-80 J/cm3; after exposure, performing development on the photoresist layer 120, and the time for development being selected from 10 s to 500 s; performing post-baking to the developed photoresist layer 120, and a temperature during the post-backing process being selected from 150° C. to 300° C., and the time for the post-baking time being selected from 10 s to 500 s, for example, the time for post-baking is 10 s-50 s. After the abovementioned exposure, development, and post-baking, the second region 122 having the second size L2 of 1 μm-2.9 μm is formed on the photoresist layer 120. Therefore, the film patterning method utilizes the characteristics of a hot-melt photoresist that melts and collapses at a high temperature after development and post-baking, to provide a possibility to form a pattern with a size smaller than the limit precision of an exposure equipment on a film to be patterned. The patterning method is simple in process, and has low costs.
S104: patterning the film by using the mask pattern as a mask.
For example, as illustrated by
For example, the film 110 can be patterned to form an opening 111 having the second size L2, that is, a pore size of the opening 111 is 1 μm-2.9 μm, and the embodiment includes but is not limited thereto.
For example, the film 110 can also be patterned to form a line shape 112 having a minimum size of the second size L2, that is, a size of a short edge of the line shape 112 (a length of an edge extending in the Y direction) is 1 μm-2.9 μm, and the present embodiment includes but is not limited thereto. It should be noted that,
For example,
For example, a planar shape of the opening 111 in the YZ plane may be a standard circular shape or an approximately circular shape, and the embodiment includes but is not limited thereto.
For example, the planar shape of the opening 111 in the YZ plane may also be an irregular shape or the like. It should be noted that,
For example, upon the film 110 being a gate insulating layer and/or an interlayer insulating layer, the photoresist layer 120 having the second region 122, i.e., the mask pattern, can be utilized as a mask to form a contact hole (i.e., the opening 111) for connecting a source electrode and a drain electrode with an active layer of a thin film transistor. Herein, the thin film transistor is a top gate type.
For example, upon the film 110 being an etch barrier layer, the photoresist layer 120 having the second region 122 can be utilized as a mask to form a contact hole (i.e., the opening 111) for connecting a source electrode and a drain electrode with an active layer of a thin film transistor.
For example, upon the film 110 being a passivation layer, the photoresist layer 120 having the second region 122 can be utilized as a mask to form a via hole (i.e., the opening 111) for exposing a drain electrode of a thin film transistor and a common electrode line, and the exposed drain electrode can be electrically connected with a subsequently formed pixel electrode through the via hole, the exposed common electrode line can be electrically connected with a subsequently formed common electrode through the via hole, and the present embodiment includes but is not limited thereto.
For example, the film 110 may also be other insulating layers or metal layers, etc., which is not limited in the present embodiment.
For example, as illustrated by
An embodiment of the present disclosure provides a manufacturing method of an array substrate.
S201: providing a base substrate.
For example, the base substrate may be made of one or more materials selected from the group consisting of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The embodiment includes but is not limited thereto.
S202: forming a film to be patterned on the base substrate.
For example, the film to be patterned may be formed on the base substrate by a method such as deposition or magnetron sputtering.
For example, the film may be an insulating layer. For example, the film may be a gate insulating layer, an interlayer insulating layer, a passivation layer or an etch barrier layer, and the like, which is not limited in the present embodiment.
For example, the film may include an inorganic material, such as a metal oxide, a metal sulfide, or a metal nitride, which is not limited in the present embodiment.
For example, the film may also be an organic material, and the organic material may include, for example, one or a combination of ones selected from the group consisting of polyimide, polyamide, polycarbonate, and epoxy resin, and the present embodiment is not limited thereto.
For example, the film may also be a metal layer. For example, the material of the film may be one or more materials selected from the group consisting of aluminum, silver, molybdenum, titanium, platinum, gold, and chromium. The present embodiment is not limited thereto, for example, the film can be other films.
S203: patterning the film by a film patterning method.
In the present embodiment, the film is patterned by using any film patterning method provided by the abovementioned embodiments, and the specific patterning processes and the parameters such as the shape and the size of the small-sized pattern obtained by patterning the film will not be repeated herein.
The manufacturing method of an array substrate utilizes the characteristics of a hot-melt photoresist that melts and collapses at a high temperature after development and post-baking, to provide a possibility to form a pattern with a size smaller than the limit precision of an exposure equipment on a film to be patterned. The patterning method is simple in process, and has low costs.
An embodiment of the present disclosure provides an array substrate, and the array substrate is manufactured by the manufacturing method of the array substrate provided by the abovementioned embodiments.
For example, a surface of a film included in the array substrate includes a film pattern having the substantially same shape with a planar shape of the second region of the photoresist layer, and a minimum size of the film pattern in a direction parallel to the plane where the film is located is a second size, i.e., a minimum size of the second region in the direction parallel to the plane where the film is located.
For example, the minimum size of the film pattern in the direction parallel to the plane where the film is located is 1 μm-2.9 μm.
For example, the minimum size of the film pattern in the direction parallel to the plane where the film is located may be 1 μm-2.5 μm, or may also be 1.5 μm-2 μm, which is not limited in the present embodiment.
For example, the array substrate can be applied to a display device such as a liquid crystal display device, an organic light emitting diode (OLED) display device, and any products or components having a display function and including the display device, such as a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, and a navigator. The present embodiment is not limited thereto.
The following points should to be explained:
(1) Unless otherwise defined, in the embodiments and accompanying drawings in the present disclosure, the same reference numeral represents the same meaning.
(2) The accompanying drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).
(3) For the purpose of clarity, in accompanying drawings for illustrating the embodiment(s) of the present disclosure, layer(s) or region(s) may be enlarged. However, it should understood that, in the case in which a component or element such as a layer, film, region, substrate or the like is referred to be “on” or “under” another component or element, it may be directly on or under the another component or element or a component or element is interposed therebetween.
The foregoing is only the embodiments of the present disclosure and not intended to limit the scope of protection of the present disclosure, alternations or replacements which can be easily envisaged by any skilled person being familiar with the present technical field shall fall into the protection scope of the present disclosure. Thus, the protection scope of the present disclosure should be based on the protection scope of the claims.
Wang, Jun, Yuan, Guangcai, Wang, Dongfang, Li, Guangyao, Fang, Chong
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
7592129, | Mar 04 2005 | OKI SEMICONDUCTOR CO , LTD | Method for forming photoresist pattern and method for manufacturing semiconductor device |
20060257785, | |||
20090130571, | |||
20100038649, | |||
20110001138, | |||
20170125546, | |||
CN101435992, | |||
CN102455593, | |||
CN104330196, | |||
CN104716092, | |||
CN105527801, | |||
CN107275195, |
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