A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance≤(0.9×T12/first distance), and/or (1.1×T12/first distance)≤depression formation distance<second distance.
|
1. A semiconductor device comprising:
a semiconductor chip; and
a substrate, including:
an insulating plate with a thickness of T1,
a conductive pattern with a thickness of T2, the semiconductor chip being mounted on a front surface of the conductive pattern, the insulating plate being positioned on a rear surface of the conductive pattern, and
a metal plate with a thickness of T3, the metal plate being positioned on a rear surface of the insulating plate, and having a plurality of depressions formed on a rear surface thereof,
wherein, in a side view of the semiconductor device,
a first edge face, which is an edge face of the conductive pattern, is, measured inwardly of the substrate in a horizontal direction along a main surface of the substrate, at a first distance away from a second edge face that is an edge face of the metal plate,
a third edge face, which is an edge face of the semiconductor chip, is, measured inwardly of the substrate in the horizontal direction, at a second distance away from the second edge face, and
each of the plurality of depressions is located within a depression formation distance, measured inwardly of the substrate in the horizontal direction, from the first edge face, the depression formation distance satisfying at least one of:
0<the depression formation distance≤(0.9×T12/the first distance), and (1.1×T12/the first distance)≤the depression formation distance<the second distance, each depression being entirely located between the first edge face and the third edge face in the side view.
2. The semiconductor device according to
the depression formation distance further satisfies at least one of:
0<the depression formation distance≤(0.8×T12/the first distance), and (1.2×T12/the first distance)≤the depression formation distance<the second distance. 3. The semiconductor device according to
the first distance satisfies:
0<the first distance≤(T22+T32−T12+2×T2×T3)1/2. 4. The semiconductor device according to
each of the plurality of depressions is formed on the metal plate, avoiding, in a planar view of the semiconductor device, a vicinity of each corner of the conductive pattern and of the metal plate.
5. The semiconductor device according to
the plurality of depressions are formed in a ring shape along the sides of the metal plate on the rear surface of the metal plate, avoiding the vicinity of each corner at an intersection where a line of the depressions along one side of the metal plate meets another line of the depressions along another side of the metal plate.
6. The semiconductor device according to
each of the plurality of depressions has a spherical cap shape or a spherical frustum shape, and is formed on the metal plate without penetrating the metal plate.
7. The semiconductor device according to
each of the plurality of depressions has a spherical frustum shape or a cylindrical shape, and is formed on the metal plate to penetrate the metal plate.
8. The semiconductor device according to
no further conductive pattern is formed outside the conductive pattern on which the semiconductor chip is disposed.
|
This application is a continuation application of International Application PCT/JP2019/046531 filed on Nov. 28, 2019 which designated the U.S., which claims priority to Japanese Patent Application No. 2019-005278, filed on Jan. 16, 2019, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein relate to a semiconductor device.
Semiconductor devices include semiconductor chips, for example, insulated gate bipolar transistors (IGBTs), power metal oxide semiconductor field effect transistor (power MOSFETs), and so forth. Such semiconductor devices are used, for example, as power converters. Semiconductor devices include the aforementioned semiconductor chips and a ceramic circuit substrate. The ceramic circuit substrate includes an insulating plate, a plurality of conductive patterns which is formed on the front surface of the insulating plate and on which the semiconductor chips are mounted, and a metal plate formed on the rear surface of the insulating plate. Further, on the rear surface of the ceramic circuit substrate, a heat radiating unit such as a heatsink is installed.
In recent years, ceramic circuit substrates are sometimes reduced in size in an effort to miniaturize semiconductor devices. However, layout areas on the ceramic circuit substrates, where semiconductor chips are mounted, need to be maintained. In addition, in order to provide semiconductor devices with desired functions, the semiconductor chip layout areas on the ceramic circuit substrates are sometimes increased without enlarging the ceramic circuit substrates. Therefore, in either case, the distance between the edge face of each conductive pattern and the edge face of the insulating plate (edge-to-edge distance) needs to be reduced.
In manufacturing a semiconductor device, semiconductor chips are mounted, via solder, onto a ceramic circuit substrate which is mounted onto a radiator plate via solder. Then, they are heated and subsequently cooled. Herewith, the semiconductor chips, the ceramic circuit substrate, and the radiator plate are held together by solder. The semiconductor device undergoes temperature changes associated with its own operation. The semiconductor device is also subjected to temperature changes in the external environment. Therefore, due to the insulating plate having a different coefficient of thermal expansion relative to the conductive patterns and the metal plate, the ceramic circuit substrate is subjected to thermal stress. This causes cracks in the insulating plate, thus decreasing the reliability of the semiconductor device. In view of this problem, dimples (depressions) are formed on the rear surface of the metal plate in the ceramic circuit substrate to relieve the thermal stress applied to the ceramic circuit substrate (see, for example, Description of U.S. Pat. No. 5,527,620).
However, cracks may occur in the insulating plate depending on where on the rear surface of the metal plate in the ceramic circuit substrate the dimples are located. The dimples therefore need to be formed at appropriate positions on the rear surface of the metal plate while reducing the edge-to-edge distance between the edge face of the insulating plate and that of each conductive pattern.
According to an aspect, there is provided a semiconductor device including: a semiconductor chip; and a substrate, including: an insulating plate with a thickness of T1, a conductive pattern with a thickness of T2, the semiconductor chip being mounted on a front surface of the conductive pattern, the insulating plate being positioned on a rear surface of the conductive pattern, and a metal plate with a thickness of T3, the metal plate being positioned on a rear surface of the insulating plate, and having a plurality of depressions formed on a rear surface thereof, wherein, in a side view of the semiconductor device, a first edge face, which is an edge face of the conductive pattern, is, measured inwardly of the substrate in a horizontal direction along a main surface of the substrate, at a first distance away from a second edge face that is an edge face of the metal plate, a third edge face, which is an edge face of the semiconductor chip, is, measured inwardly of the substrate in the horizontal direction, at a second distance away from the second edge face, and each of the plurality of depressions is located within a depression formation distance, measured inwardly of the substrate in the horizontal direction, from the first edge face, the depression formation distance satisfying at least one of: 0<the depression formation distance≤(0.9×T12/the first distance), and (1.1×T12/the first distance) the depression formation distance<the second distance.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
Several embodiments will be described below with reference to the accompanying drawings.
A semiconductor device according a first embodiment is described with reference to
The semiconductor device 1 includes the semiconductor chip 2, the ceramic circuit substrate 3 on which the semiconductor chip 2 is mounted, and the radiator plate 4 with the ceramic circuit substrate 3 fitted thereto. On the rear surface of the ceramic circuit substrate 3, dimples 3c2 which are depressions are formed. The semiconductor chip 2 and the ceramic circuit substrate 3 are joined together via a bonding member such as solder 5a. In addition, the ceramic circuit substrate 3 and the radiator plate 4 are joined together via a bonding member such as solder 5b. Note that the semiconductor chip 2 may be provided in plurality on the ceramic circuit substrate 3 according to desired functions. Similarly, the ceramic circuit substrate 3 with the multiple semiconductor chips 2 installed according to the desired functions may also be provided in plurality on the radiator plate 4. Note however that the following describes an example where one set of the semiconductor chip 2 and the ceramic circuit substrate 3 is provided on the single radiator plate 4. In addition, although no illustration is given here, the semiconductor device 1 may be housed in a case provided with an external connecting terminal, and then a sealing resin may be used to seal off the inside of the case. In this case, the external connecting terminal (not illustrated) is electrically connected to the semiconductor chip 2 and the ceramic circuit substrate 3 using a wire or lead frame appropriately.
The semiconductor chip 2 may be a power semiconductor chip. The semiconductor chip 2 includes, for example, a switching element, such as an IGBT or power MOSFET. This semiconductor chip 2 includes, for example, an input electrode (a drain electrode or collector electrode) on the rear surface as a main electrode, and a control electrode (a gate electrode) and, as a main electrode, an output electrode (a source electrode or emitter electrode) on the front surface. The rear surface of the aforementioned semiconductor chip 2 is joined to the conductive pattern 3b by the solder 5a. The semiconductor chip 2 may include a diode, such as a Schottky barrier diode (SBD) or free wheeling diode (FWD). In this case, the semiconductor chip 2 includes an output electrode (cathode electrode) on its rear surface as a main electrode and an input electrode (anode electrode) on its front surface as a main electrode. The semiconductor chip 2 may be a reverse-conducting IGBT (RC-IGBT), which integrates an IGBT and FWD into one chip. The semiconductor chip 2 has a third edge face 2a1 on its side. The third edge face 2a1 faces the dimples 3c2 outwardly in a horizontal direction along a major surface of the ceramic circuit substrate 3. Further, the third edge face 2a1 is an edge face of the semiconductor chip 2, located closest to the dimples 3c2. In the case where a plurality of semiconductor chips 2 is provided on the ceramic circuit substrate 3, the third edge face 2a1 is an edge face located closest to the dimple 3c2 among the edge faces of the multiple semiconductor chips 2.
The ceramic circuit substrate 3 includes an insulating plate 3a, the conductive pattern 3b formed on the front surface of the insulating plate 3a, and a metal plate 3c formed on the rear surface of the insulating plate 3a. As for the conductive pattern 3b, the shape and number thereof are just an example. The insulating plate 3a is made of ceramics with high thermal conductivity, such as aluminum oxide, aluminum nitride, or silicon nitride, which conduct heat well. The insulating plate 3a has a thickness of T1. The conductive pattern 3b is made of metal with excellent electrical conductivity, such as copper or a copper alloy. The conductive pattern 3b has a first edge face 3b1 on its side. The first edge face 3b1 has a thickness of T2. The first edge face 3b1 faces outwardly in a horizontal direction along the major surface of the ceramic circuit substrate 3 and is located outwardly from the dimples 3c2. The metal plate 3c is made of metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy composed of at least one of these. The metal plate 3c has a second edge face 3c1 on its side. The second edge face 3c1 has a thickness of T3. The second edge face 3c1 faces outwardly in a horizontal direction along the major surface of the ceramic circuit substrate 3 and is located outwardly from the first edge face 3b1. As the ceramic circuit substrate 3 configured as described above, a direct copper bonding (DCB) substrate or active metal brazed (AMB) substrate may be used, for example. Note that the thicknesses T1, T2, and T3 of the insulating plate 3a, the conductive pattern 3b, and the metal plate 3c are preferably in the range of 0.05 mm to 2.00 mm inclusive, and more preferably in the range of 0.10 mm to 0.65 mm inclusive.
On the rear surface of the metal plate 3c in the ceramic circuit substrate 3, the dimples 3c2 which are depressions are formed. The dimples 3c2 are aligned in an array along the outer periphery of the rear surface of the metal plate 3c, as illustrated in
The ceramic circuit substrate 3 is joined to the radiator plate 4 via the solder 5b. Herewith, the ceramic circuit substrate 3 conducts heat generated in the semiconductor chip 2 through the conductive pattern 3b, the insulating plate 3a, and the metal plate 3c to the radiator plate 4 depicted in the lower part of
In the above-described ceramic circuit substrate 3, the first edge face 3b1 of the conductive pattern 3b is located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3 at a first distance (d1) away from the second edge face 3c1 of the metal plate 3c. In other words, the first distance (d1) is an edge-to-edge distance between the first edge face 3b1 of the conductive pattern 3b and the second edge face 3c1 of the metal plate 3c. In this case, the first distance (d1) is more than 0 mm but 0.60 mm or less, and more preferably more than 0 mm but 0.30 mm or less. The third edge face 2a1 of the semiconductor chip 2 is located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3 at a second distance (d2) away from the second edge face 3c1 of the metal plate 3c. In addition, the third edge face 2a1 of the semiconductor chip 2 is located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3 at a fourth distance (d4) away from the first edge face 3b1 of the conductive pattern 3b.
Next described is the location where each dimple 3c2 is formed. Note that the location where each dimple 3c2 is formed refers to a site which encompasses the entire dimple 3c2. For example, in the case of the dimple 3c2 depicted in
The depression formation distance from the first edge face 3b1 of the conductive pattern 3b falls in at least one of the following ranges:
0<depression formation distance≤(0.9×T12/first distance (d1)), and
(1.1×T12/first distance (d1))≤depression formation distance<second distance (d2) (1).
The radiator plate 4 is made of a material with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy composed of at least one of these. In order to provide improved corrosion resistance, for example, nickel plating or the like may be applied to coat the surface of the radiator plate 4. Specifically, other than nickel, a nickel-phosphorus alloy or nickel-boron alloy may be used. Note that, to improve heat dissipation, a cooler (not illustrated) may be provided on the rear surface of the radiator plate 4. As the cooler, a fin, a heatsink with a plurality of fins, or a water cooling system may be used, for example. In addition, the radiator plate 4 may be integrally formed with such a cooler. In that case, the radiator plate 4 is made of a material with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy composed of at least one of these. Then, in order to provide improved corrosion resistance, for example, nickel plating or the like may be applied to coat the surface of the radiator plate 4 integrally formed with the cooler. Specifically, other than nickel, a nickel-phosphorus alloy or nickel-boron alloy may be used.
The aforementioned expression (1) is explained next. In this connection, the direction of a crack induced in the insulating plate 3a according to the first distance (d1), which is the edge-to-edge distance between the first edge face 3b1 of the conductive pattern 3b and the second edge face 3c1 of the metal plate 3c in the ceramic circuit substrate 3, is first described with reference to
distance between Points A and B(D)=(T12+d12)1/2 (2).
First, in the case of the first distance (d1) being about 1.10 mm (see the graph of
Next, even when the first distance (d1) is made shorter than the state depicted in
When the first distance (d1) is progressively made even shorter than the state depicted in of
When the first distance (d1) is progressively made even shorter than the state depicted in
Finally, when the first distance (d1) is made further shorter to be 0 mm such that the distance (D) between Points A and B becomes T1, which is shorter than the sum (T2+T3) of the thicknesses T2 and T3 (i.e., D=T1<T2+T3), the stress orientation and the direction of crack propagation shift back to the state depicted in
Therefore, according to the graph of
first distance (d1)=(T22+T32−T12+2×T2×T3)1/2 (3).
When the first distance (d1) is 0 mm, a crack is likely to develop in a horizontal direction along the front surface of the insulating plate 3a, propagating inwardly from Point A. Note that if the first distance (d1) is less than 0 mm, i.e., if the conductive pattern 3b is longer than the metal plate 3c, a crack may develop in the conductive pattern 3b, beginning at Point B. In addition, grooves on the conductive pattern 3b, corresponding to a circuit pattern, make a crack even more likely to propagate. In view of these considerations, the first distance (d1) preferably falls in the range defined by the following expression (4). In the case of the graph of
0<first distance (d1)≤(T22+T32−T12+2×T2×T3)1/2 (4).
Next described is where on the rear surface of the metal plate 3c in the above-described ceramic circuit substrate 3 the dimples are formed, with reference to
e=T12/d1 (5).
If the dimple 3c2 is located at a crack propagation front, the crack may develop into the dimple 3c2. For this reason, the dimples 3c2 need to be formed on the rear surface of the metal plate 3c in the ceramic circuit substrate 3, avoiding the crack propagation front. A crack propagates not only linearly but sometimes in a slightly curved manner from the crack origin. Given the possibility of a crack propagating in a slightly curved manner from the crack origin, the displacement range of the crack propagation front is set to preferably ±10%, more preferably ±20%. Another consideration is that if the dimples 3c2 are formed in an area just below the semiconductor chip 2, the heat dissipation of the semiconductor chip 2 is significantly impaired, which is not preferable. Hence, the dimples 3c2 need to be positioned more outwardly than the third edge face 2a1 of the semiconductor chip 2. In view of the above considerations, the ranges where the dimples 3c2 are formed are defined, using the edge-to-edge distance (e) measured from Point A on the edge face 3b1 of the conductive pattern 3b, preferably by expression (6), and more preferably by expression (7) below.
0<edge-to-edge distance (e)≤(0.9×T12/first distance (d1)), and
(1.1×T12/first distance (d1))≤edge-to-edge distance (e)<second distance (d2) (6).
0<edge-to-edge distance (e)≤(0.8×T12/first distance (d1)), and
(1.2×T12/first distance (d1))≤edge-to-edge distance (e)<second distance (d2) (7).
Note here that the edge-to-edge distance (e) between Point A on the first edge face 3b1 of the conductive pattern 3b and Point C, which is a crack propagation front on the metal plate 3c, corresponds to the ranges of the depression formation distance which are the formation ranges of the dimples 3c2. Hence, expression (1) is obtained from expression (6). Similarly, expression (7) is rewritten as expression (8) below.
The depression formation distance from the first edge face 3b1 of the conductive pattern 3b falls in at least one of the following ranges:
0<depression formation distance≤(0.8×T12/first distance (d1)), and
(1.2×T12/first distance (d1))≤depression formation distance<second distance (d2) (8).
In the ceramic circuit substrate 3 of
The above-described semiconductor device 1 includes the semiconductor chip 2 and the ceramic circuit substrate 3 including the conductive pattern 3b with a thickness of T2, on the front surface of which the semiconductor chip 2 is mounted, the insulating plate 3a with a thickness of T1, which is positioned on the rear surface of the conductive pattern 3b, and the metal plate 3c with a thickness of T3, which is positioned on the rear surface of the insulating plate 3a and has the dimples 3c2 formed on its rear surface. When the semiconductor device 1 is viewed from the side, the first edge face 3b1 of the conductive pattern 3b is located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3 at the first distance (d1) away from the second edge face 3c1 of the metal plate 3c. In addition, the third edge face 2a1 of the semiconductor chip 2 is located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3 at the second distance (d2) away from the second edge face 3c1. Further, the dimples 3c2 are located inwardly of the ceramic circuit substrate 3 in a horizontal direction along the main surface of the ceramic circuit substrate 3, at a distance from the first edge face 3b1. Specifically, the location where the dimples 3c2 are formed is defined as expression (1) above. Furthermore, the first distance (d1) preferably satisfies expression (4) above. The formation of the dimples 3c2 on the rear surface of the metal plate 3c in this manner reduces stress acting on the insulating plate 3a, thus preventing a crack from developing. Especially, because the dimples 3c2 are not formed near the corners of the metal plate 3c, it is possible to prevent development of cracks in the insulating plate 3a around the corners of the conductive pattern 3b. This prevents degradation in the quality of the semiconductor device 1 and thus leads to improved yield, thereby increasing the reliability.
A second embodiment is directed to the case where dimples provided on the rear surface of the metal plate 3c in the ceramic circuit substrate 3 penetrate the metal plate 3c, which is described with reference to
The semiconductor device 1a includes the semiconductor chip 2, a ceramic circuit substrate 30 on which the semiconductor chip 2 is mounted, and the radiator plate 4 with the ceramic circuit substrate 30 fitted thereto. Although no illustration is given here, the semiconductor device 1a is also housed in a case provided with an external connecting terminal. A sealing resin may be used to seal off the inside of the case. In this case, the external connecting terminal (not illustrated) is electrically connected to the semiconductor chip 2 and the ceramic circuit substrate 30 using a wire appropriately.
The ceramic circuit substrate 30 includes the insulating plate 3a, the conductive pattern 3b formed on the front surface of the insulating plate 3a, and a metal plate 30c formed on the rear surface of the insulating plate 3a. The metal plate 30c is made of metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy composed of at least one of these. The metal plate 30c has a second edge face 30c1 on its side. Further, dimples 30c2 which are depressions are formed on the rear surface of the metal plate 30c. These multiple dimples 30c2 are aligned in an array along the outer periphery of the rear surface of the metal plate 30c, as in the case of the dimples 3c2 of the first embodiment illustrated in
According to the semiconductor device 1a, the formation of the dimples 30c2 on the rear surface of the metal plate 30c also reduces stress acting on the insulating plate 3a, thus preventing cracks from developing, as in the case of the semiconductor device 1 of the first embodiment. This prevents degradation in the quality of the semiconductor device 1a and thus leads to improved yield, thereby increasing the reliability.
According to one aspect, it is possible to relieve stress applied to the substrate while securing the layout area for the semiconductor chips, thus enhancing the reliability of the semiconductor device.
All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Oda, Yoshinori, Uezato, Yoshinori
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
5527620, | Jun 02 1993 | CURAMIK HOLDING GMBH, IN LIQUIDATION | Metal coated substrate having improved resistivity to cyclic temperature stress |
20030173660, | |||
20080164588, | |||
20180005956, | |||
20200194386, | |||
DE112019001086, | |||
EP1345480, | |||
EP3264869, | |||
JP2003100965, | |||
JP2003273289, | |||
JP2006140401, | |||
JP2012114203, | |||
JP2015225948, | |||
WO2019167509, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 11 2020 | ODA, YOSHINORI | FUJI ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 055562 | /0984 | |
Dec 11 2020 | UEZATO, YOSHINORI | FUJI ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 055562 | /0984 | |
Dec 28 2020 | Fuji Electric Co., Ltd. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Dec 28 2020 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Date | Maintenance Schedule |
Dec 06 2025 | 4 years fee payment window open |
Jun 06 2026 | 6 months grace period start (w surcharge) |
Dec 06 2026 | patent expiry (for year 4) |
Dec 06 2028 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 06 2029 | 8 years fee payment window open |
Jun 06 2030 | 6 months grace period start (w surcharge) |
Dec 06 2030 | patent expiry (for year 8) |
Dec 06 2032 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 06 2033 | 12 years fee payment window open |
Jun 06 2034 | 6 months grace period start (w surcharge) |
Dec 06 2034 | patent expiry (for year 12) |
Dec 06 2036 | 2 years to revive unintentionally abandoned end. (for year 12) |