By providing, in a field-frequency doubling circuit comprising a converter circuit (3) of an A, A, B, B, type, an interpolation circuit (31) which combines, in an appropriate manner, the information of two subjacent lines of a first field of a picture of the television signal to be converted and a second field of a picture of the television signal to be converted, line flicker can be prevented from occurring without it being necessary to provide a movement detector and a change-over switch for an A, B, A, B-type conversion.

Patent
   4603351
Priority
Sep 05 1984
Filed
Aug 30 1985
Issued
Jul 29 1986
Expiry
Aug 30 2005
Assg.orig
Entity
Large
6
5
EXPIRED
1. A field-frequency doubling circuit, comprising a converter circuit for converting an interlaced television signal, having a picture frequency of n pictures per second and a field frequency of 2n fields per second, into a converted television signal having a field frequency of 4n fields per second, the fields of the converted television signal having substantially the same number of lines as the fields of the interlaced television signal and every two consecutive fields of the converted television signal being equal to each other, said field-frequency doubling circuit further comprising, coupled to an output of the converter circuit, an interpolation circuit for adding together informatin from some of the lines of the converted television signal in each line period of the converted television signal, characterized in that the interpolation circuit comprises a change-over switch for interpolating, for each group of four fields of the converted television signal during a first and a third field of said group, between a line of the converted television signal corresponding to a line of a first field of a picture of the interlaced television signal, and a line of the converted television signal corresponding to a subjacent line of a second field of a picture of the interlaced television signal, and, during a second and a fourth field of said group, between a line of the converted television signal corresponding to a line of the first field of a picture of the interlaced television signal, and a line of the converted television signal, corresponding to a superjacent line of the second field of a picture of the interlaced television signal.
2. A field-frequency doubling circuit as claimed in claim 1, characterized in that the field interpolation circuit comprises a series arrangement of a delay line producing a delay of two field periods minus a line period of the converted television signal and a delay line producing a delay of one line period of the converted television signal and change-over summing means coupled to an input of said interpolation circuit and an output of each of the delay lines, with which, alternatingly, a sum of the input signal of the interpolation circuit and an output signal of each of the delay lines is obtained.

The invention relates to a field-frequency doubling circuit, comprising a converter circuit for converting an interlaced television signal, having a picture frequency of n pictures per second and a field-frequency of 2n fields per second, into a converted television signal having a field frequency of 4n fields per second, the fields of the converted television signal having substantially the same number of lines as have the fields of the interlaced television signal to be converted and every two consecutive fields of the converted television signal being equal to each other, and comprising, coupled to an output of the converter circuit, an interpolation circuit for adding together information from some of the lines of the converted television signal in each line period of the converted television signal.

U.S. Pat. No. 4,435,728, which corresponds to Netherlands Patent Application 8100603 (PHN 9947), discloses a field-frequency doubling circuit of the above-defined type, which comprises a movement detector which, in the absence of movement switches the circuit to a type of conversion in which the fields of the converted television signal alternately correspond to a first and a second field of the television signal to be converted. The interpolation proposed for the case in which there is movement, relates to combining information from two consecutive lines of a field of the converted television signal.

The invention has for its objects a circuit from which a movement detector and a change-over of the type of conversion can be omitted.

Therefore, according to the invention, a field-frequency doubling circuit of the type defined in the opening paragraph, is characterized in that the interpolation circuit comprises a change-over switch for interpolation, for each group of four fields of the converted television signal during the first and third fields of this group, between a line of the converted television signal, corresponding to a line of a first field of a picture of a television signal to be converted, and a line corresponding to a subjacent line of the second field of a picture of the television signal to be converted, and, during the second and fourth fields of this group, between a line of the converted television signal corresponding to a line of the first field and a line of the converted television signal corresponding to a superjacent line of the second field of a picture of the television signal to be converted.

When this measure is applied, it is no longer necessary to switch to a different type of conversion when there is no movement in the picture in order to eliminate not only zonal flicker but also the line flicker.

The invention will now be described in detail, by way of example, with reference to the accompanying drawings. In the drawing:

FIG. 1 illustrates, by means of a block circuit diagram, a possible embodiment of a field-frequency doubling circuit according to the invention; and

FIG. 2 is a time diagram for conversion and interpolation for the circuit of FIG. 1.

In FIG. 1, a television signal to be converted is applied to an input 1 of a converter circuit 3. The converter circuit 3 has a further input 5 to which a write clock signal is applied, an input 7 to which a read clock signal, having twice the frequency of the write clock signal, is applied and an input 9 to which a switching signal is applied. These signals are produced by a pulse generator 11.

The converter circuit 3 comprises a switching arrangement 13, 15, 17, 19, 21 and two field delay lines 23, 25. In response to the switching signal applied to the input 9, a converted television signal is obtained at an output 27 of the converter circuit 3. This converted television signal is applied to an input 29 of an interpolation circuit 31.

The input 29 of the interpolation circuit 31 is connected to an input 33 of a delay line 35, producing a time delay of two field periods minus one line period of the converted television signal, to an input 37 of a first adder circuit 39 and to an input 41 of a second adder circuit 43. A further input 45 of the first adder circuit 39 is connected to an output 47 of the delay line 35 and a further input 49 of the second adder circuit 43 is connected to an output 51 of a delay line 53, producing a delay of one line period of the converted television signal.

A change-over switch 57 connects an output 59 of the interpolation circuit 31 to an output 61 of the first adder circuit 39 or to an output 63 of the second adder circuit 43. The change-over switch 57 is operated by a switching signal applied to an input 65 of the interpolation circuit 31 and produced by the pulse generator 11. The operation of the circuit will now be described in detail with reference to FIG. 2. In FIG. 2 reference numerals 201, 227, 251, 247, and 259, respectively, denote the time diagram of the signals at the input 1, the output 27 of the converter circuit 3, the output 51 of the delay line 53, the output 47 of the delay line 35, and the output 59 of the interpolation circuit 31, respectively. The respective waveforms 209 and 265 represent the switching signal at the input 9 of the converter circuit 3 and at the input 65 of the interpolation circuit 31, respectively.

The fields A1, B1, A2, B2, A3 and B3, denoted in FIG. 2 by reference numeral 201, and which produce at the output 27 the fields A1, A1, B1, B1, A2, A2, B2, B2, A3, A3, denoted by 227 in FIG. 2, of the converted television signal with twice the field frequency of the television signal to be converted, occur sequentially at the input 1 of the converter circuit 3. In the television signal to be converted, the interlaced fields Ax and Bx form together one picture.

The signal A1b, A1b, B1b, B1b, A2b, A2b, B2b, B2b, which is denoted by reference numeral 251 in FIG. 2 and is delayed through two field periods of the converted television signal relative to the signal 227, is produced at the output 51 of the delay line 53. The signal A1a, A1a, B1a, B1a, A2a, A2a, B2a, B2a, which, relative to the signal 227, is delayed through two field periods minus one line period of the converted television signal, appears one line period of the converted television signal earlier at the output 47 of the delay line 35 than the signal 251 at the outputs 51 of the delay line 53.

In a period T corresponding to four field periods of the converted television signal, the interpolated signals (A2 +B1b), (A2 +B1a), (A2a +B2) and (A2b +B2), respectively, which in FIG. 2 are denoted by reference numeral 259, are obtained at the output 59 of the interpolation circuit 31. For this it holds that:

In the first field period of the period T, the lines of the field A2 which occur simultaneously with the lines of the field B1b, correspond to lines from an A-field and a B-field of the television signal to be converted, in which a corresponding line from the A-field is located above the line of the B-field.

In the second field period of period T, the lines of the field A2 which occur simultaneously with those of the field B1a, correspond to lines from an A-field and a B-field of the television signal to be converted, in which a corresponding line from the A-field is located below the line of the B-field.

In the third field period T, the lines of the field A2a which occur simultaneously with those of the field B2, correspond to the lines from an A-field and a B-field, in which a corresponding line of the A-field is located above the line of the B-field.

In the fourth field period of the period T, the lines of the field A2b which occur simultaneously with those of the field B2, correspond to lines of an A-field and a B-field of the television signal to be converted, in which a corresponding line of the A-field is located below the line of the B-field.

The switch 57 of the interpolation circuit 31 then is in the position shown in the drawing when the waveform 265 is in the low state and in the position not shown when the waveform 265 is in the high state.

The switching arrangement 13, 15, 17, 19, 21 of the converter circuit 3 is in the position shown when the waveform 209 is in the high state and in the position not shown when the waveform 209 is in the low state.

In the interpolation circuit 31, the first adder circuit 39 may be omitted if instead, the change-over switch 57 alternately connects the input 49 of the second adder circuit 43 to the output 51 of the delay line 53 or to the output 47 of the delay line 35.

If so desired, the delay lines 35 and 53 may be interchanged.

Vreeswijk, Franciscus W. P., Tan, Sing L.

Patent Priority Assignee Title
4701793, Apr 11 1986 RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE Television display system with flicker reduction processor
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5243422, Nov 13 1990 Hitachi, Ltd. Field converting method for television signals and device for realizing same
5469217, Nov 04 1992 U.S. Philips Corporation Arrangement for doubling the field frequency of a picture signal
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Executed onAssignorAssigneeConveyanceFrameReelDoc
Aug 30 1985U.S. Philips Corporation(assignment on the face of the patent)
Oct 16 1985VREESWIJK, FRANCISCUS W P U S PHILIPS CORPORATION, A CORP OF DEASSIGNMENT OF ASSIGNORS INTEREST 0045160284 pdf
Feb 17 1986TAN, SING L U S PHILIPS CORPORATION, A CORP OF DEASSIGNMENT OF ASSIGNORS INTEREST 0045160284 pdf
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