An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory bank for use in computers, or other applications requiring high-density on-board memory. The high-density integrated circuit packages which form the modules each have an internal lead frame and optional internal member which overlie an integrated circuit die. A thin, warp-resistant metal layer and an external heat conductor element are mounted to the exterior of the package. Heat is dissipated from the package while structural forces are selectively balanced.

Patent
   5644161
Priority
Mar 29 1993
Filed
Jun 07 1995
Issued
Jul 01 1997
Expiry
Jul 01 2014
Assg.orig
Entity
Large
92
79
EXPIRED
1. An ultra-high density memory module, comprising:
a plurality of high density memory integrated circuit packages, wherein each package comprises:
an integrated circuit die;
a substantially planar internal lead frame mounted to at least a portion of said die, said internal lead frame having a plurality of electrical conductors electrically connected to said die;
a protective casing covering said die and said internal lead frame, wherein a plurality of said conductors extend from said internal lead frame, as leads, through a first edge of said casing;
a substantially planar thermally conductive internal element within said casing which is in thermal contact with at least a portion of said die; and
a substantially planar external thermally conductive element mounted to an exterior major surface of said casing,
wherein an edge portion of said thermally conductive internal element extends through a second edge of said casing opposite said first casing edge;
wherein a thin, warp-resistant metal layer is mounted to an exterior major surface of said casing of at least one of said packages, said metal layer being mounted to a major surface of said casing opposite said external thermally conductive element; and
wherein said packages are vertically oriented and mounted to one another to form said module.
2. The module of claim 1, wherein said thin, warp-resistant metal layer comprises is an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel.
3. The module of claim 1, further comprising a thin layer of reworkable adhesive mounted to a major surface of said thin, warp-resistant metal layer or to a major surface of said external thermally conductive element.
4. The module of claim 1, wherein said thermally conductive internal element is attached to said die with a two-sided polyimide film having a thin layer of high temperature epoxy on both sides of said film.
5. The module of claim 1, wherein said internal lead frame is attached to said die with a two-sided polyimide film having a thin layer of high temperature epoxy on both sides of said film.
6. The module of claim 1, wherein said thin, warp-resistant metal layer is attached to said casing with a thin layer of epoxy.
7. The module of claim 1, wherein said internal lead frame comprises nickel and iron.
8. The module of claim 1, wherein said external thermally conductive element is attached to said casing with a thin layer of epoxy.
9. The module of claim 1, wherein said external thermally conductive element comprises copper.
10. The module of claim 1, wherein said thin, warp-resistant metal layer, said thermally conductive internal element and said external thermally conductive element of each package each have an end portion which extends outward from said second edge of said casing and wherein said end portions form a thermally conductive platform.
11. The module of claim 10, further comprising a heat conduction cap which is in thermal contact with said thermally conductive platform of each said package comprising said module.
12. The module of claim 11, wherein said cap is comprised of metal.
13. The module of claim 1, wherein a plurality of said internal lead frame electrical conductors include a relief portion formed therein.
14. The module of claim 13, wherein said relief portion comprises an "S" shaped portion formed in at least one said internal lead frame conductor between said conductor distal end and said conductor die bond end.
15. The module of claim 1, further comprising a mounting header, wherein said leads of said packages are electrically connected to said header.
16. The module of claim 1, wherein said external thermally conductive element and said thin, warp-resistant metal layer of adjacent packages in said module are mounted to one another with a reworkable adhesive.
17. The module of claim 10, wherein said packages are mounted to one another such that said external thermally conductive element end portion and said thin metal layer end portion of adjacent packages in said module at least partially overlap and are in thermal contact with each other.

This application is a continuation-in-part of application Ser. No. 08/280,968, filed Jul. 27, 1994, U.S. Pat. No. 5,581,121 which is a division of application Ser. No. 08/037,830, filed Mar. 29, 1993, U.S. Pat. No. 5,369,056.

1. Field of the Invention

This invention relates to an ultra-high density integrated circuit module. More particularly, this invention relates to an ultra-high density warp-resistant integrated circuit memory module having in-line leads.

2. Discussion of Related Technology

As computer systems, and other electronic equipment, become more complex, the never-ending need for smaller, higher density memory devices persists. One approach to achieving this desired goal is a high-density electronic module formed of a plurality of stacked integrated circuit memory die (chips) disposed within a casing, typically hermetically sealed, and placed on a substrate and/or lead frame connection to a printed circuit board. Examples of such high-density memory devices are described in U.S. Pat. Nos. 4,983,533, 5,104,820, 4,764,846, and 4,706,166, all of which are assigned to Irvine Sensors Corporation of Costa Mesa, Calif.

In some instances, utilizing modules of stacked integrated circuit memory devices disposed within a single enclosure provides inadequate thermal dissipation, resulting in overheating. Additionally, if one of the chips within the memory module fails during operation, the entire module must be disconnected from the circuit board, the hermetic enclosure removed and opened, the faulty chip replaced and the module reassembled and reconnected. Otherwise, to expedite trouble shooting, the entire module would need to be replaced, necessitating the costly replacement of an entire high-density memory module. The basic technology for an improved high-density integrated circuit package utilizing enhanced heat dissipation characteristics is described in application Ser. No. 07/990,334, filed Dec. 11, 1992, U.S. Pat. No. 5,484,959, assigned to the assignee of the present invention.

In the past, one area of concentration for high density packaging has been memory devices such as SRAMs and DRAMs. Prior systems typically utilized a transfer molded plastic encasement surrounding the integrated circuit and having one of a variety of pin-out or mounting and interconnect schemes. The older M-DIPs (Dual-In-Line-Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounted to an underlying circuit board substrate. These packages provided 100 mil spacing between leads.

A more dense package was the 100 mil SIP (Single-In-Line-Plastic), which was assembled on edge with two rows of 100 mil staggered leads extending from the bottom edge for through-hole assembly. Another popular prior art package is the PLCC (Plastic Leaded Chip Carrier), SOJ (Small Outline J-leaded) molded package with twenty surface-mount designed J-leads (length 0.67", width 0.34", height 0.14").

Higher density versions of the SIMM (Single-In-Line Memory Module) design with even smaller versions of the DRAM plastic package have been developed. These thinner versions of SOJ DRAMs are one-half the thickness (having a plastic packaging thickness of about 70 mils) of standard SOJ designs, and have been mounted on both sides of circuit board substrates.

An example of a fabrication method and apparatus for lead-on chip integrated circuits having improved thermal dissipation characteristics is more fully described in U.S. Pat. No. 5,221,642; Patent Cooperative Treaty International Application No. PCT/US92/06778; and U.S. patent application Ser. No. 07/783,737, filed on Oct. 28, 1991, U.S. Pat. No. 5,498,450 each having the common assignee of the present invention.

The present invention is for an ultra high-density memory module which includes a plurality of integrated circuit memory packages, each memory package including an integrated circuit die within a protective casing. The integrated circuit memory packages are stacked, adhered to each other and connected, through in-line leads which extend from an edge of each package, to a printed circuit board. No additional enclosure is required.

The present invention provides a system and method for dissipating heat from a ultra high-density memory module while selectively controlling warpage through equalization of thermally affected structural forces. Heat is dissipated from each package through a substantially planar, external, thermally conductive element mounted externally to a major surface of the package. An internal lead frame disposed within the casing and overlaying a portion of the internal die functions to provide package stiffness in a preferred embodiment, and may be used to improved thermal conductivity in applications manifesting extreme heat stress. Rigidity may be further controlled through an optional substantially planar internal element that may also be chosen to dissipate heat for extreme applications.

An external, thin warp-resistant metal layer, typically INVAR, an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel, mounted to an external major surface of the package exterior provides equalization of structural forces contributed by the external thermally conductive element mounted on an opposite planar surface. The thin warp-resistant metal layer, the externally mounted thermally conductive element, the lead frame and the optional internal element cooperate to control structural forces within the package. Thus, each memory package has structurally balanced, warpage and heat control layers.

The heat conduction elements of the invention may be preferentially exposed from one end of the package to provide a platform suitable for heat extraction through an added heat pipe or conduction apparatus. After a plurality of packages are vertically stacked and adhered together with a fracturable, or reworkable, adhesive to form an ultra high-density memory module, a heat conduction cap is attached to the conduction platform to contact thermally conductive elements disposed along the same edge of each package within the memory module. In a preferred embodiment, a thermally conductive grease is applied between the platform and heat pipe or conduction cap to improve thermal conductivity away from the package. The platform may be spring-biased for better contact. The heat conduction cap may be cooled by liquid nitrogen, liquid oxygen, or other super-cooled gas, or may be a tinned or unfinned heat sink.

In order to achieve an extremely high-density memory bank for computers or other applications requiring large on-board memories, a plurality of ultra high-density memory modules may be grouped together. The modules may be separated from each other by a spacer gap in order to facilitate heat transfer and easy removal of individual memory modules for maintenance purposes.

Typically, each memory module includes ten high-density integrated circuit memory packages. If one of the memory packages is defective, the module containing the defective package can be removed from the printed circuit board without effecting the remaining high-density memory modules. The defective package is separated from the remaining packages in the module. After the defective package is replaced, the individual packages are re-adhered to each other with fracturable adhesive, and then inserted back into the printed circuit board as a module.

The above embodiments of the present invention improve the thermal conductivity between the integrated circuit memory package of each module and the external environment. The present invention also improves packaging density and heat dissipation characteristics of high-density memory modules.

In contrast to prior art technology, the fabrication method and apparatus of the present invention also provides warp-resistant ultra-high density integrated circuit memory modules that are thermally and mechanically balanced to prevent the ultra-thin profile packages that comprise the modules, and the modules themselves, from warping.

In an alternative embodiment, a thin layer of material with a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of silicon and preferably approximately equal to that of the casing material is mounted to an exterior major surface of the integrated circuit package to prevent warping. The material with a coefficient of thermal expansion that is greater than that of silicon may be, for example, aluminum or copper.

In a preferred embodiment, to prevent warpage, a thin layer of material with a coefficient of thermal expansion that is less than the coefficient of thermal expansion of silicon, for example INVAR, an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel, is mounted to an exterior major surface of the integrated circuit package with a high temperature epoxy.

The thickness of the layers of the materials mounted to the exterior major surfaces of the integrated circuit package depends on the resulting thermal balance throughout the package to avoid warping of the integrated circuit package. When the integrated circuit package is cooled after it is cured, it tends to warp due to thermal imbalances in the different materials that make up the layers of the integrated circuit package. This tendency to warp increases as the integrated circuit package is made thinner. Unless warpage is controlled, the molded package will bend unacceptably upon cooling from its bonding temperature to cooler storage and operational temperatures. An unacceptable level of warping may be as little as one mil but certainly includes three mils. This level of warping detracts from the integrity of the package and may induce cracking in the die.

A potential for package bow results from the method of package construction which utilizes stacked layers of different materials, with each material exhibiting a different coefficient of thermal expansion (CTE). Each material layer, upon cooling, seeks its new dimensions according to its CTE, but is restrained by the presence of the other material layers which make up the assembly. The forces produced by these restraining layers, if not minimized and balanced by proper design, materials selection, and construction, can produce undesirable warpage.

A thin, warp resistant layer, such as INVAR, an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel, for example, is mounted to only selected packages within each module, but functions to control warpage of the entire module.

The present invention provides a method of warpage control that minimizes the differential thermal expansion forces and moments between the material layers on either side of a neutral thermodynamic axis in the assembly. The neutral thermodynamic axis is chosen for convenience to be the plane through the center of the lead frame. The total warpage-causing moments on either side of the neutral thermodynamic axis are the sum of the moments associated with each layer, relative to the neutral thermodynamic axis. For a particular layer, the moment, m, is proportional to the following product:

m≡(E)(h)(t)Δ(a)Δ(T)

where m is the moment of the layer; E is the Young's modules of elasticity of the layer material; h is the moment-arm distance of the center of the layer from the neutral thermodynamic axis; t is the layer thickness; Δ(a) is the difference in CTE of the layer and that of the material containing the neutral thermodynamic axis; and β(T) is the temperature difference between assembly bonding temperature and operation, storage, or other temperatures of interest.

The product Δ(a)Δ(T) is the source of forces and moments, the product (E)(t) is the deflection compliance of the layer with the differential force, and h is the lever arm allowing the force to produce a moment with its resulting warpage.

The product in the above equation, for moment, m, is evaluated for each layer on one side of the neutral thermodynamic axis and these values summed. The process is repeated for the layers on the opposite side of the neutral thermodynamic axis and the two sums compared. The package materials and dimensions are then adjusted until the sums are either equal or acceptably close enough in value to assure acceptably low values of warpage. In other words, the vectorial summation of all of the moments of each layer is as close to zero as possible.

An advantage of the present invention is that one can asymmetrically locate elements formed of different materials in the package and thermally balance them. Thus the integrated circuit die does not have to be symmetrically centered in the package to obtain thermal balance throughout the integrated circuit package. Application of the method of the present invention compensates for material and orientation asymmetries in the integrated circuit package to prevent warping.

Other and further objects, features and advantages will be apparent from the following description of the presently preferred embodiment of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.

A better understanding of the present invention can be obtained when the following detailed description is read in conjunction with the following drawings in which:

FIG. 1 is a perspective view of the ultra high-density memory package, comprised of ultra high-density memory modules, of the present invention;

FIG. 2 is a perspective view of an ultra high-density memory module and thermally conductive cap of the present invention;

FIG. 3 illustrates a cross-sectional view of a preferred embodiment of the high-density memory package of the present invention; and

FIG. 4 is a plan view of an internal lead frame having "S" shaped strain relief portions;

FIG. 5 illustrates a cross-sectional view of a further embodiment of the high-density memory package of the present invention having two-sided tape mounted to the die.

FIG. 1 illustrates an ultra high-density memory bank 11 formed of a plurality of ultra high density memory modules 10. Each memory module 10 is formed of a plurality of individual high-density integrated circuit memory packages 20. As shown in FIG. 2, the leads 24 of each high-density memory package 20 project from one end of each package 20 in an in-line configuration.

The memory modules 10 may be electrically connected to a mounting header 12 (FIG. 1) for electrical interconnection to circuit board 16 via electrical conductor platform 14. Platform 14 is omitted in one configuration, whereby electrical connection between mounting header 12 and circuit board 16 is made directly. In other configurations, electrical interconnections between leads 24 of packages 20 of modules 10 may be made directly to circuit board 16.

As illustrated in FIG. 3, each package 20 includes an internal integrated circuit die 26. A substantially planar internal lead frame 30 overlays a portion of die 26 to provide thermal coupling and structural rigidity. In a preferred embodiment, lead frame 30 is alloy 42 (42% nickel, 58% iron). Although less efficient in heat dissipation than other materials such as copper for example, alloy 42 provides the advantage of added rigidity where heat dissipation is adequately controlled through the other heat dissipating members disclosed herein. Where the modules are used in applications having extreme thermal stress, those skilled in the art will recognize that design trade-offs may dictate a preferable lead frame member composed of a copper alloy rather than alloy 42.

As depicted in FIG. 3, connectors from lead frame 30 extend through an edge of casing 32 to form leads 24. Optionally, a substantially planar internal element 34, preferably also composed of alloy 42 (or copper where heat stress is extreme), may be overlaid a substantial portion of die 26 to provide additional rigidity. Element 34 may be a joined extension of lead frame 30, or as depicted in FIG. 3, a separate element mounted to the same major surface of die 26 as internal lead frame 30. In other embodiments, internal lead frame 30 and optional internal element 34 may be mounted to opposite major surfaces of die 26. In a preferred embodiment, protective casing 32 envelopes internal lead frame 30 and optional internal element 34 and the surface area of die 26.

FIG. 4 illustrates a plan view of a substantially planar internal lead frame 30 in accordance with the present invention. FIG. 4 is presented for illustration purposes and is not meant to delimit lead frame configurations useable in accordance with the present invention. Lead frame 30 includes "S" shaped relief portions 22 to provide strain relief for lead frame conductors 17 such that temperature cycling conditions within the protective casing 32 will not cause lead frame conductors 17 to break electrical connection with the terminals (not shown) of die 26 to which conductors 17 are connected. Hatched outline 19 represents the approximate finished size of internal lead frame 30 after it is stamped or cut to form leads 24 (FIG. 3) on the distal ends of lead frame conductors 17. The strain relief portion is preferably formed in each lead frame conductor 17 between said conductor distal end, which includes the lead 24, and the die bond end where the conductor 17 is electrically connected to die 26.

Integrated circuit memory package 20 is preferably thin, and without the preventive measures described herein could warp during fabrication or use due to dissimilar coefficients of thermal expansion in the various layers or component parts which comprise package 20. As illustrated in FIG. 3, to prevent warping while still maintaining a thin profile, a thin, warp-resistant metal layer 36 having a coefficient of thermal expansion less than that of silicon is mounted to a major surface of each integrated circuit package 20. Thin warp-resistant metal layer 36 is mounted to an outer major surface of casing 32. Metal layer 36 is preferably INVAR, an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel.

A substantially planar external thermally conductive element 38 is mounted to and is in thermal contact with an opposite outer major surface of package 20. As depicted in FIG. 3 and FIG. 5, external thermally conductive element 38 is preferably mounted in close contact with die 26 as exposed through casing 32 in contemporary ultra high-density devices such as those offered commercially by the assignee of the present invention. Element 38 is a thin sheet of copper 110 alloy or, alternatively, a laminate composed of alternating Cu/INVAR/Cu layers, where INVAR is an iron-nickel based alloy consisting essentially of about 63% iron and 46% nickel.

In other embodiments, only selected packages 20 within module 10 include a thin, warp-resistant layer 36 mounted to a major exterior surface. In these embodiments, the CTE of the material used for metal layer 36 is selected to thermally balance and make warp-resistant the entire module 10 without requiring a metal layer 36 on each package 20 within the module 10.

The present invention provides a method of warpage control that minimizes the differential thermal expansion forces and moments between the material layers on either side of a neutral thermodynamic axis in the assembly. The neutral thermodynamic axis is chosen for convenience to be the plane through the center of the lead frame. The total warpage-causing moments on either side of the neutral thermodynamic axis are the sum of the moments associated with each layer, relative to the neutral thermodynamic axis. For a particular layer, the moment, m, is proportional to the following product:

m≡(E)(h)(t)Δ(a)Δ(T)

where m is the moment of the layer; E is the Young's modules of elasticity of the layer material; h is the moment-arm distance of the center of the layer from the neutral thermodynamic axis; t is the layer thickness; Δ(a) is the difference in CTE of the layer and that of the material containing the neutral thermodynamic axis; and Δ(T) is the temperature difference between assembly bonding temperature and operation, storage, or other temperatures of interest.

The product Δ(a)Δ(T) is the source of forces and moments, the product (E)(t) is the deflection compliance of the layer with the differential force, and h is the lever arm allowing the force to produce a moment with its resulting warpage.

The product in the above equation, for moment, m, is evaluated for each layer on one side of the neutral thermodynamic axis and these values summed. The process is repeated for the layers on the opposite side of the neutral thermodynamic axis and the two sums compared. The package materials and dimensions are then adjusted until the sums are either equal or acceptably close enough in value to assure acceptably low values of warpage. In other words, the vectorial summation of all of the moments of each layer is as close to zero as possible.

An advantage of the present invention is that one can asymmetrically locate elements formed of different materials in each package 20 and thermally balance them. Thus, integrated circuit die 26 does not have to be symmetrically centered in the package 20 to obtain thermal balance throughout each package 20. Application of the method of the present invention allows compensation for material and orientation asymmetries in each package 20 to prevent warping.

As shown in FIG. 3, an end portion 39 of external thermally conductive element 38 extends outward beyond edge 37 of casing 32. Warp resistant layer 36 is also depicted with an edge portion 41 configured to create a platform area 45 suitable for contact with a heat conduction pipe or cap. When copper is used as lead frame 30 and optional element 34, element 34 may also have an extended edge conformal to the platform 45. Together, end portions 41 and 39 form platform 45, the edge portions being outwardly spring-biased. Element 34 may also have an end portion 50 which extends through edge 37 of casing 32 and may be formed to be a part of platform 45.

A heat conduction cap 18 (FIG. 2) is mounted to platform 45, formed of the contact area of end portions 39 and 41 (FIG. 3). A thermal grease is preferably used to provide a heat transfer conduit from platform area 45 to cap 18. End portions 39 and 41 are spring-biased to provide better mechanical and thermal contact through the thermal grease between platform 45 and cap 18. Cap 18 is provided for additional heat dissipation and is preferably made of metal or other thermally conductive material. For maximum heat dissipation, cap 18 may be cooled by liquid nitrogen, liquid oxygen or other super-cooled gas. Alternatively, cap 18 may also include fins or other form of conventional heat sinks.

As shown in FIG. 3, epoxy layer 44, preferably ABLE FILM or ABLE LOG, is used to mount thin, warp-resistant metal layer 36 to an outer major surface of casing 32. Likewise, a layer of epoxy 44 is used to mount external thermally conductive element 38 to an opposite outer major surface of each package 20. As depicted in FIG. 3, external thermally conductive element 38 is preferably mounted in close contact with die 26 as exposed through casing 32 in contemporary ultra high-density devices such as those offered commercially by the assignee of the present invention. A compliant adhesive, such as phenolic butyral epoxy, may be used to relieve stress caused by dissimilar thermal expansion of the lead frame 30 and die 26.

In other embodiments, as shown in FIG. 5, a two-sided polyimide film 51, such as KAPTON by DuPont, having a thin layer of high temperature epoxy 49 applied to both sides of film 51, is used to mount internal lead frame 30 and/or internal element 34 to die 26. The high temperature adhesive may be epoxy, such as Rogers Corp. R/flex (R) 8970 which is B-staged phenolic butyral epoxy, that may be laminated at a temperature of about 130° C. and cured at a temperature of about 175°C

Referring now to FIG. 2, ultra high-density memory modules 10 are assembled from a plurality of individual packages 20. Packages 20 are vertically oriented and mounted to one another such that a major surface of each is mounted to and is in thermal contact with a major surface of an adjacent package. Each module 10 is assembled so leads 24 of the individual packages 20 are aligned with adjacent corresponding leads of adjacent packages 20, forming a grid array. Preferably, ten individual packages 20 are mounted to one another to form a high-density memory module 10. A thin layer of fracturable adhesive 35 (FIG. 3) is applied to the exterior major surface of the external thermally conductive element 38 and/or the exterior surface of thin, warp-resistant metal layer 36 of each individual package 20 within each high-density memory module 10. The packages 20 are mounted such that the end portion 39 of the external thermally conductive element 38 of one package and the end portion 41 of the thin metal warp-resistant layer 36 of an adjacent package at least partially overlap and are in contact with each other.

Fracturable or reworkable form of adhesive 35 is used to form the modules 10 so a defective package may be easily replaced. Once a defective package is isolated to a certain memory module 10, the memory module 10 is unsoldered from mounting header 12 or from circuit board 16, depending on how the leads are connected. The individual package 20 within the defective module 10 can then be identified. The individual packages 20 on either side of the defective package 20 within the module 10 may then be separated from the defective package by applying lateral pressure to crack the fracturable, or reworkable, adhesive layer 35. Once the defective package 20 has been replaced, a new layer of fracturable adhesive 35 may be applied to the major surfaces of the packages separated, as stated previously, and the module 10 may then be reassembled. The repaired module 10 is then reinserted and reconnected to mounting header 12 or to circuit board 16.

The foregoing disclosure and description of the invention are illustrated and explanatory of the preferred embodiments, and changes in the size, shape, materials and individual components, circuit elements, connections and construction may be made without departing from the spirit of the invention.

Burns, Carmen D.

Patent Priority Assignee Title
5781791, Apr 16 1996 The United States of America as represented by the Secretary of the Army Digital microelectronic circuit package using buffer dies and programmable device or memory dies
5828125, Mar 29 1993 OVID DATA CO LLC Ultra-high density warp-resistant memory module
6089920, May 04 1998 Micron Technology, Inc. Modular die sockets with flexible interconnects for packaging bare semiconductor die
6194247, Mar 29 1993 OVID DATA CO LLC Warp-resistent ultra-thin integrated circuit package fabrication method
6265773, Dec 31 1997 Round Rock Research, LLC Vertically mountable and alignable semiconductor device, assembly, and methods
6319065, May 04 1998 Micron Technology, Inc. Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
6329705, May 20 1998 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
6331448, May 20 1998 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes
6342731, Dec 31 1997 Round Rock Research, LLC Vertically mountable semiconductor device, assembly, and methods
6453550, May 04 1998 Micron Technology, Inc. Method for forming modular sockets using flexible interconnects and resulting structures
6462408, Mar 27 2001 TAMIRAS PER PTE LTD , LLC Contact member stacking system and method
6478627, May 04 1998 Micron Technology, Inc. Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
6500697, May 20 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes
6512290, Dec 31 1997 Round Rock Research, LLC Vertically mountable and alignable semiconductor device, assembly, and methods
6531764, Dec 31 1997 Round Rock Research, LLC Vertically mountable semiconductor device, assembly, and methods
6572387, Sep 24 1999 TAMIRAS PER PTE LTD , LLC Flexible circuit connector for stacked chip module
6576992, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Chip scale stacking system and method
6608763, Sep 15 2000 M-RED INC Stacking system and method
6612872, May 04 1998 Micron Technology, Inc. Apparatus for forming modular sockets using flexible interconnects and resulting structures
6634098, Dec 31 1997 Round Rock Research, LLC Methods for assembling, modifying and manufacturing a vertical surface mount package
6703260, May 20 1998 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and methods of designing and fabricating such leadframes
6709895, Oct 31 1996 Tessera, Inc. Packaged microelectronic elements with enhanced thermal conduction
6731011, Feb 19 2002 SanDisk Technologies LLC Memory module having interconnected and stacked integrated circuits
6751859, May 04 1998 Micron Technology, Inc. Method for forming modular sockets using flexible interconnects and resulting structures
6758696, May 04 1998 Micron Technology, Inc. Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
6760970, May 04 1998 Micron Technology, Inc. Method for forming modular sockets using flexible interconnects and resulting structures
6806120, Mar 27 2001 TAMIRAS PER PTE LTD , LLC Contact member stacking system and method
6914324, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Memory expansion and chip scale stacking system and method
6919626, Dec 11 1992 OVID DATA CO LLC High density integrated circuit module
6940729, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Integrated circuit stacking system and method
6955945, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Memory expansion and chip scale stacking system and method
6956284, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Integrated circuit stacking system and method
6963128, Dec 31 1997 Round Rock Research, LLC Vertically mountable and alignable semiconductor device assembly
7005730, Feb 19 2002 SanDisk Technologies LLC Memory module having interconnected and stacked integrated circuits
7026708, Oct 26 2001 OVID DATA CO LLC Low profile chip scale stacking system and method
7033861, May 18 2005 TAMIRAS PER PTE LTD , LLC Stacked module systems and method
7040930, May 04 1998 Micron Technology, Inc. Modular sockets using flexible interconnects
7053478, Oct 29 2001 TAMIRAS PER PTE LTD , LLC Pitch change and chip scale stacking system
7066741, Sep 24 1999 TAMIRAS PER PTE LTD , LLC Flexible circuit connector for stacked chip module
7082681, Dec 31 1997 Round Rock Research, LLC Methods for modifying a vertical surface mount package
7094108, May 04 1998 Micron Technology, Inc. Apparatus for forming modular sockets using flexible interconnects and resulting structures
7094632, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Low profile chip scale stacking system and method
7153164, May 04 1998 Micron Technology, Inc. Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
7180167, Oct 26 2001 OVID DATA CO LLC Low profile stacking system and method
7192311, May 04 1998 Micron Technology, Inc. Apparatus for forming modular sockets using flexible interconnects and resulting structures
7193310, Dec 14 2001 TAMIRAS PER PTE LTD , LLC Stacking system and method
7202555, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Pitch change and chip scale stacking system and method
7256484, Oct 26 2001 ENTORIAN TECHNOLOGIES L P Memory expansion and chip scale stacking system and method
7289327, Feb 27 2006 ENTORIAN TECHNOLOGIES L P Active cooling methods and apparatus for modules
7304382, Jan 11 2006 TAMIRAS PER PTE LTD , LLC Managed memory component
7309914, Jan 20 2005 TAMIRAS PER PTE LTD , LLC Inverted CSP stacking system and method
7324352, Sep 03 2004 ENTORIAN TECHNOLOGIES L P High capacity thin module system and method
7335975, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Integrated circuit stacking system and method
7367845, May 04 1998 Micron Technology, Inc. Modular sockets using flexible interconnects
7371609, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Stacked module systems and methods
7423885, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Die module system
7432599, Feb 19 2002 SanDisk Technologies LLC Memory module having interconnected and stacked integrated circuits
7443023, Sep 03 2004 TAMIRAS PER PTE LTD , LLC High capacity thin module system
7446410, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Circuit module with thermal casing systems
7459784, Sep 03 2004 TAMIRAS PER PTE LTD , LLC High capacity thin module system
7468553, Oct 20 2006 TAMIRAS PER PTE LTD , LLC Stackable micropackages and stacked modules
7468893, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Thin module system and method
7480152, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Thin module system and method
7485951, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Modularized die stacking system and method
7508058, Jan 11 2006 TAMIRAS PER PTE LTD , LLC Stacked integrated circuit module
7508069, Jan 11 2006 TAMIRAS PER PTE LTD , LLC Managed memory component
7511968, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Buffered thin module system and method
7511969, Feb 02 2006 TAMIRAS PER PTE LTD , LLC Composite core circuit module system and method
7522421, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Split core circuit module
7522425, Sep 03 2004 TAMIRAS PER PTE LTD , LLC High capacity thin module system and method
7542297, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Optimized mounting area circuit module system and method
7542304, Sep 15 2003 TAMIRAS PER PTE LTD , LLC Memory expansion and integrated circuit stacking system and method
7569418, Dec 31 1997 Round Rock Research, LLC Methods for securing packaged semiconductor devices to carrier substrates
7576995, Nov 04 2005 TAMIRAS PER PTE LTD , LLC Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
7579687, Jan 13 2006 TAMIRAS PER PTE LTD , LLC Circuit module turbulence enhancement systems and methods
7586758, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Integrated circuit stacking system
7595550, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Flex-based circuit module
7602613, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Thin module system and method
7605454, Jan 11 2006 TAMIRAS PER PTE LTD , LLC Memory card and method for devising
7606040, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Memory module system and method
7606042, Sep 03 2004 TAMIRAS PER PTE LTD , LLC High capacity thin module system and method
7606048, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Integrated circuit stacking system
7606049, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Module thermal management system and method
7606050, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Compact module system and method
7608920, Jan 11 2006 TAMIRAS PER PTE LTD , LLC Memory card and method for devising
7616452, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Flex circuit constructions for high capacity circuit module systems and methods
7626259, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Heat sink for a high capacity thin module system
7656678, Oct 26 2001 TAMIRAS PER PTE LTD , LLC Stacked module systems
7737549, Nov 18 2005 OVID DATA CO LLC Circuit module with thermal casing systems
7760513, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Modified core for circuit module system and method
7768796, Sep 03 2004 TAMIRAS PER PTE LTD , LLC Die module system
7957134, Apr 10 2007 Hewlett Packard Enterprise Development LP System and method having evaporative cooling for memory
Patent Priority Assignee Title
3436604,
3614546,
3713893,
3739462,
4030080, Jan 07 1974 SIEMENS INDUSTRIAL AUTOMATION, INC A DELAWARE CORPORATION Variable module memory
4103318, May 06 1977 LORAL AEROSPACE CORP , A CORP OF DE Electronic multichip module
4158745, Oct 27 1977 AMP Incorporated Lead frame having integral terminal tabs
4241493, Dec 22 1978 AMOCO ENRON SOLAR Method of fabricating solar cell modules
4288841, Sep 20 1979 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
4321418, May 08 1979 SAINT GOBAIN VITRAGE, 63, RUE DE VILLIERS, F92209 NEUILLY-SUR-SEINE, FRANCE A FRENCH COMPANY Process for manufacture of solar photocell panels and panels obtained thereby
4437235, Dec 29 1980 Honeywell Information Systems Inc. Integrated circuit package
4451973, Apr 28 1981 MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
4521828, Dec 23 1982 AT & T TECHNOLOGIES, INC , Component module for piggyback mounting on a circuit package having dual-in-line leads
4525921, Sep 16 1980 Irvine Sensors Corporation High-density electronic processing package-structure and fabrication
4530152, Apr 01 1982 Compagnie Industrielle des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
4630172, Mar 09 1983 PCI 1989 PTE LTD A SINGAPORE CORPORATION Semiconductor chip carrier package with a heat sink
4633573, Oct 12 1982 AEGIS, INC , A CORP OF MA Microcircuit package and sealing method
4680617, May 23 1984 INOVENT, LTD Encapsulated electronic circuit device, and method and apparatus for making same
4684975, Dec 16 1985 National Semiconductor Corporation Molded semiconductor package having improved heat dissipation
4706166, Apr 25 1986 APROLASE DEVELOPMENT CO , LLC High-density electronic modules--process and product
4722060, Mar 22 1984 SGS-Thomson Microelectronics, Inc Integrated-circuit leadframe adapted for a simultaneous bonding operation
4733461, Dec 28 1984 MICRO CO , LTD , 1-15, KITA-SHINJUKU, 1-CHOME, SHINJUKU-KU, TOKYO 160 JAPAN Method of stacking printed circuit boards
4763188, Aug 08 1986 Packaging system for multiple semiconductor devices
4764846, Jan 05 1987 Irvine Sensors Corporation High density electronic package comprising stacked sub-modules
4771366, Jul 06 1987 International Business Machines Corporation Ceramic card assembly having enhanced power distribution and cooling
4796078, Jun 15 1987 International Business Machines Corporation Peripheral/area wire bonding technique
4821148, Jun 14 1985 Hitachi, Ltd. Resin packaged semiconductor device having a protective layer made of a metal-organic matter compound
4823234, Aug 16 1985 Dai-Ichi Seiko Co., Ltd. Semiconductor device and its manufacture
4829403, Jan 20 1987 Packaging arrangement for energy dissipating devices
4833568, Jan 29 1988 TROVE TECHNOLOGY INCORPORATED, 7752 STEFFENSEN DRIVE, SALT LAKE CITY, UT 84121 A CORP OF UT Three-dimensional circuit component assembly and method corresponding thereto
4839717, Dec 19 1986 National Semiconductor Corporation Ceramic package for high frequency semiconductor devices
4855868, Jan 20 1987 Preformed packaging arrangement for energy dissipating devices
4862245, Apr 18 1985 International Business Machines Corporation Package semiconductor chip
4862249, Apr 17 1987 XOC Devices, Inc. Packaging system for stacking integrated circuits
4878106, Dec 02 1986 Anton Piller GmbH & Co. KG Semiconductor circuit packages for use in high power applications and method of making the same
4884237, Mar 28 1984 International Business Machines Corporation Stacked double density memory module using industry standard memory chips
4891789, Mar 03 1988 Bull HN Information Systems, Inc.; HONEYWELL BULL INC , A CORP OF DE Surface mounted multilayer memory printed circuit board
4948645, Aug 01 1989 Rogers Corporation Tape automated bonding and method of making the same
4953005, Apr 17 1987 XOC DEVICES, INC Packaging system for stacking integrated circuits
4953060, May 05 1989 NCR Corporation Stackable integrated circuit chip package with improved heat removal
4983533, Oct 28 1987 APROLASE DEVELOPMENT CO , LLC High-density electronic modules - process and product
4994411, Mar 10 1988 Hitachi, Ltd. Process of producing semiconductor device
4997517, Jan 09 1990 Olin Corporation Multi-metal layer interconnect tape for tape automated bonding
5014113, Dec 27 1989 Motorola, Inc. Multiple layer lead frame
5016138, Oct 27 1987 Three dimensional integrated circuit package
5041015, Mar 30 1990 CAL FLEX, INC Electrical jumper assembly
5049527, Jun 25 1985 AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD ; AVAGO TECHNOLOGIES GENERAL IP PTE LTD ; AVAGO TECHNOLOGIES ECBU IP SINGAPORE PTE LTD Optical isolator
5057906, May 22 1989 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device
5065277, Jul 13 1990 Sun Microsystems, Inc. Three dimensional packaging arrangement for computer systems and the like
5086018, May 02 1991 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
5089876, Jul 19 1989 Elpida Memory, Inc Semiconductor IC device containing a conductive plate
5099393, Mar 25 1991 International Business Machines Corporation Electronic package for high density applications
5104820, Jul 07 1989 APROLASE DEVELOPMENT CO , LLC Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
5108553, Apr 04 1989 OLIN CORPORATION, G-tab manufacturing process and the product produced thereby
5134463, Oct 23 1989 Mitsubishi Denki Kabushiki Kaisha Stress relief layer providing high thermal conduction for a semiconductor device
5138430, Jun 06 1991 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
5138434, Jan 22 1991 Micron Technology, Inc. Packaging for semiconductor logic devices
5139969, May 30 1990 Mitsubishi Denki Kabushiki Kaisha Method of making resin molded semiconductor device
5147822, Aug 26 1988 Semiconductor Energy Laboratory Co., Ltd. Plasma processing method for improving a package of a semiconductor device
5151559, May 02 1991 International Business Machines Corporation Planarized thin film surface covered wire bonded semiconductor package
5155068, Aug 31 1989 Sharp Kabushiki Kaisha Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
5157478, Apr 19 1989 Mitsubishi Denki Kabushiki Kaisha Tape automated bonding packaged semiconductor device incorporating a heat sink
5214845, May 11 1992 Micron Technology, Inc.; MICRON TECHNOLOGY, INC , A DE CORP Method for producing high speed integrated circuits
5216283, May 03 1990 Freescale Semiconductor, Inc Semiconductor device having an insertable heat sink and method for mounting the same
5223739, Sep 14 1989 Kabushiki Kaisha Toshiba Plastic molded semiconductor device having waterproof cap
5235672, Feb 06 1991 APROLASE DEVELOPMENT CO , LLC Hardware for electronic neural network
5279991, May 15 1992 APROLASE DEVELOPMENT CO , LLC Method for fabricating stacks of IC chips by segmenting a larger stack
5313097, Nov 16 1992 International Business Machines, Corp. High density memory module
5347428, Dec 03 1992 TALON RESEARCH, LLC Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
5367766, Aug 01 1990 ENTORIAN GP LLC; ENTORIAN TECHNOLOGIES INC Ultra high density integrated circuit packages method
JP31166,
JP53959,
JP96756A,
JP112348,
JP125440,
JP153849,
JP163652A,
JP180150A,
JP207061,
//////
Executed onAssignorAssigneeConveyanceFrameReelDoc
Jun 07 1995Staktek Corporation(assignment on the face of the patent)
Jun 07 1995BURNS, CARMEN D Staktek CorporationASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0077360192 pdf
Sep 27 2000Staktek CorporationSTAKTEK GROUP L P CORRECTIVE ASSIGNMENT TO CORRECT THE STATE OF INCORPORATION WITHIN THE ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 011177, FRAME 0921 ASSIGNORS HEREBY CONFIRMS THE STATE OF INCORPORATION IS TEXAS 0309620142 pdf
Sep 27 2000Staktek CorporationSTAKTEK GROUP L P ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0111770921 pdf
Aug 19 2003STAKTEK GROUP L P COMERICA BANK, AS AGENTSECURITY AGREEMENT0145460001 pdf
Feb 19 2004COMERICA BANK, AS AGENTSTAKTEK GROUP L P NOW KNOWN AS ENTORIAN TECHNOLOGIES L P RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0239850954 pdf
Date Maintenance Fee Events
Aug 16 2000ASPN: Payor Number Assigned.
Dec 29 2000M183: Payment of Maintenance Fee, 4th Year, Large Entity.
Jan 10 2001LSM2: Pat Hldr no Longer Claims Small Ent Stat as Small Business.
Jan 19 2005REM: Maintenance Fee Reminder Mailed.
Jan 26 2005REM: Maintenance Fee Reminder Mailed.
Jul 01 2005EXP: Patent Expired for Failure to Pay Maintenance Fees.


Date Maintenance Schedule
Jul 01 20004 years fee payment window open
Jan 01 20016 months grace period start (w surcharge)
Jul 01 2001patent expiry (for year 4)
Jul 01 20032 years to revive unintentionally abandoned end. (for year 4)
Jul 01 20048 years fee payment window open
Jan 01 20056 months grace period start (w surcharge)
Jul 01 2005patent expiry (for year 8)
Jul 01 20072 years to revive unintentionally abandoned end. (for year 8)
Jul 01 200812 years fee payment window open
Jan 01 20096 months grace period start (w surcharge)
Jul 01 2009patent expiry (for year 12)
Jul 01 20112 years to revive unintentionally abandoned end. (for year 12)