Electric circuit and method for forming the same

Abstract

An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

Description

This is a divisional application of Ser. No. 08/053,227, filed Apr. 28, 1993 now U.S. Pat. No. 5,576,225.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to an electric circuit and a method for forming the same.

2. Description of the Prior Art

As from '80s, gate electrodes of MOS type semiconductor integrated circuits have been formed mainly from silicon. This is because of the small differential electron energy between the silicon gate and the underlying semiconductor channel region and the great heat resistance of silicon which make it possible to utilize the self-aligning fabrication technique for forming source/drain regions. On the contrary, the self-aligning fabrication technique is not available in the case utilizing aluminum gate electrodes which had been broadly employed prior to the silicon gate. This is because aluminum does not have a sufficient resistance to heat. Aluminum gates have been considered out of date for this reason in spite of the low electric resistance thereof.

Recently, however, it has been reported to utilize the self-aligning fabrication technique for forming source/drain regions also in the case of aluminum gates by employing laser annealing techniques. It has also been proposed that interlayer insulation from the gate electrodes can be sufficiently performed by forming anodic oxide films on the gate electrodes together with wirings formed from the same material at the same time. The gate electrodes and the wirings are generally referred to for both simply as gate electrode wirings hereinbelow because they can not always be exactly distinguished from each other. The aluminum oxide films have a sufficient corrosion resistance and a sufficient pressure resistance and are utilized to form the so-called offset structure between the gate and the source and drain regions as described in Japanese Patent Application No. Hei 3-340336, Japanese Patent Application No. Hei 4-30220 or Japanese Patent Application No. Hei 4-34194 of the same applicants.

Several problems, however, have been pointed out in the technique utilizing anodizing gate electrode wirings. For example, even if the external surfaces of the gate electrode wirings are coated with aluminum oxide films, the adhesivity between them fluctuates depending on the location of the surfaces so that the aluminum oxide films sometimes partially comes off from the underlying gate electrode wirings. In addition to this, the anodic aluminum oxide film are formed with substantially disparity of the thickness depending on the location on the gate electrodes. Furthermore, since the aluminum oxide films have an extremely strong resistance against corrosion, it is difficult to remove them by usual wet etching or dry etching so that other materials such as silicon oxide existing near the aluminum oxide films tend to be etched during the removal of the aluminum oxide films. Furthermore, since the gate electrode wirings are integrally connected to each other during the anodizing in order to treat the gate electrodes as an anode, unnecessary portions connecting the individual gate electrodes must be removed after the anodizing to separate them. The unnecessary portions, however, are also coated with aluminum oxide and therefore it is very difficult to remove them. Furthermore, it is also difficult to open necessary contact holes through the corrosion-proof aluminum oxide films to access the underlying gate electrode wirings so that neighboring circuit elements are also corroded.

On the other hand, it is proposed to partially remove the gate electrode wirings coated with aluminum oxide and to open contact holes by exposing necessary portions to high energy laser illumination as described in Japanese Patent Application No. Hei 3-348130. The underlying gate electrode wirings are damaged by the high energy laser light so that it seems impossible to form contact holes by this method.

BRIEF SUMMARY OF THE INVENTION

As pointed out in the above, there are following shortcomings in the technique utilizing gate electrodes coated with anodic oxide films.

1) Disparity of adhesivity between the gate electrodes and the covering anodic oxide film resulting in peeling off.

2) Difficulty in removing unnecessary portions of the gate electrode wirings coated with anodic oxide film and forming contact holes through the anodic oxide films.

3) Disparity of the thickness of the anodic films.

It has been discovered through research conducted by the inventors that the above shortcomings 1) and 3) result mainly from variation of the potential level over the external surfaces of the gate electrode wirings and therefore from the variation of the electric current passing therethrough. The oxidation speed of the aluminum surface during anodizing is dictated by the potential level at the respective location in question. Namely, the difference in the anodizing speed is considered to reflect the difference in potential level. As a result, the anodic oxide films grow on narrow patterns at speeds faster than in wide patterns and tend to peel off due to the difference in adhesivity.

It is therefore an object of the present invention to provide a method of manufacturing improved electronic devices having aluminum gate electrodes.

It is another object of the present invention to provide a method of manufacturing improved electronic devices by the use of anodic oxidation.

It is a further object of the present invention to provide a method of manufacturing improved electronic devices in which patterning of anodized aluminum wirings can be easily carried out.

It is a still further object of the present invention to provide a method of manufacturing improved electronic devices suitable for forming very fine structures thereof.

It is a still further object of the present invention to provide an improved electronic devices having anodic oxidized aluminum gate electrodes.

Additional objects, advantages and novel features of the present invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the present invention. The object and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve the foregoing and other object, and in accordance with the present invention, as embodied and broadly described herein, a method for manufacturing semiconductor devices comprising the steps of forming an aluminum pattern which is electrically undevided on a substrate, partially covering the aluminum pattern with a resist film, anodizing an external surface of the aluminum pattern which is not covered with the resist film, and removing the resist film. Particularly, the aluminum pattern is partially covered with aluminum oxide by the anodizing and, after the removing step, provided with an exposed surface through which the underlying aluminum pattern can be removed or electrically accessed.

In the case of forming insulated gate field effect transistors, a film comprising a material selected from the group consisting of aluminum, tantalum, aluminum having added thereto silicon, copper, tantalum, scandium and palladium, an alloy thereof and a multi-layer thereof is formed on a substrate, and said film is patterned to form gate electrodes, common connecting lines and higher level common connecting lines. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form aluminum oxide covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

In accordance with an aspect of the present invention, a plurality of gate electrodes are divided into a plurality of group. The gate electrodes belonging to each group are connected to a corresponding one of a plurality of common connecting lines having a width larger than that of the gate electrodes. Width of the common connecting lines is increased to be larger than width of the gate electrodes in order to reduce resistance of the first wiring. The common connecting lines are connected, in turn, to a higher level common connecting line. Namely, the whole aluminum pattern is designed in a hierarchy fashion. An electric circuit in accordance with the present invention comprises such a gate electrode provided on a substrate, such a common connecting line as a first wiring provided on the substrate, and such a higher level common connecting line as a second wiring provided on the substrate. The second wiring has a width larger than that of the first wiring. Width of the second wiring is increased to be larger than width of the first wiring in order to reduce resistance of the second wiring. The gate electrode, the first wiring and the second wiring comprise the same material selected from the group consisting of aluminum, tantalum, aluminum having added thereto silicon, copper, tantalum, scandium and palladium, an alloy thereof and a multi-layer thereof. A channel is formed on the substrate and adjacent to the gate electrode with a gate insulating film therebetween. A typical example can be seen from FIG. 1(A). In the figure, a number of gate electrodes 6 are connected to a branch line 5 having a wider width while a number of branch lines 5 are connected to a trunk line having a furthermore wider width. By this fashion, the thicknesses and the degrees of adhesivity of anodic oxide films coated on the gate electrodes at the tips of the hierarchy system are equal to each other.

The aluminum pattern including the gate electrodes can be etched by a dry etching technique such as laser etching to improve the yield since the aluminum portions to be etched are not covered by the corrosion-proof aluminum oxide film. Because of this, very fine geometrical structure can be fabricated. Prior to the present invention, aluminum oxide must be removed by wet etching which is capable of removing aluminum oxide but not suitable for fabricating very fine structures and so that the integration density can not be improved so high.

Ratio (width of the first wiring)/(width of the gate wiring) is preferably 2 to 10. And ratio (width of the second wiring)/(width of the first wiring) is 2 to 10.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of the invention and, together with the description, serve to explain the principles of the invention.

FIGS. 1(A) to 1(D) are plan views showing a method of manufacturing complementary thin film insulated gate field effect transistors in accordance with a first embodiment of the present invention.

FIGS. 2(A) to 2(D) are cross sectional views showing a method of manufacturing complementary thin film insulated gate field effect transistors in accordance with the first embodiment of the present invention in a conceptual correspondence with FIGS. 1(A) to 1(D).

FIGS. 3(A) to 3(D) are cross sectional views showing a method of manufacturing complementary thin film insulated gate field effect transistor in accordance with a second embodiment of the present invention.

FIG. 4(A) is a graphical views showing the V_G -I_D characteristics of a thin film insulated gate field effect transistor manufactured in accordance with the first embodiment of the present invention.

FIG. 4(B) is a graphical views showing the V_G -I_D characteristics of a thin film insulated gate field effect transistor manufactured in accordance with the second embodiment of the present invention.

FIG. 5 is a graphical view showing the relationship between the pressure of an oxygen plasma atmosphere as an etchant gas and the etching rate of an organic coating made of Photoneece with a thickness of 2.3 micrometers in the oxygen plasma.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIGS. 1(A) to 1(D) and FIGS. 2(A) to 2(D), a method of manufacturing complementary thin film insulated gate field effect transistors in accordance with a first embodiment of the present invention will be explained. FIGS. 1(A) to 1(D) and FIGS. 2(A) to 2(D) are plotted conceptually in a correspondence but not in an exactly geometrical correspondence for convenience of illustration and explanation.

A glass plate is used as a substrate 1. The glass plate is, for example, the Corning 7059 glass plate manufactured by Corning Corp. A silicon oxide film 2 is formed on the substrate to a thickness of 100 nm by sputtering. An amorphous semiconductor film is deposited on the silicon oxide film 2 to a thickness of 150 nm by plasma CVD. The semiconductor film is then recrystallized by thermal annealing at 600°C for 60 hours and patterned into a plurality of semiconductor islands 3 by photolithography and reactive ion etching. A silicon oxide film 4 is deposited to a thickness of 115 nm by sputtering in oxygen with a target of silicon oxide to form gate insulating films. An aluminum film is formed on the silicon oxide film 4 to a thickness of 500 nm by electron beam evaporation and patterned by etching, e.g. wet etching with a mixed acid etchant prepared by adding a 5% nitric acid to phosphoric acid in order to form gate electrodes 6, leader lines 5 and trunk lines 13. The gate electrodes 6, the leader lines 5 and the trunk lines 13 are formed to electrically connected to each other as illustrated in FIG. 1(A). The etching ratio is, for example, about 225 nm/min. The width of the feeder lines 5 is 4 micrometers. The width of the trunk lines 13 is 10 micrometers. The channels formed just under the gate electrodes 6 are 2 micrometers long and 12 micrometers wide. By the above procedure, the indispensable outlines of the transistors are formed on the substrate as illustrated in FIGS. 1(A) and 2(A). An organic coating is selectively formed on the gate electrode or the wiring connected therewith (the leader lines and trunk lines) provided on the substrate.

The gate electrodes 6 or the wiring connected therewith are then anodic oxidized by supplying current thereto in an electrolyte with the leader lines 5 and the trunk lines 13 being partially coated with organic coating films in order that the aluminum films to be removed or providing contacts are not covered with corrosion-proof oxide films. A portion or at least a portion of the organic coating is etched to expose the gate electrode or the wiring connected therewith in said portion. The organic coating films are preferably formed from an organic material having a heat resistance at a temperature of 270°C or higher. For this purpose, polyimide based organic materials are appropriate. A typical example of such polyimide based material is Photoneece (UR3800) which is a photosensitive organic resin manufactured by Tore Industries Company. This resin can be easily patterned. The organic coating of this kind can be easily removed (etched) by a suitable solvent such as hydrazine, or by plasma generated in an oxygen or other oxidizing gas atmospheres, e.g. nitrogen dioxide or ozone. On the other hand, the organic coating of this kind can resist against the anodizing environment.

FIG. 5 illustrates the relationship between the pressure of an oxygen plasma atmosphere and the etching rate of an organic coating made of Photoneece with a thickness of 2.3 micrometers. The partial pressure of oxygen is 100%. The plasma is generated by applying RF electric energy between a pair of flat plates arranged in parallel at room temperature to carry out etching (ashing) therein. Oxygen is continuously supplied to the etching space at 2.3 SCCM. As understood from the figure, the etching rate is in proportion to the pressure of the oxygen plasma. Although not shown in the figure, it was found in accordance with experiments that the etching rate was increased by elevating the temperature during ashing with a linear proportional relationship therebetween in a range of from room temperature to 300°C Accordingly, it has been confirmed that the etching performance can be improved by increasing the partial pressure of the oxidizing gas.

Namely, Photoneece (UR3800) manufactured by Tore Industries Company is coated by spin coating on the substrate 1 over the gate electrodes 6, the feader lines 5 and the trunk lines 13. The rotation speed is 2500 rpm. The organic film is dried by baking at 80°C for an hours in nitrogen. After the baking, the coating film is then partially removed by patterning in order to leave only the film 7 covering the feader lines 5 and the trunk lines 13 as illustrated in FIG. 1(B). The coating film 7 is baked again at 300°C for 0.5 to 2 hours in order to make it a polyimide film. The external surfaces of the gate electrodes 6, i.e. the upper and side surfaces thereof are then anodic oxidized to form aluminum oxide films covering them. The anodizing is carried out by dipping the substrate with the gate electrodes as an anode in a solution together with a platinum plate as a cathod and passing a current through the gate electrodes 6, the feader lines 5 and the trunk lines 13. The solution is prepared by neutralizing an ethylene glycol solution of 3% tartaric acid with a 5% ammonia water added in order that the, pH falls in 7.0±0.2. The temperature of the solution is maintained during the anodizing at 25°±2°C

The current is passed through the gate electrodes 6, the feader lines 5 and the trunk lines 13 during the anodizing in the following manner. First, the voltage between the anode and the cathod is adjusted in order to pass a current at 0.1 to 0.5 mA/cm², for example, 0.5 mA/cm². The voltage is gradually increased in order to maintain the current density. When the voltage reaches to 250 V, the anodizing is continued with the voltage being kept at 250 V whereas the current density is gradually decreased. When the current density is decreased to 0.005 mA/cm², the substrate is removed from the solution and placed in a plasma chamber in which ashing of the substrate is carried out to remove the Photoneece film 7. The pressure in the plasma chamber is 0.2 to 2.0 Torr. The RF power is 0.1 to 0.3 W/cm³. The plasma formed in the chamber during ashing is an oxygen plasma. The etching ratio by the, ashing is improved by heating the substrate at 90° to 300°C As a result, the aluminum oxide films 8 are formed to a thickness of 320 nm as illustrated in FIGS. 1(B) and 2(B).

Next, source and drain regions are formed within the semiconductor islands 3 to form n-channel and p-channel regions therebetween by ion implantation in accordance with the known CMOS manufacturing technique. Numerals 9a and 9b in FIG. 1(C) designate p-channel and n-channel transistors respectively. Namely, phosphorous ions are implanted into the semiconductor island for the p-channel transistor 9a with an acceleration voltage of 70 to 110 KeV while the gate electrode 8 and the aluminum oxide film 8 cover the middle portions of the semiconductor islands to be the channel regions. The concentration of phosphorous ions is finally 1 to 5×10¹3 cm-2. Boron fluoride ions (BF₃+) are implanted in the same procedure into the semiconductor island for the n-channel transistors 9b. In the light of the aluminum oxide films 8, the source and drain regions 9 are formed a certain distance apart from the edge of the gate electrodes in the so-called offset structure as illustrated in FIG. 2(C). The offset distance is considered to be about 300 nm corresponding to the thickness of the aluminum oxide film 8.

Since the crystallinity of the source and drain regions 9 is substantially damaged by the ion implantation so as to be substantially amorphous, laser annealing is performed in order to recrystallize the source and drain regions. The laser annealing is carried out by irradiating the semiconductor with 50 shots of a laser pulse emitted from a KrF excimer laser. The energy density of the laser pulse is, for example, 350 mJ/cm². The laser can be replaced in this case by a halogen lamp to obtain the same performance. After the annealing, the leader lines 5 and the trunk lines 13 are selectively removed in order to leave only part 5a of the leader lines 5 as illustrated in FIG. 1(C). A plurality of CMOS gate array are then formed. The gate electrodes can be accessed through the part 5a without difficulties.

The structure is then coated with a silicon oxide interlayer film 10 deposited by sputtering. Contact holes 11a and 11b are opened through the silicon oxide films 4 and 10 by a known photolithography technique to expose the source and drain regions 9. Appropriate contact holes 12 may be also opened through the silicon oxide films 4 and 10 to expose the wiring 5a. These contact holes may be formed at the same time or separately in accordance with appropriate procedures necessary for the method. Finally, necessary wirings are formed from a metallic film by depositing and patterning an aluminum or chromium film.

Referring now to FIGS. 3(A) to 3(D), a method of manufacturing complementary thin film insulated gate field effect transistors in accordance with a second embodiment of the present invention will be explained. The plan views of FIGS. 3(A) to 3(D) are in a conceptual correspondence with FIGS. 1(A) to 1(D) in the same manner as FIGS. 2(A) to 2(D).

A glass plate is used as a substrate 21. The glass plate is, for example, the Corning 7059 glass plate manufactured by Corning Corp. A silicon oxide film 22 is formed on the substrate to a thickness of 100 nm by sputtering. An amorphous semiconductor film is deposited on the silicon oxide film 22 to a thickness of 50 nm by low pressure CVD. The semiconductor film is then recrystallized by laser annealing. The laser annealing is carried out by irradiating the semiconductor with pulsed light emitted from a KrF excimer laser. The energy density of the laser pulse is, for example, 150 to 350 mJ/cm², preferably 250 to 300 mJ/cm². The semiconductor film is then patterned into a plurality of semiconductor film islands 23 provided on the substrate by photolithography and reactive ion etching. A silicon oxide film 24 is deposited on the substrate 21 over the semiconductor film islands 23 to a thickness of 115 nm by sputtering in oxygen with a target of silicon oxide to form gate insulating films. An aluminum film is formed on the silicon oxide film 24 to a thickness of 500 nm by electron beam evaporation and patterned by etching with a mixed acid prepared by adding a 5% nitric acid to phosphoric acid in order to form gate electrodes 28, leader lines and trunk lines, i.e. the gate electrode wirings in the same manner as in the first embodiment. The etching ratio is, for example, about 225 nm/min. The channels formed just under the gate electrodes 28 are 2 micrometers long and 12 micrometers wide. By the above procedure, the indispensible outlines of the transistors are formed on the substrate as illustrated.

A photosensitive organic resin is coated by spin coating on the substrate 21, over the gate electrode wirings. The photosensitive organic resin is, for example, Photoneece (UR3800) manufactured by Tore Industries Company. The rotation speed is 2500 rpm. The coating film is partially removed by patterning in order to leave only the film 27 covering the wirings 25 as illustrated in FIG. 3(B). The external exposed surfaces of the gate electrodes 28, i.e. the upper and side surfaces thereof are then anodic oxidized to form aluminum oxide films covering them. The anodizing is carried out by dipping the substrate with the gate electrodes as an anode in a solution together with a platinum plate as a cathode and passing a current through the gate electrodes 26. The solution is prepared by neutralizing an ethylene glycol solution of 3% tartaric acid with a 5% ammonia water added in order that the pH falls in 7.0±0.2. The temperature of the solution is maintained during the anodizing at 25°±2°C

The current is passed through the gate electrodes 26 during the anodizing in the following manner. First, the voltage between the anode and the cathode is adjusted in order to pass a current at 0.1 to 0.5 mA/cm² for example 0.5 mA/cm². The voltage is gradually increased in order to maintain the current density. When the voltage reaches to 250 V, the anodizing is continued with the voltage being kept at 250 V whereas the current density is gradually decreased. When the current density is decreased to 0.005 mA/cm² the anodizing is finished. As a result, the aluminum oxide films 28 are formed to a thickness of 320 nm as illustrated in FIGS. 1(B) and 2(B).

Next, source and drain regions are formed on the substrate within the semiconductor film islands 23 to form n-channel and p-channel regions therebetween by ion implantation in accordance with the known CMOS manufacturing technique. P-channel and n-channel transistors are formed in the same manner as in the first embodiment. Namely, phosphorous ions as impurities are introduced into the semiconductor film island for the p-channel transistor with an acceleration voltage of 70 to 110 KeV while the gate electrode 26 and the aluminum oxide film 28 cover the middle portions of the semiconductor film islands to be the channel regions. The concentration of phosphorous ions is finally 1 to 5×10¹3 cm-2. Boron fluoride ions (BF₃+) are introduced in the same procedure into the semiconductor film island for the n-channel transistors. In the light of the aluminum oxide films 28, the source and drain regions 29 sandwiching the channel are formed a certain distance apart from the edge of the gate electrodes in the so-called offset structure as illustrated in FIG. 3(C). An offset region is provided between the channel and each of the source and drain. The offset distance is considered to be about 300 nm corresponding to the thickness of the aluminum oxide film 28. The formation of source and drain regions may be carried out by the plasma doping technique (i.e., the ion doping technique), which can not separate different ions according to the mass differences, or another suitable doping technique.

After removing the Photoneece film 27, laser annealing is performed in order to recrystallize the source and drain regions in the same manner as in the first embodiment. In this case, however, the laser annealing is carried out by irradiating the semiconductor with 10 shots of a laser pulse through the substrate 21. Namely, the pulsed laser light is directed to the rear surface of the substrate 21. The laser is a XeCl excimer laser (308 nm wavelength) or a KrF excimer laser (350 nm wavelength). The selection of the laser is done taking the transparency of the substrate (Corning 7059 in this case) into consideration. If the substrate is made of quartz, a KrF laser (248 nm wavelength) can be utilized. The energy density of the laser pulse is, for example, 350 mJ/cm². The laser can be replaced by a halogen lamp to obtain the same performance. After the annealing, the wirings 25 which are not coated with aluminum oxide are selectively removed in order to leave only part 25a as illustrated in FIG. 3(C). As a result, a plurality of CMOS gate array are formed.

The structure is then coated with a silicon oxide interlayer film 30 deposited by sputtering. Contact holes 31a and 31b are opened through the silicon oxide films 24 and 30 by a known photolithography technique to expose the source and drain regions 29. Appropriate contact holes 32 may be also opened through the silicon oxide films 24 and 30 to expose the wiring 25a. These contact holes may be formed at the same time or separately in accordance with appropriate procedures necessary for the method. Finally, necessary wirings are formed from a metallic film by depositing and patterning an aluminum or chromium film.

In the case of the second embodiment, the semiconductor film islands are recrystallized by laser annealing in the same manner as in the first embodiment. The second laser annealing, however, is carried out by irradiating the substrate and the semiconductor film island with a laser light or a light emitted from a halogen lamp from the rear surface (from the back of the substrate) after the introduction of the impurity. This makes it possible to form the source and drain regions continuously and smoothly connected to the channel region located therebetween. If the first laser annealing is omitted, the upper portions of the semiconductor film islands may not be sufficiently recrystallized. For this reason, it is preferred to perform the laser annealing (or lamp annealing) from the both sides of the substrate. Furthermore, since the second laser annealing is performed from the rear surface of the substrate, it is effectively avoided that the gate electrode wirings are coming off due to the differential thermal expansion coefficient between the portions covered by aluminum oxide films and the portions which are not covered by aluminum oxide films.

The actual advantage of irradiation from the rear surface of the substrate will be understood from FIGS. 4(A) and 4(B). In the case of irradiation from the upper surface, the I_D -V_G characteristics were initially good as depicted by curve (a) in FIG. 4(A) but significantly deteriorated as depicted by curve (b) when a pulse of 25 to 30 V was repeatedly applied to the gate electrode. This is considered because hydrogen atoms terminating dangling bonds broke away from the interfaces between the channel region and the source and drain regions since the interface is discontinuous and provides poor connection. On the other hand, when the semiconductor film islands are irradiated with laser light from the rear surface of the substrate, the initial characteristics as depicted by curve (c) in FIG. 4(B) were maintained without appreciable deterioration even after operation for 100 hours as depicted by curve (d) in FIG. 4(B).

The foregoing description of preferred embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen in order to explain most clearly the principles of the invention and its practical application thereby to enable others in the art to utilize most effectively the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Claims

1. An electric circuit comprising:

a gate electrode provided on a substrate and comprising a material selected from the group consisting of aluminum, tantalum, aluminum having added thereto silicon, copper, tantalum, scandium and palladium, an alloy thereof and a multi-layer thereof;

a first wiring provided on said substrate and connected with said gate electrode and comprising said material, said first wiring having a width larger than that of said gate electrode; and

a second wiring provided on said substrate and connected with said first wiring and comprising said material, said second wiring having a width larger than that of said first wiring.

2. The circuit of claim 1 further comprising a channel provided on said substrate and adjacent to said gate electrode with a gate insulating film therebetween.

3. The circuit of claim 2 further comprising source and drain provided on said substrate and sandwiching said channel.

4. The circuit of claim 3 wherein an offset region is provided between said channel and each of said source and drain.

5. An electric circuit comprising:

a gate electrode provided on a substrate and comprising a material selected from the group consisting of aluminum, tantalum, aluminum having added thereto silicon, copper, tantalum, scandium and palladium, an alloy thereof and a multi-layer thereof;

a first wiring provided on said substrate and connected with said gate electrode and comprising said material, said first wiring having a width larger than that of said gate electrode;

a second wiring provided on said substrate and connected with said first wiring and comprising said material, said second wiring having a width larger than that of said first wiring; and

an anodic oxide coated on said gate electrode.

6. An electric circuit comprising:

a gate electrode provided on a substrate and comprising a material selected from the group consisting of aluminum, tantalum, aluminum having added thereto silicon, copper, tantalum scandium and palladium, an alloy thereof and a multi-layer thereof;

a first wiring provided on said substrate and connected with said gate electrode and comprising said material, width of said first wiring being increased to be larger than width of said gate electrode in order to reduce resistance of said first wiring; and

a second wiring provided on said substrate and connected with said first wiring and comprising said material, width of said second wiring being increased to be larger than width of said first wiring in order to reduce resistance of said second wiring.

7. The circuit of claim 6 wherein ratio (width of said first wiring)/(width of said gate wiring) is 2 to 10.

8. The circuit of claim 6 wherein ratio (width of said second wiring)/(width of said first wiring) is 2 to 10.

9. An electric circuit comprising:

a substrate having an insulating surface;

a first plurality of gate electrodes and a second plurality of gate electrodes on said insulating surface;

a plurality of semiconductor islands formed adjacent to said first and second plurality of gate electrodes,

a first branch line formed on said insulating surface, said first plurality of gate electrodes being connected to said first branch line in parallel;

a second branch line formed on said insulating surface, said second plurality of gate electrodes being connected to said second branch line in parallel; and

a trunk line formed on said insulating surface, said first and second branch lines being connected to said trunk line in parallel,

wherein a width of said gate electrodes is smaller than a width of said first and second branch lines, and the width of said first and second branch lines is smaller than said trunk line.