A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer is formed over the conductive layer, patterned and developed. The conductive layer is etched after which the first photoresist layer is removed. A second photoresist layer is formed over the integrated circuit, patterned and developed. The remaining regions of the conductive layer forming an interconnect or a gate are partially etched to form two-tiered stepped sidewalls.
|
13. A method of producing a conductive structure of a semiconductor integrated circuit having stepped sidewalls, comprising the steps of:
forming an insulating layer over a substrate; forming a conductive layer over the insulating layer; completely removing portions of the conductive layer to form a remaining conductive layer; and partially etching regions on the remaining conductive layer so that the remaining conductive layer has two-tiered stepped sidewalls.
1. A method of producing a conductive structure of a semiconductor integrated circuit having stepped walls, comprising the steps of:
forming an insulating layer over a substrate; forming a conductive layer over the insulating layer; forming a first photoresist layer over the conductive layer; patterning the first photoresist layer; etching the conductive layer to completely remove portions not covered by the patterned first photoresist layer and to form a remaining conductive layer; forming a second photoresist layer over the remaining conductive layer and the insulating layer; patterning the second photoresist layer; partially etching the remaining conductive layer to form a step; and, removing the second photoresist layer.
17. A method of producing a conductive structure of a semiconductor integrated circuit having stepped sidewalls, comprising the steps of:
forming an insulating layer over a substrate; forming a conductive layer over the insulating layer; forming and patterning a first photoresist layer over the conductive layer; etching the conductive layer to completely remove portions not covered by the patterned first photoresist layer and to form a remaining conductive layer; removing the first photoresist layer; forming and patterning a second photoresist layer over the remaining conductive layer; etching partway through the remaining conductive layer; removing the second photoresist layer; forming sidewall oxide spacers in regions of the conductive layer where the conductive layer was etched partway through; and etching portions of the remaining conductive layer not covered by the sidewall oxide spacers.
22. A method of producing a conductive structure having stepped walls in a semiconductor integrated circuit, comprising:
forming an insulating layer over a substrate; forming a conductive layer over the insulating layer; forming a first photoresist layer over the conductive layer; patterning the first photoresist layer to leave a first photoresist region over the conductive layer; etching the conductive layer to completely remove portions of the conductive layer not covered by the first photoresist region and to form a remaining conductive layer; removing the first photoresist region; forming a second photoresist layer over the remaining conductive layer and the insulating layer; patterning the second photoresist layer to form a second photoresist region located only over the remaining conductive layer, the second photoresist region being smaller than the first photoresist region; partially etching portions of the remaining conductive layer not covered by the second photoresist region to form a step; and removing the second photoresist region.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. The method of
12. The method of
14. The method of
15. The method of
16. The method of
18. The method of
19. The method of
20. The method of
lightly doping the substrate after removing the photoresist layer; heavily doping the substrate after etching the exposed region of the remaining conductive layer.
21. The method of
23. The method of
24. The method of
25. The method of
26. The method of
|
This application is a divisional of U.S. application Ser. No. 08/104,500, filed Aug. 10, 1993 now abandoned, which was a continuation of U.S. application Ser. No. 07/693,671, filed Apr. 30, 1991 now abandoned, which has been assigned to the assignee hereof and incorporated by reference herein.
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to producing stepped sidewall interconnects and gates.
With the trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes, photolithography has become one of the most critical steps in semiconductor manufacturing. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer.
As line widths shrink smaller and smaller in submicron photolithography, the process to print lines in photoresist becomes increasingly more difficult. Photoresists have been developed to keep pace with the industry's need to print narrower lines with fewer defects. The selection of the photoresist must be made on whether the photoresist has the capability of producing the design dimensions. The resist must also be able to function as an etchant barrier during the etching step and be free of pinholes. Furthermore, the selection of photoresist must provide for process latitude and step coverage capabilities.
Exposure light sources are chosen in photolithography based upon the characteristics of the photoresist. Standard production exposure tools used to print lines may limit how small the devices can be made. One problem with standard exposure tools is in the auto focus mechanism used to pattern a wafer. The exposure tools, when used in conjunction with thick photoresists have a small depth of focus so that light focused on the top of the photoresist will be out of focus near the bottom of the photoresist.
Production tools with light sources having longer wavelengths also create negative optical effects such as diffraction. Diffraction reduces the resolution of an image in the photoresist causing poor image definition.
Smaller features can be imaged clearly by using thinner photoresist layers for a given photoresist chemistry and optical tool. Thinner photoresists, however, are not suitable for all masking requirements because of the reduced ability to protect masked areas.
A concern in printing submicron devices is the resultant angle of the step from the top of the photoresist to the bottom of the layer in which the device is being made. If the angle is too steep, subsequently deposited layers may be too thin over the step and not fill in the spaces between adjacent devices. Thus, step coverage problems result.
Step coverage problems have been of prime importance throughout the history of integrated circuit manufacture. Poor step coverage can be found at the sharp vertical step metal to substrate contacts, metal to metal vias, and metal crossovers. On the other hand, there is a concern in printing submicron devices in close proximity to adjacent devices. Design criteria requires controlling the cross sectional lengths of the devices. Control of the cross sectional lengths of devices is best achieved when the sidewall slopes of the devices are 90 degrees. The critical dimension, or cross sectional length, is then a function of the critical dimension of the photoresist. If the sidewall slope is not 90 degrees, other factors must be considered in determining the critical dimension of the device, such as the angle of the sidewall slope, photoresist selectivity and the photoresist critical dimension.
As stated above, however, step coverage problems arise when the angle of the slope forms a steep sidewall. For example, as the height of a vertical or 90 degree sidewall increases, the percent of step coverage decreases. The ratio of the sidewall height to the space between adjacent structures is the aspect ratio. Device structures with high aspect ratios only increase step coverage problems. The spaces between the devices become harder to fill. On the other hand, sloped sidewall structures have an advantage over structures with sidewalls having a 90 degree angle because of a lower aspect ratio.
In order to increase step coverage while maintaining a lower aspect ratio, a two-tiered stepped sidewall is proposed by this invention. The step heights of each tier of the stepped sidewall are kept at a minimum, thus lowering the equivalent aspect ratio while increasing step coverage.
It would be desirable to provide a method for printing interconnects and gates having stepped sidewalls to enhance step coverage using thin photoresists. It would be further desirable for such fabrication technique to provide stepped sidewall profiles for use with small device geometries by lowering aspect ratios. It would be further desirable for such method to be compatible with current process technologies.
Therefore, according to the present invention, a method is provided for making submicron interconnects and transistor gates by forming an insulating layer over a substrate and a conductive layer over the insulating layer. The conductive layer is etched to form two-tiered stepped sidewalls.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-9 illustrate one method for forming integrated circuit structures according to the present invention.
FIGS. 10-12 illustrate an alternate method for forming integrated circuit structures according to the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, an integrated circuit device is to be formed in a silicon substrate 10. Selected regions of the substrate 10 are oxidized to form an oxide insulating layer 12. A conductive layer 14 is deposited over the insulating layer 12 by methods known in the art. The conductive layer 14 may a metal or a polysilicon. A first layer of photoresist 16 is formed on the conductive layer. Photoresist layer 16 is then patterned and developed.
Referring to FIG. 2, conductive layer 14 is then etched by methods known in the art, using photoresist layer 16 as a mask. Among the various devices manufactured, conductive layer 14 may be used as an interconnect or as the gate of a field effect transistor. Photoresist layer 16 is then stripped away.
Referring to FIG. 3, second photoresist layer 18 is spun onto the wafer again by known methods covering the remaining regions of conductive layer 14 and the exposed regions of insulating layer 12. Photoresist layers 16 and 18 typically have a thickness of less than 1.2 microns and preferably between approximately 0.1 and 0.5 microns. In order to adequately protect masked areas, one photoresist layer may need to be thicker than the other photoresist layer.
Referring to FIG. 4, photoresist layer 18 is patterned and developed by methods known in the art. The pattern of the second photoresist layer 18 is smaller than the pattern of the first photoresist layer 16. The remaining conductive layer 14 regions are then partially etched using photoresist layer 18 as a mask to form the two-tiered stepped sidewalls as shown in FIG. 5.
Referring to FIG. 6, photoresist layer 18 is stripped away leaving the interconnect or gate device structure shown. The height of each vertical section of the two-tiered stepped sidewalls will be smaller than the total height of the device. Thus, step coverage will improve over the device and the aspect ratio will be lowered.
If a gate of a field effect transistor is to be manufactured, the additional steps necessary to manufacture source and drain regions of the transistor need to be implemented during or after the manufacture of the gate. Referring to FIG. 7, the process steps are the same as above as shown in FIGS. 1-2. An insulating layer 22 is grown on substrate 20. A conductive layer 24 is deposited on insulating layer 22. A first photoresist layer 26 is spun onto the conductive layer 24, patterned and developed. Conductive layer 24 is then etched using photoresist layer 26 as a mask. The source and drain regions are created using two different implantation steps as known in the art. The first implantation step occurs after removing the first photoresist layer 26. Source and drain regions 28 are formed by heavily doping insulating layer 22. The dopant used during these implantation steps may be either N-type or P-type.
Referring to FIG. 8, a second photoresist layer 30 is then spun onto the remaining regions of conductive layer 24 and the exposed regions of insulating layer 22. Photoresist layer 30 is patterned and developed. Conductive layer 24, which forms the gate of a field effect transistor, is then etched to form the two-tiered stepped sidewalls using photoresist layer 30 as a mask. Insulating layer 22 and substrate 20 are lightly doped after the second photoresist layer 30 is removed to form a second source/drain region 32 underneath the step of the conductive layer 24. Again, either N-type or P-type dopants may be used to minimize resistance of these regions. An alternative to implanting dopants at two different stages of the process to form the source/drain regions is to form both source/drain regions 28 and 32 after conductive layer 24 is partially etched to form the two-tiered stepped sidewalls. No sidewall oxide spacers are required in using either alternative in this process to create the source/drain regions. Referring to FIG. 9, the gate device shown as conductive layer 24 is formed with first and second source/drain regions 28 and 32.
Referring to FIG. 10, an alternative method of producing a structure with stepped sidewalls is shown. As above, insulating layer 22 is formed on substrate 20 and conductive layer 24 is formed on insulating layer 22. Photoresist layer 26 is formed on conductive layer 24, patterned and developed. Conductive layer 24 is then etched partway through using photoresist layer 26 as a mask. Photoresist layer 26 is then removed. Sidewall oxide spacers 34 are then formed by methods known in the art at the step of conductive layer 24. Conductive layer 24 is then further etched using sidewall oxide spacers 34 as a mask. If the structure to be manufactured is an interconnect, the sidewall oxide spacers 34 are removed to form the structure shown in FIG. 6.
Referring to FIG. 11, where a gate of a field effect transistor is to be made, two implantation steps are necessary to form source/drain regions 36 and 38. Source/drain regions 36 are first formed by lightly doping the substrate 20 after photoresist layer 26 is removed. Source/drain regions 38 are then formed by heavily doping the substrate 20 after the final etching step of conductive layer 24 and before the sidewall oxide spacers 34 are removed. The sidewall oxide spacers 34 are then removed to form the structure shown in FIG. 12.
This alternative allows a single thin layer of photoresist to clearly image the device, providing for self-alignment. Moreover, by forming sidewall oxide spacers, the source/drain regions of a gate can be easily formed.
Submicron devices, such as interconnects and gates, can be produced with sufficient control to allow for short distances between adjacent devices, if the sidewalls have a 90 degree angle. By forming a two-tiered stepped sidewall using thin photoresists to clearly image the devices, the equivalent aspect ratio is minimized and step coverage maximized allowing the distances between devices to be minimized.
Patent | Priority | Assignee | Title |
10236356, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
10271381, | May 22 2017 | Honeywell International Inc. | Legacy Modbus communication devices |
10272260, | Nov 23 2011 | BRONCUS MEDICAL INC. | Methods and devices for diagnosing, monitoring, or treating medical conditions through an opening through an airway wall |
10631938, | May 13 2011 | BRONCUS MEDICAL INC. | Methods and devices for diagnosing, monitoring, or treating medical conditions through an opening through an airway wall |
10763370, | Apr 12 2018 | ATOMERA INCORPORATED | Inverted T channel field effect transistor (ITFET) including a superlattice |
11664459, | Apr 12 2018 | ATOMERA INCORPORATED | Method for making an inverted T channel field effect transistor (ITFET) including a superlattice |
5937326, | Jun 09 1995 | MagnaChip Semiconductor, Ltd | Method for making semiconductor device having via hole |
6040220, | Oct 14 1997 | Advanced Micro Devices, Inc. | Asymmetrical transistor formed from a gate conductor of unequal thickness |
6083816, | Nov 28 1997 | OKI SEMICONDUCTOR CO , LTD | Semiconductor device and method of manufacturing the same |
6090676, | Sep 08 1998 | Advanced Micro Devices, Inc. | Process for making high performance MOSFET with scaled gate electrode thickness |
6624473, | Mar 10 1999 | TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO , LTD | Thin-film transistor, panel, and methods for producing them |
6800528, | Jun 14 2002 | OKI SEMICONDUCTOR CO , LTD | Method of fabricating LDMOS semiconductor devices |
6812490, | Mar 10 1999 | TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO , LTD | Thin-film transistor, panel, and methods for producing them |
6815337, | Feb 17 2004 | Episil Technologies, Inc. | Method to improve borderless metal line process window for sub-micron designs |
6960517, | Jun 30 2003 | Intel Corporation | N-gate transistor |
7456476, | Jun 27 2003 | TAHOE RESEARCH, LTD | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
7479421, | Sep 28 2005 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
7518196, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
7528025, | Sep 30 2004 | TAHOE RESEARCH, LTD | Nonplanar transistors with metal gate electrodes |
7547637, | Jun 21 2005 | TAHOE RESEARCH, LTD | Methods for patterning a semiconductor film |
7550333, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
7579280, | Jun 01 2004 | Intel Corporation | Method of patterning a film |
7714397, | Jun 27 2003 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
7736956, | Aug 17 2005 | TAHOE RESEARCH, LTD | Lateral undercut of metal gate in SOI device |
7781771, | Mar 31 2004 | TAHOE RESEARCH, LTD | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
7820513, | Jun 27 2003 | TAHOE RESEARCH, LTD | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
7825481, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
7859053, | Sep 29 2004 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
7879675, | Mar 14 2005 | Intel Corporation | Field effect transistor with metal source/drain regions |
7893506, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
7898041, | Jun 30 2005 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
7902014, | Sep 28 2005 | TAHOE RESEARCH, LTD | CMOS devices with a single work function gate electrode and method of fabrication |
7915167, | Sep 29 2005 | TAHOE RESEARCH, LTD | Fabrication of channel wraparound gate structure for field-effect transistor |
7960794, | Aug 10 2004 | TAHOE RESEARCH, LTD | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
7989280, | Nov 30 2005 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
8067818, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
8071983, | Jun 21 2005 | TAHOE RESEARCH, LTD | Semiconductor device structures and methods of forming semiconductor structures |
8084818, | Jun 30 2004 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
8183646, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
8193567, | Sep 28 2005 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
8268709, | Sep 29 2004 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
8273626, | Jun 27 2003 | TAHOE RESEARCH, LTD | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
8294180, | Sep 28 2005 | TAHOE RESEARCH, LTD | CMOS devices with a single work function gate electrode and method of fabrication |
8362566, | Jun 23 2008 | TAHOE RESEARCH, LTD | Stress in trigate devices using complimentary gate fill materials |
8368135, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
8399922, | Sep 29 2004 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
8405164, | Jun 27 2003 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
8502351, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
8581258, | Jun 21 2005 | TAHOE RESEARCH, LTD | Semiconductor device structures and methods of forming semiconductor structures |
8617945, | Aug 02 2006 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
8664694, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
8741733, | Jun 23 2008 | TAHOE RESEARCH, LTD | Stress in trigate devices using complimentary gate fill materials |
8749026, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
8816394, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
8933458, | Jun 21 2005 | TAHOE RESEARCH, LTD | Semiconductor device structures and methods of forming semiconductor structures |
9048314, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
9190518, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
9224754, | Jun 23 2008 | TAHOE RESEARCH, LTD | Stress in trigate devices using complimentary gate fill materials |
9337307, | Jun 15 2005 | TAHOE RESEARCH, LTD | Method for fabricating transistor with thinned channel |
9368583, | Feb 23 2005 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
9385180, | Jun 21 2005 | TAHOE RESEARCH, LTD | Semiconductor device structures and methods of forming semiconductor structures |
9450092, | Jun 23 2008 | TAHOE RESEARCH, LTD | Stress in trigate devices using complimentary gate fill materials |
9741809, | Oct 25 2004 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
9761724, | Jun 21 2005 | TAHOE RESEARCH, LTD | Semiconductor device structures and methods of forming semiconductor structures |
9806193, | Jun 23 2008 | TAHOE RESEARCH, LTD | Stress in trigate devices using complimentary gate fill materials |
9806195, | Jun 15 2005 | TAHOE RESEARCH, LTD | Method for fabricating transistor with thinned channel |
9913969, | Oct 05 2006 | BRONCUS MEDICAL INC. | Devices for delivering substances through an extra-anatomic opening created in an airway |
9993306, | May 13 2011 | BRONCUS MEDICAL INC. | Methods and devices for diagnosing, monitoring, or treating medical conditions through an opening through an airway wall |
Patent | Priority | Assignee | Title |
4472237, | May 22 1981 | AT&T Bell Laboratories | Reactive ion etching of tantalum and silicon |
4617193, | Jun 16 1983 | COMPAQ INFORMATION TECHNOLOGIES GROUP, L P | Planar interconnect for integrated circuits |
4764480, | Apr 01 1985 | National Semiconductor Corporation | Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size |
4818715, | Jul 09 1987 | Transpacific IP Ltd | Method of fabricating a LDDFET with self-aligned silicide |
4905068, | Mar 10 1987 | MITSUBISHI DENKI KABUSHIKI KAISHA, 2-3 MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN | Semiconductor device having interconnection layers of T-shape cross section |
4907048, | Nov 23 1987 | Xerox Corporation; XEROX CORPORATION, STAMFORD, CT A CORP OF NEW YORK | Double implanted LDD transistor self-aligned with gate |
4917759, | Apr 17 1989 | Motorola, Inc. | Method for forming self-aligned vias in multi-level metal integrated circuits |
4994873, | Oct 17 1988 | Motorola, Inc. | Local interconnect for stacked polysilicon device |
4996584, | Jan 31 1985 | AMI Semiconductor, Inc | Thin-film electrical connections for integrated circuits |
5043294, | Sep 04 1989 | Siemens Aktiengesellschaft | Method for manufacturing an FET with asymmetrical gate region |
5053841, | Oct 19 1988 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory |
5061975, | Feb 19 1988 | Mitsubishi Denki Kabushiki Kaisha | MOS type field effect transistor having LDD structure |
5089863, | Sep 08 1988 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with T-shaped gate electrode |
5100820, | Jun 14 1990 | OKI SEMICONDUCTOR CO , LTD | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
5113238, | Jan 06 1989 | Promos Technologies Inc | Contactless non-volatile memory array cells |
5204285, | Dec 01 1989 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Method for patterning a metal layer |
5266508, | Aug 26 1991 | Sharp Kabushiki Kaisha | Process for manufacturing semiconductor device |
5384479, | Oct 14 1991 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with T-shaped gate electrode |
5578166, | May 17 1993 | Fujitsu Limited | Method of reactive ion etching of a thin copper film |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Oct 14 1994 | SGS-Thomson Microelectronics, Inc. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Jul 18 2002 | M183: Payment of Maintenance Fee, 4th Year, Large Entity. |
Aug 29 2006 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Aug 25 2010 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Aug 26 2010 | ASPN: Payor Number Assigned. |
Date | Maintenance Schedule |
Mar 09 2002 | 4 years fee payment window open |
Sep 09 2002 | 6 months grace period start (w surcharge) |
Mar 09 2003 | patent expiry (for year 4) |
Mar 09 2005 | 2 years to revive unintentionally abandoned end. (for year 4) |
Mar 09 2006 | 8 years fee payment window open |
Sep 09 2006 | 6 months grace period start (w surcharge) |
Mar 09 2007 | patent expiry (for year 8) |
Mar 09 2009 | 2 years to revive unintentionally abandoned end. (for year 8) |
Mar 09 2010 | 12 years fee payment window open |
Sep 09 2010 | 6 months grace period start (w surcharge) |
Mar 09 2011 | patent expiry (for year 12) |
Mar 09 2013 | 2 years to revive unintentionally abandoned end. (for year 12) |