The present invention discloses a method to manufacture metal gate of integrated circuits. A gate oxide layer is formed on a substrate and a polysilicon layer is then deposited on the gate oxide layer. Afterwards, a barrier layer is formed on the polysilicon layer and a metal layer is deposited on the barrier layer. An etching process is performed to etch the metal layer and the barrier layer, and a metal gate is defined. Then, silicon nitride liners are formed on the sidewalls of the metal gate. Finally, silicon nitride spacers are formed on the silicon nitride liners and on the sidewalls of the polysilicon gate to serve as an insulating layer.
|
1. A method for fabricating a metal gate of integrated circuits, comprising:
providing a substrate; forming a gate oxide layer on said substrate; forming a polysilicon layer on said gate oxide layer; forming a barrier layer on said polysilicon layer; forming a metal layer on said barrier layer; etching only said metal layer and said barrier layer to define said metal gate on said barrier layer; forming a liner on sidewalls of said metal gate to protect said metal layer and said barrier layer; and then etching said polysilicon layer and said gate oxide layer, wherein said polysilicon layer and said gate oxide layer under said barrier layer is remained to be a polysilicon gate, wherein said polysilicon gate being a contact layer between said metal gate and said substrate.
11. A method for fabricating a metal gate of integrated circuits, comprising:
providing a substrate; forming a gate oxide layer on said substrate; forming a polysilicon layer on said gate oxide layer; forming a barrier layer on said polysilicon layer; forming a metal layer on said barrier layer; forming a silicon nitride layer on said metal layer; etching only said nitride layer, said metal layer and said barrier layer to define said metal gate; forming liners on sidewalls of said metal gate to protect said silicon nitride layer, said metal layer and said barrier layer; etching said polysilicon layer and said gate oxide layer, and said polysilicon layer and said gate oxide layer under said barrier layer being remained to be a polysilicon gate, wherein said polysilicon gate is used to be a contact layer between said substrate and said metal gate; and forming spacers on sidewalls of said liners, said polysilicon layer and said gate oxide layer.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
9. The method of
10. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
19. The method of
|
|||||||||||||||||||||||||||
The present invention relates to a method for fabricating a metal gate of integrated circuits, and more specifically, to a method for fabricating a metal gate with silicon nitride spacers for integrated circuits.
According to the trend for the development of integrated circuits, the integration of integrated circuits is increased as large as possible. Many techniques to shrink the dimension of devices are implemented to increase the density of the devices on a silicon wafer.
To reduce the dimension of devices is accompanied by many problems, such as short-channel effect. Besides, the contact resistance of the devices is increased. After the metallization process of the devices, the contact resistance between an active region and a metallic contact of a large-size device is lower than that of a small-size device. Simultaneously, the performance of the small-size devices will be degraded. Thus, a method to manufacture a gate, which is made of metal material, is proposed to reduce the contact resistance between the gate and the substrate and also the gate sheet resistance. In the following descriptions, a method for fabricating a metal gate is described.
Referring to FIG. 1, a substrate 100 is used to be a basis for integrated circuits. A gate oxide layer 110 is deposited on the substrate 100 and a polysilicon layer 120 is then deposited on the gate oxide layer 110. A barrier layer 130 and a metal layer 140 are sequentially deposited. At last, a silicon nitride layer 150 covers the metal layer 140.
As the metal layer 140 will react on the polysilicon layer 120 to form a silicide layer between the metal layer 140 and the polysilicon layer 120, a barrier layer 130 is used to prevent from the formation of the silicide layer. Besides, an ohmic contact is formed between the metal layer 140 and the polysilicon layer 120. Another reason for using the barrier layer is to prevent metal ions from diffusing into the gate oxide layer 110 during the following process for integrated circuits. If the gate oxide layer 110 is degraded, the devices could not be operated. As a lower resistance of the metal gate, a current can be easily transfer through the metal gate.
In memory devices, source/drain regions must be connect to metal contacts. The silicon nitride layer 150 on the metal layer 140 is served as a etching protective layer for a self-aligned contact process of the source/drain regions to protect the metal layer 140. The silicon nitride layer 150 is not needed for the process of all kinds of devices, for example, the process for fabricating logic circuits do not comprise the self-aligned contact stage. So, the silicon nitride layer 150 could be optionally deposited.
Referring to FIG. 2, the layers on the substrate are etched to define the metal gate of integrated circuits. A resistance pattern (not shown) is defined on the silicon nitride layer 150 by using lithography technology. Afterwards, the silicon nitride layer 150, the metal layer 140, the barrier layer 130, the polysilicon layer 120 and the gate oxide layer 110 are anisotropically etched by using a plasma etching process.
Referring to FIG. 3, after the definition of the metal gate, a silicon nitride layer is deposited to cover the surface of the gate and the substrate 100. A dry etching is performed to etch the silicon nitride layer and silicon nitride spacers are formed to on the sidewalls of the gate to serve as an insulating layer.
Metal gates exhibit a low sheet resistance. Nevertheless, oxidation or cleaning process is needed during the process, as is shown in FIG. 2. The process for forming lightly doped drains or a process, which is implemented in an oxygen ambient, will cause the devices failure. As the volume of the layers is changed after an oxidation process, a stress is induced in the metal gate so that the layers on the substrate peel off.
An issue about the metal gate is that the metal gate is etched or degraded by an acid solution or a base solution during cleaning processes. Thus, the metal gate must be protected so that a device with the metal gate has a high reliability.
A method for fabricating a metal gate of integrated circuits is disclosed in the present invention. A substrate is provided for the basis of integrated circuits. A gate oxide layer, a polysilicon layer, a barrier layer and a metal layer are sequentially deposited on the substrate. The metal layer and the barrier layer are etched to define the metal gate of integrated circuit. Then, liners is formed on sidewalls of the metal gate for protecting. Finally, the polysilicon layer and the gate oxide layer are etched. The polysilicon layer and the gate oxide layer under the barrier layer is used to be a contact layer between the metal gate and the substrate for the same work function with nominal polysilicon gate.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic cross sectional view of a substrate in accordance with prior art, a gate oxide layer, a polysilicon layer, a barrier layer, a metal layer and a silicon nitride layer are deposited on the substrate;
FIG. 2 is a schematic cross sectional view of the substrate in accordance with prior art, gate structures of integrated circuits is defined on the substrate;
FIG. 3 is a schematic cross sectional view of the substrate in accordance with prior art, silicon nitride spacers are formed on the sidewalls of the metal gates to be an insulating layer for the gates;
FIG. 4 is a schematic cross sectional view of the substrate in accordance with the present invention, a gate oxide layer, a polysilicon layer, a barrier layer, a metal layer and a silicon nitride layer are deposited on the substrate;
FIG. 5 is a schematic cross sectional view of the substrate in accordance with the present invention, the silicon nitride layer, the metal layer and the barrier layer are etched to form a metal gate on the polysilicon layer;
FIG. 6 is a schematic cross sectional view of the substrate in accordance with the present invention, silicon nitride liners are formed on the sidewalls of the metal gates to protect the metal gates from etching;
FIG. 7 is a schematic cross sectional view of the substrate in accordance with the present invention, the polysilicon layer and the gate oxide layer are etched and a polysilicon layer is formed between the metal gates and the substrate to be a contact layer; and
FIG. 8 is a schematic cross sectional view of the substrate in accordance with the present invention, the silicon nitride spacers cover on the sidewalls of the metal gates and the polysilicon gates.
The present invention discloses a method for fabricating a metal gate of integrated circuits. A barrier layer and a metal layer are sequentially deposited on the polysilicon gates of integrated circuits and the composite structures are metal gates of integrated circuits. Afterwards, a silicon nitride liners are formed on the sidewalls of the metal gates. The silicon nitride liners are indicated as an insulating layer and it protects the metal gates from degradation during oxidation or cleaning processes. Silicon nitride spacers are formed on the side-surface of the silicon nitride liners and the polysilicon gates. After the formation of the silicon nitride spacers, the metal gate structure is complete. The silicon nitride liners protect the metal gates of integrated circuits against an acid solution or a base solution.
Referring to FIG. 4, a substrate 100 is provided and integrated circuits will be constructed on it. The substrate 100 is a semiconductor substrate with <100> crystal orientation. Firstly, a gate oxide layer 110 is formed on the surface of the substrate 100. As known in the art, the gate oxide layer 110 is formed by using a thermal oxidation process or a conventional chemical vapor deposition process. In a case, the thickness of the gate oxide layer 110 is between about 50 to 100 angstroms. Afterwards, a polysilicon layer 120 is deposited on the gate oxide layer 110 and a polysilicon gate consisting of the gate oxide layer 110 and the polysilicon layer 120 is formed. As skilled in the art, the method to deposit the polysilicon layer 120 is low pressure chemical vapor deposition (LPCVD) process and the polysilicon layer 120 has a thickness between about 1000 to 3000 angstroms.
Referring to FIG. 4 again, a barrier layer 130 is formed on the polysilicon layer 120 to be a contact layer between polysilicon material and metal material. By using the barrier layer 130, an ohmic contact can be formed between the polysilicon gate and a metal gate on the polysilicon gate. As skilled in the art, the barrier layer 130 is made of titanium nitride, tungsten titanium or tungsten nitride, and the technology for forming the barrier layer 130 is physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process. In a case, the barrier layer 130 has a thickness between about 50 to 500 angstroms.
Still referring to FIG. 4, a metal layer 140 is formed on the barrier layer 130 by using physical vapor deposition (PVD) process and it is made of titanium silicide, tungsten or cobalt silicide. In a preferred embodiment, the metal layer 140 has a thickness between about 700 to 1500 angstroms.
Referring to FIG. 4 again, a silicon nitride layer 150 is formed to cover the surface of the metal layer 140. The silicon nitride layer 150 is used to be a protective layer of the metal gate and an etching mask for the metal gate during a self-aligned contact process. As skilled in the art, the silicon nitride layer 150 is deposited by using low pressure chemical vapor deposition (LPCVD) process. In a case, the thickness of the silicon nitride layer 150 is between about 2000 to 3000 angstroms. In the manufacturing of logic circuits, a self-aligned contact process for source/drain regions is not required. Thus, the metal gates of logic circuits do not need a protective layer and the silicon nitride layer 150 can be optionally deposited.
Referring to FIG. 5, the silicon nitride layer 150, the metal layer 140 and the barrier layer 130 are etched to define a metal gate on the polysilicon layer 120 by using an anisotropical etching process, such as a plasma etching process. Besides, the pattern of the metal gate is defined by using a conventional lithography technology.
Referring to FIG. 6, silicon nitride liners 160 are formed on the sidewalls of the metal gate to protect the sidewalls of the silicon nitride layer 150, the metal layer 140 and the barrier layer 130. The formation of the silicon nitride liners 160 is to deposit a silicon nitride layer over the surface of the metal gate and to cover the substrate 100. In a preferred embodiment, the forgoing silicon nitride layer has a thickness between about 100 to 200 angstroms. Afterwards, the silicon nitride layer on the metal gate and on the substrate is removed and the silicon nitride layer on the sidewalls of the metal gate is remained to be the silicon nitride liners 160.
The silicon nitride liners 160 cover the sidewalls of the metal gate for protecting and the metal gate will not be degraded or etched during following oxidation and cleaning processes. In prior art, the silicon nitride liners 160 do not protect the metal gate; the metal gate and the polysilicon gate are simultaneously formed during an etching process. The metal gate is easy to be degraded. Consequently, the silicon nitride liners in the present invention could protect the metal gate from the forgoing problem in prior art.
Referring to FIG. 7, the polysilicon layer 120 and the gate oxide layer 110 are etched to define the structure of the polysilicon gate by using the silicon nitride layer 150 and the silicon nitride liners 160 to serve as an etching mask. In a preferred embodiment, a plasma etching technology is used for the etching process to define the polysilicon gate . Because the polysilicon material and the oxide material have a high etching selectivity to the silicon nitride material, the silicon nitride layer 150 and the silicon nitride liners 160 are served as an etching mask. A lithography process to define the pattern of the polysilicon gate is not required in the present invention.
Referring to FIG. 8, silicon nitride spacers 160 are formed on the sidewalls of the silicon nitride liners 160, and the polysilicon layer 120 and the gate oxide layer 110. The silicon nitride spacers 160 are indicated as a hard mask during the self-aligned contact process of source/drain regions. A self-aligned contact for the source/drain region is formed between the silicon nitride spacers 160. As skilled in the art, the deposition of the silicon nitride spacers 170 is to deposit a silicon nitride layer, which has a thickness between about 400 to 800 angstroms. An etching process is performed to remove the silicon nitride layer on the silicon nitride layer 150 and the substrate 100 and the silicon nitride spacers 170 is remained on the sidewalls of the gate structure.
The silicon nitride spacers 170 are indicated as a hard mask for the gate structure during the self-aligned contact process of source/drain regions. If integrated circuits do not comprise a self-aligned contact process, the spacers for the gate structure could not be made of silicon nitride material and it can be made of silicon oxide material for insulating.
After the manufacturing of the gate structure, the processes to fabricate active regions of integrated circuits and the metallic process are performed, and these processes are similar to that is used in prior art.
While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.
| Patent | Priority | Assignee | Title |
| 10985262, | Nov 07 2017 | Winbond Electronics Corp. | Semiconductor structure and manufacturing method thereof |
| 11302705, | Nov 08 2018 | Winbond Electronics Corp. | Semiconductor structure and the forming method thereof |
| 11839075, | Nov 08 2018 | Winbond Electronics Corp. | Semiconductor structure and the forming method thereof |
| 6277699, | Nov 06 1998 | United Microelectronics Corp. | Method for forming a metal-oxide-semiconductor transistor |
| 6326260, | Jun 22 2000 | International Business Machines Corporation | Gate prespacers for high density, high performance DRAMs |
| 6333250, | Dec 28 1998 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate electrode in semiconductor device |
| 6346467, | Sep 02 1999 | MONTEREY RESEARCH, LLC | Method of making tungsten gate MOS transistor and memory cell by encapsulating |
| 6509282, | Nov 26 2001 | GLOBALFOUNDRIES Inc | Silicon-starved PECVD method for metal gate electrode dielectric spacer |
| 6573132, | Mar 25 1999 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof |
| 6605848, | Nov 26 2001 | GLOBALFOUNDRIES U S INC | Semiconductor device with metal gate electrode and silicon oxynitride spacer |
| 6713826, | Mar 25 1999 | Matsushita Electric Industrial Co., Ltd | Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof |
| 7459383, | Nov 09 2005 | ProMos Technologies Inc. | Fabricating method of gate structure |
| 7781333, | Dec 27 2006 | Hynix Semiconductor Inc. | Semiconductor device with gate structure and method for fabricating the semiconductor device |
| 7902614, | Dec 27 2006 | Hynix Semiconductor Inc. | Semiconductor device with gate stack structure |
| 8008178, | Dec 27 2006 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with an intermediate stack structure |
| 8319341, | Dec 27 2006 | Hynix Semiconductor Inc. | Semiconductor device with gate structure |
| 8441079, | Dec 27 2006 | Hynix Semiconductor Inc. | Semiconductor device with gate stack structure |
| 9064854, | Dec 27 2006 | SK Hynix Inc. | Semiconductor device with gate stack structure |
| 9401279, | Jun 14 2013 | SanDisk Technologies LLC | Transistor gate and process for making transistor gate |
| Patent | Priority | Assignee | Title |
| 5304504, | Dec 18 1991 | SGS-Thomson Microelectronics, Inc. | Method of forming a gate overlap LDD structure |
| 5679591, | Dec 16 1996 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of making raised-bitline contactless trenched flash memory cell |
| 5874353, | Jul 31 1997 | United Microelectronics Corporation | Method of forming a self-aligned silicide device |
| 5888588, | Mar 31 1997 | Freescale Semiconductor, Inc | Process for forming a semiconductor device |
| 5897349, | Apr 19 1995 | International Business Machines Corporation | Method for fabricating a capped gate conductor |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jun 18 1998 | TSAI, KWONG-JR | Vanguard International Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009315 | /0860 | |
| Jul 09 1998 | Vanguard International Semiconductor Corporation | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Feb 18 2004 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Dec 27 2007 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Jan 20 2012 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Aug 22 2003 | 4 years fee payment window open |
| Feb 22 2004 | 6 months grace period start (w surcharge) |
| Aug 22 2004 | patent expiry (for year 4) |
| Aug 22 2006 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Aug 22 2007 | 8 years fee payment window open |
| Feb 22 2008 | 6 months grace period start (w surcharge) |
| Aug 22 2008 | patent expiry (for year 8) |
| Aug 22 2010 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Aug 22 2011 | 12 years fee payment window open |
| Feb 22 2012 | 6 months grace period start (w surcharge) |
| Aug 22 2012 | patent expiry (for year 12) |
| Aug 22 2014 | 2 years to revive unintentionally abandoned end. (for year 12) |