Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
|
1. A method for fabricating a semiconductor device, the method comprising:
forming at least two isolating regions, separated by an isolated region, within a substrate; forming a floating gate over the substrate; forming a dielectric layer on the floating gate and at least a portion of each of the two isolating regions; and forming at least one spacer on a portion of the dielectric layer, wherein the portion of the dielectric layer is at least partially located directly over and contacting one of the two isolating regions.
20. A method for forming a control gate in a non-volatile memory device, the method comprising:
forming a dielectric layer on a floating gate arranged within a semiconductor device; forming a first layer of conductive material on the dielectric layer; removing a portion of the first layer of conductive material; forming a second layer of conductive material on a remaining portion of the first layer of conductive material; and selectively patterning the second layer and the remaining portion of the first layer of conductive material to form a control gate.
11. A method for fabricating a semiconductor device, the method comprising:
forming at least two isolating regions, separated by an isolated region, within a substrate; forming a floating gate over the substrate; forming at least one spacer that contacts the floating gate and one of the two isolating regions; forming a dielectric layer on the floating gate, the spacer and at least a portion of each of the two isolating regions; forming a control gate on at least a portion of the dielectric layer and at least partially located directly over at least a portion of the floating gate; and forming a silicide on at least a portion of the control gate.
26. A method for forming a floating gate with at least one spacer in a non-volatile memory device, said device consisting essentially of a semiconductor substrate having a tunnel oxide portion and at least one isolating region in said semiconductor, the method consisting of:
forming a first layer of conductive material on the tunnel oxide portion of the semiconductor device; selectively patterning the first layer of conductive material, said first layer of conductive material forming an initial floating gate; forming a second layer of conductive material on the initial floating gate and at least a portion of one isolating region of the semiconductor device; and removing at least a portion of the second layer of conductive material to form at least one spacer that contacts the isolating region and the initial floating gate.
2. The method as recited in
3. The method as recited in
4. The method as recited in
forming a control gate on at least a portion of the dielectric layer and at least partially located directly over at least a portion of the floating gate; and forming a silicide on at least a portion of the control gate.
5. The method as recited in
6. The method as recited in
10. The method as recited in
12. The method as recited in
13. The method as recited in
14. The method as recited in
16. The method as recited in
19. The method as recited in
21. The method as recited in
22. The method as recited in
23. The method as recited in
24. The method as recited in
25. The method as recited in
|
|||||||||||||||||||||||||||
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and apparatus associated with non-volatile memory semiconductor devices.
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1a. As shown, memory cell 8 is viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and within which a source 13a and a drain 13b have been formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
On top of control gate 26 there is a silicide layer 28, which acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a.
FIG. 1b depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line. In FIG. 1b, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1b shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a-b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a-c and field oxide regions 14a-b. Interpoly dielectric layer 24 isolates floating gates 16a-c from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as a oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the features depicted in the memory cells of FIGS. 1a-b, places a burden on the fabrication process to deposit/form the floating gate 16 and control gate 26 without creating deleterious effects within the memory cell. Of particular concern caused by the shrinking dimensions is the need to provide adequate isolation between each of the floating gates 16a-c, and between each of the floating gates 16a-c and control gate 26, while also providing an adequately arranged floating/control gate configuration.
These needs and others are met by the present invention, which provides methods and arrangements that increase the process control during the fabrication of semiconductor devices, and in particular, during the formation of the floating/control gate configuration in a non-volatile memory semiconductor device. In accordance with one aspect of the present invention, it has been found that, in certain semiconductor arrangements, the topology created by the space between adjacent floating gates (e.g., 16a and 16b, can be so severe in shape (e.g., deep and narrow) that the silicide layer 28 formed on the overlying control gate 26 often contains significant depressions over the space. These significant depressions can lead to cracks in the silicide layer 28 during subsequent thermal processing of the semiconductor device, which tends to stress the silicide layer 28.
In accordance with one aspect of the present invention, the amount and shape of the open spaces located between floating gates following patterning is reduced and altered to present a modified topology that is not so severe. The modified topology improves the step coverage of both the control gate material and silicide material, and thereby does not cause significant depressions to form in the subsequently formed silicide layer 28. Consequently, cracking of silicide layer 28 is substantially less likely to occur during the subsequent thermal processes.
Thus, in accordance with certain embodiments of the present invention, a method, and an associated arrangement, are provided. The method includes the step of forming at least two isolating regions, separated by an isolated region, within a substrate. The method further includes the steps of forming a tunnel oxide on the top surface of the substrate and within the isolated region, forming a floating gate over the substrate, forming a dielectric layer on the floating gate and at least a portion of each of the two isolating regions, and forming at least one spacer on a portion of the dielectric layer, wherein the portion of the dielectric layer is at least partially located directly over and contacting one of the two isolating regions.
The above stated needs are further met by still other embodiments of the present invention that also include a method and associated arrangements. The method for fabricating a semiconductor device includes the step of forming at least two isolating regions, separated by an isolated region, within a substrate. The method further includes the steps of forming a floating gate over the substrate, forming at least one spacer that contacts the floating gate and one of the two isolating regions, and forming a dielectric layer on the floating gate, the spacer and at least a portion of each of the two isolating regions.
In accordance with still other embodiments of the present invention, there is provided a method for forming a control gate in a non-volatile memory device. The method includes the steps of forming a dielectric layer on a floating gate arranged within a semiconductor device, forming a first layer of conductive material on the dielectric layer, removing a portion of the first layer of conductive material, forming a second layer of conductive material on a remaining portion of the first layer of conductive material, and selectively patterning the second layer and the remaining portion of the first layer of conductive material to form a control gate. In certain embodiments, the step of removing a portion of the first layer further includes removing substantially all of the first layer to form at least one spacer.
In accordance with certain embodiments of the present invention, a method is also provided for forming a floating gate in a non-volatile memory device. The method includes the steps of forming a first layer of conductive material on a tunnel oxide portion of a semiconductor device, selectively patterning the first layer of conductive material to form an initial floating gate, forming a second layer of conductive material on the initial floating gate and at least a portion of an isolating region of the semiconductor device, and removing at least a portion of the second layer of conductive material to form at least one spacer that contacts the isolating region and the initial floating gate.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements in which;
FIGS. 1a-b depict different cross-sectional views of portions of a typical prior art semiconductor device having at least one memory cell;
FIGS. 2a-2e sequentially depict cross-sectional views of a portion of a semiconductor device during the formation of a plurality of memory cells, which results in at least one of the memory cells having a control gate arrangement with a damaged or cracked silicide layer;
FIG. 3 depicts a cross-sectional view of a portion of a semiconductor device having a plurality of memory cells having spacers in accordance with an embodiment of the present invention;
FIG. 4 depicts a cross-sectional view of a portion of a semiconductor device having a plurality of memory cells having an additional polysilicon layer, in accordance with an embodiment of the present invention; and
FIGS. 5a-b sequentially depict a cross-sectional view of a portion of a semiconductor device during the formation of a plurality of memory cells, having spacers arranged on the floating gates in accordance with an embodiment of the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit device during fabrication are not drawn to scale, but instead are drawn to illustrate the features of the present invention.
FIG. 2a represents a portion 10 of a semiconductor device as viewed from a cross-sectional perspective through the word line (similar to FIG. 1b). Portion 10, in FIG. 2a, depicts the formation of floating gates 16a-c from at least one layer of polysilicon. As shown, a conformal polysilicon layer 16 has been formed over substrate 12, tunnel oxide 15, and field oxides 14a-b that form isolating regions. Polysilicon layer 16 can be deposited, for example, using conventional deposition techniques, such as, chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) techniques. To pattern polysilicon layer 16 into floating gates 16a-16c (see FIG. 2b) a mask 18 has been formed and patterned on polysilicon layer 16. Mask 18, which is typically a lithographic mask, includes openings 20a-20b that selectively expose portions of the underlying polysilicon layer 16. The formation of floating gates 16a-16c includes anisotropic etching, such as reactive ion etching (RIE), or other anisotropic plasma etching processes that remove the exposed portions of polysilicon layer 16 through openings 20a-b, and stop on field oxides 14a-b.
In FIG. 2b, portion 10 has been etched and mask 18 has been stripped away, for example, using conventional stripping techniques, leaving floating gates 16a-c. The etching process creates spaces 22a and 22b. Spaces 22a-22b tend to be relatively narrow in width. For example, in sub-micron flash memories, spaces 22a and 22b can be between about 0.1 and 0.4 microns. Floating gates 16a-c are typically about 900 to 1,100 Angstroms thick. Consequently, the critical dimension of spaces 22a-b represents a significantly severe topology over which the subsequent layers are formed (e.g., interpoly dielectric layer 24, control gate 26 and silicide layer 28).
FIG. 2c depicts the portion 10 of FIG. 2b following deposition of interpoly dielectric layer 24 over floating gates 16a-c and within spaces 22a and 22b (see FIG. 2b). In certain preferred embodiments of the present invention, interpoly dielectric layer 24 is an ONO layer. An ONO layer can be formed, for example, by a three stage process in which a first film of silicon dioxide (e.g., about 50 Angstroms thick) is deposited or grown, followed by deposition of a second film of silicon nitride (e.g., about 80 Angstroms thick), and then a third film of silicon dioxide (e.g., about 40 Angstroms thick) is deposited or grown. The ONO layer provides a thin highly-insulative dielectric layer that separates the floating gate 16 from the control gate 26, as depicted in FIG. 2d.
In FIG. 2d, the portion 10 of FIG. 2c has been further processed to include a conformal layer of polysilicon that is patterned to form the control gate 26. This polysilicon can be deposited to a thickness of about 1,200 Angstroms using conventional deposition techniques, such as, CVD and PECVD techniques. A silicide layer 28, for example tungsten silicide (e.g., WSi2), is then formed on top of the polysilicon, as depicted in FIG. 2e. Although not visible from the word line cross-sectional perspective of FIG. 2d, the polysilicon is then selectively patterned using conventional polysilicon etching processes to form control gate 26.
Silicide layer 28 increases the conductivity of the control gate 26 and is designed to carry a significant portion of the programming current during the programming of the memory cells. It has been found, however, that silicide layer 28 can develop cracks, such as cracks 30a-30b in FIG. 2e, during subsequent thermal processing of portion 10. Cracks 30a-30b can extend partially through silicide layer 28, or in some cases can extend all the way through silicide layer 28 to control gate 26.
The cracking of silicide layer 28 appears to be caused by a combination of the severe topology of the spaces 22a-b (see FIG. 2b) and the subsequent thermal processing which typically is required to complete the manufacturing process. For example, subsequent thermal processes can include a high voltage anneal or thermal oxidation process associated with subsequent manufacturing steps. Thus, silicide layer 28, when subjected to the high temperatures of the subsequent thermal processes, tends to crack above the severe topology of the underlying layers. Cracks, such as, for example cracks 30a and 30b in FIG. 2e, tend to increase the resistance in the control gate 26 and degrade the performance of the flash memory and/or damage the semiconductor device.
It has been found that the cracking of silicide layer 28 is more prominent when the spaces 22a-b between the floating gates 16a-c are less than approximately 0.4 microns. In certain preferred embodiments of the present invention, spaces 22a-b are each approximately 0.26 microns wide, and the thickness of each of the floating gates 16a-c is approximately 900 to 1,100 Angstroms. The resulting topology has been found to cause a significant amount of cracking of silicide layer 28 during subsequent thermal processing. By way of example, in certain situations the cracking of suicide layer 28 has caused the resistance of a word line to increase by 100 times.
In accordance with the present invention, several new methods and arrangements have been developed to prevent the cracking of silicide layer 28. In accordance with one aspect of the present invention, the cracking of silicide layer 28 is substantially reduced, if not entirely eliminated, by reducing the severity of the underlying topology, and in particular, by altering the shapes of the overlying layers deposited over and above spaces 22a-b. This allows for increased step coverage when forming control gate 26 and silicide layer 28.
By way of example, FIG. 3 depicts one embodiment of the present invention in which the portion 10 has been modified during fabrication to include spacers 32 on top of interpoly dielectric layer 24. Spacers 32 are formed by depositing a thin layer (e.g., thickness of about 200 Å to about 500 Å of polysilicon over interpoly dielectric layer 24 and etching back the thin layer of polysilicon using a reactive ion etch or plasma etch to etch back portions of the thin layer of polysilicon. As a result of the etch back process, spacers 32 are formed, which alters the overall shape of the topology over spaces 22a and 22b such that subsequent deposition of control gate 26 and silicide layer 28 tend to be smoother in shape above spaces 22a-b. As depicted in FIG. 3, only relatively minor depressions 33a and 33b are formed by silicide layer 28 over spaces 22a-b. During subsequent thermal processing, minor depressions 33a and 33b are not, therefore, severe enough to initiate or lead to cracking of silicide layer 28.
However, in forming spacers 32 there will be contact between the interpoly dielectric layer 24 and the reactive ion or plasma etchant. In certain arrangements, such as when interpoly dielectric layer 24 is an ONO layer, the reactive ion or plasma etchant may damage or otherwise affect the ONO layer. For example, because the upper silicon dioxide film of the ONO layer is typically very thin (e.g., about 40 Angstroms thick), it can be inadvertently removed or substantially thinned such that the control gate 26, when formed, contacts the silicon nitride film of the ONO layer. This could, for example, result in reliability problems if the control gate 26 is poisoned by the nitride in the ONO layer, and/or if the ONO layer electrically breaks down. Thus, it is important to control the etch back process and to select an etching chemistry that provides a high selectivity between the polysilicon and the top film of silicon dioxide.
To avoid this problem altogether, in accordance with another embodiment of the present invention, the thin polysilicon layer (described above) is only partially etched away after it has been deposited over the interpolydielectric layer 24. Consequently, there is left a thin polysilicon layer 34 (e.g., thickness of about 100 Å to about 500 Å), that has been partially etched back and which also reduces the severity of the topology such that the subsequently formed control gate 26 and silicide layer 28 have only minor depressions 35a and 35b. As before, the minor depressions 35a and 35b are not severe enough to initiate or lead to cracking of silicide layer 28 during subsequent thermal processing.
In accordance with yet another embodiment of the present invention, the cracking of silicide layer 28, due to the severe topology and subsequent thermal processing, is solved by altering the shape of floating gates 16a-c, for example, by forming the floating gate 16a-c in a multistage process. An exemplary process is shown in FIGS. 5a-b.
In FIG. 5a, floating gates 16a-c have been formed by patterning an initial polysilicon layer. Next, an additional thin layer (e.g., 200-500 Angstroms thick) of polysilicon 36 has been conformally deposited over floating gates 16a-c and field oxides 14a-b, for example, using the same deposition process used to form the initial polysilicon layer from which floating gates 16a-c were patterned. The portion 10 in FIG. 5a is then subjected to a reactive ion etch or plasma etch process that is configured to etch back the additional polysilicon layer 36, thereby leaving behind additional polysilicon material, for example, in the form of spacers 38 that contact the sidewalls of the floating gates 16a-c, as shown in FIG. 5b.
Spacers 38 reduce the severity of the topology of the floating gates 16a-c such that subsequent deposition of the interpoly dielectric layer 24, and formation of control gate 26 and silicide layer 28 result in a smoother shape. Thus, for example, silicide layer 28 only includes minor depressions 37a and 37b, which are not severe enough to initiate or lead to cracking of silicide layer 28 during subsequent thermal processing.
Those skilled in the art will recognize that the additional polysilicon spacers (32 and 38) in the disclosed embodiments can be replaced, in certain embodiments, with other materials. For example, in certain embodiments, a dielectric material can be used instead of polysilicon. Further, the deposition and etching of the additional materials for spacers (32 and 38) and layer 34 can be selective; for example, a mask(s) can be used.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
| Patent | Priority | Assignee | Title |
| 10622370, | Dec 15 2006 | MONTEREY RESEARCH, LLC | System and method for manufacturing self-aligned STI with single poly |
| 6465302, | Dec 29 1999 | Hyundai Electronic Industries Co., Ltd. | Method of manufacturing a flash memory device |
| 6576949, | Aug 30 1999 | MONTEREY RESEARCH, LLC | Integrated circuit having optimized gate coupling capacitance |
| 6645796, | Nov 21 2001 | GOOGLE LLC | Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices |
| 6682978, | Aug 30 1999 | MONTEREY RESEARCH, LLC | Integrated circuit having increased gate coupling capacitance |
| 6891246, | Jun 26 2001 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method thereof |
| 7192831, | Jun 26 2001 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method thereof |
| 7439167, | Jun 26 2001 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method thereof |
| 7749836, | Jun 26 2001 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method thereof |
| 8222693, | Mar 10 2004 | NEXPERIA B V | Trench-gate transistors and their manufacture |
| 8551858, | Dec 15 2006 | Spansion LLC | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory |
| 8642441, | Dec 15 2006 | GLOBALFOUNDRIES U S INC | Self-aligned STI with single poly for manufacturing a flash memory device |
| 8642458, | Jun 13 2011 | Samsung Electronics Co., Ltd. | Method of fabricating nonvolatile memory device |
| 9276007, | Dec 15 2006 | MONTEREY RESEARCH, LLC | System and method for manufacturing self-aligned STI with single poly |
| Patent | Priority | Assignee | Title |
| 4980309, | Nov 30 1987 | Texas Instruments, Incorporated | Method of making high density EEPROM |
| 5021848, | Mar 13 1990 | Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof | |
| 5266509, | May 11 1990 | North American Philips Corporation | Fabrication method for a floating-gate field-effect transistor structure |
| 5497018, | Nov 14 1991 | Fujitsu Semiconductor Limited | Semiconductor memory device having a floating gate with improved insulation film quality |
| 5547884, | May 26 1992 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device having a common source region |
| 5576995, | May 30 1995 | SAMSUNG ELECTRONICS CO , LTD | Method for rewriting a flash memory |
| 5686332, | Nov 13 1995 | United Microelectronics Corporation | Process for fabricating flash memory devices |
| 5702964, | Oct 17 1995 | MAGNACHIP SEMICONDUCTOR LTD | Method for forming a semiconductor device having a floating gate |
| 5846861, | Oct 31 1995 | NEC Corporation | Method of manufacturing non-volatile semiconductor memory having erasing gate |
| EP511628A2, | |||
| EP841693A1, | |||
| JP3246974, | |||
| JP897306, | |||
| WO4323877, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Dec 18 1997 | Advanced Micro Devices, Inc. | (assignment on the face of the patent) | / | |||
| May 12 1998 | PARK, STEVEN KEETAI | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009285 | /0526 | |
| Jan 31 2007 | Advanced Micro Devices, INC | SPANSION INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019028 | /0623 | |
| Jan 31 2007 | SPANSION INC | Spansion LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019069 | /0028 | |
| May 10 2010 | Spansion LLC | BARCLAYS BANK PLC | SECURITY AGREEMENT | 024522 | /0338 | |
| May 10 2010 | SPANSION TECHNOLOGY INC | BARCLAYS BANK PLC | SECURITY AGREEMENT | 024522 | /0338 | |
| Mar 12 2015 | Cypress Semiconductor Corporation | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTERST | 058002 | /0470 | |
| Mar 12 2015 | BARCLAYS BANK PLC | SPANSION TECHNOLOGY LLC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 035201 | /0159 | |
| Mar 12 2015 | BARCLAYS BANK PLC | Spansion LLC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 035201 | /0159 | |
| Mar 12 2015 | Spansion LLC | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTERST | 058002 | /0470 | |
| Mar 12 2015 | Spansion LLC | MORGAN STANLEY SENIOR FUNDING, INC | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 035240 | /0429 | |
| Mar 12 2015 | Cypress Semiconductor Corporation | MORGAN STANLEY SENIOR FUNDING, INC | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 035240 | /0429 | |
| Jun 01 2015 | Spansion, LLC | Cypress Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036030 | /0682 | |
| Aug 11 2016 | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | Spansion LLC | PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS | 039708 | /0001 | |
| Aug 11 2016 | Cypress Semiconductor Corporation | MONTEREY RESEARCH, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 040911 | /0238 | |
| Aug 11 2016 | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | Cypress Semiconductor Corporation | PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS | 039708 | /0001 |
| Date | Maintenance Fee Events |
| Dec 27 2004 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Jan 19 2009 | REM: Maintenance Fee Reminder Mailed. |
| Apr 23 2009 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Apr 23 2009 | M1555: 7.5 yr surcharge - late pmt w/in 6 mo, Large Entity. |
| Jan 02 2013 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Jul 10 2004 | 4 years fee payment window open |
| Jan 10 2005 | 6 months grace period start (w surcharge) |
| Jul 10 2005 | patent expiry (for year 4) |
| Jul 10 2007 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Jul 10 2008 | 8 years fee payment window open |
| Jan 10 2009 | 6 months grace period start (w surcharge) |
| Jul 10 2009 | patent expiry (for year 8) |
| Jul 10 2011 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Jul 10 2012 | 12 years fee payment window open |
| Jan 10 2013 | 6 months grace period start (w surcharge) |
| Jul 10 2013 | patent expiry (for year 12) |
| Jul 10 2015 | 2 years to revive unintentionally abandoned end. (for year 12) |