A format conversion apparatus for a digital tv includes a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data and an output image size data. A format conversion coefficient generating part generates a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part. A synchronizing signal generating part generates vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part. A format conversion part performs format conversion of image input per block according to the format conversion coefficient and the vertical and horizontal synchronizing signals. Vertical and horizontal format conversion of an input image is performed after dividing the image into a plurality of blocks so that buffer memory and bandwidth requirements for performing the format conversion are reduced simultaneously, while easily increasing a number of taps of a vertical filter. This prevents degradation of resolution generated when reducing a size of an image and realizes a high resolution with simple hardware.
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1. An apparatus for converting a format for a digital tv, comprising:
a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data and an output image size data, and generating a control signal for performing format conversion per the divided blocks; a format conversion coefficient generating part for generating a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part; a synchronizing signal generating part for generating vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part; and a format conversion part for performing format conversion per block according to the format conversion coefficient generated from the format conversion coefficient generating part and the vertical and horizontal synchronizing signals generated from the synchronizing signal generating part, wherein the blocks divided in the block division and control signal generating part are overlapped with neighboring blocks in part.
12. A format conversion apparatus for a digital tv, comprising:
a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data, an output image size data and input and output size data of each block, and generating a control signal for performing format conversion per the divided blocks; a format conversion coefficient generating part for generating a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part; a synchronizing signal generating part for generating vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part; and a format conversion part for performing format conversion per block according to the format conversion coefficient generated from the format conversion coefficient generating part and the vertical and horizontal synchronizing signals generated from the synchronizing signal generating part, wherein the blocks divided in the block division and control signal generating part are overlapped with neighboring blocks in part.
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a memory buffer Dart including a plurality of buffers for temporarily processing images per block unit; a vertical format conversion part for converting an image signal output from the memory buffer part in the vertical direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a vertical synchronizing signal generated from the synchronizing signal generating part; and a horizontal format conversion part for converting can image signal output from the vertical format conversion part in the horizontal direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a horizontal synchronizing signal generated from the synchronizing signal generating part.
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a memory buffer part including a plurality of buffers for temporarily storing images input per block unit; a vertical format conversion part for converting an image signal output from the memory buffer part in the vertical direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a vertical synchronizing signal generated from the synchronizing signal generating part; and a horizontal format conversion part for converting an image signal output from the vertical format conversion part in the horizontal direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a horizontal synchronizing signal generated from the synchronizing signal generating part.
18. An apparatus for converting a format for
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1. Field of the Invention
The present invention relates to a digital television, and more particularly to, an apparatus for converting a format for a digital television.
2. Description of the Related Art
According to the introduction of digital TVs and various display apparatuses, more various kinds of images become possible to be input and output in comparison with an existing analogue TVs. In order to convert input images of various sizes into output images of different sizes, a format conversion apparatus is essential and in order to obtain a high resolution output, proper filtering should be performed in vertical and horizontal directions, according to a ratio of input and output images.
Now, related arts will be described with reference to appended drawings.
In
The vertical format conversion element 3 converts the vertical components included in the image signals which are output from the first and second line memories 1, 2 into an output image size and outputs to the horizontal filter 4.
The horizontal filter 4 filters the horizontal components included in the image signals which are converted and output by the vertical format conversion element 3 and outputs to the horizontal format conversion element 5. That is, the horizontal filter 4 limits the bandwidth of the input image for preventing aliasing possibly generated when reducing the input image in the horizontal direction. The image signals, which are filtered in the horizontal direction, are stored in the memory 6 after the horizontal format conversion by the horizontal format conversion element 5 in accordance with the output size.
At this time, if the line memories as shown in
If buffers are adopted to avoid this disadvantage, even though the size of the hardware may be reduced but a relatively larger memory bandwidth is required. That is, in case that buffers are adopted, vertical filters of a plurality of taps should be used for obtaining a high resolution and the memory bandwidth is greatly increased. Therefore, the vertical filtering is imitatively used in an expensive system. Finally, low price systems, which can not adopt the vertical filtering, can not obtain an image quality as required.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide an apparatus for converting a format of digital TVs in which input images are divided into a plurality of blocks and the respective blocks are converted in vertical and horizontal directions.
To achieve at least these and other advantages in whole or in parts there is provided an apparatus for converting a format for a digital TV, comprising, a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data and an output image size data, and generating a control signal for performing format conversion per the divided blocks; a format conversion coefficient generating part for generating a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part; a synchronizing signal generating part for generating vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part; and a format conversion part for performing format conversion per block according to the format conversion coefficient generated from the format conversion coefficient generating part and the vertical and horizontal synchronizing signals generated from the synchronizing signal generating part.
The blocks divided in the block division and control signal generating part is overlapped with other neighboring blocks in part.
The apparatus for converting a format for a digital TV further comprises a read/write address generating part for generating a read address and a write address according to a control signal output from the block division and control signal generating part, and a memory for performing read/write of an input image according to the read address and the write address, wherein blocks read in the format conversion part according to the read address is read by overlapping with neighboring blocks in part, and blocks which are written after the format conversion are written without overlapping with neighboring blocks according to the write address.
The block division and control signal generating part determines a block size when dividing an input image into a plurality of blocks according to a memory bandwidth.
The block division and control signal generating part determines a horizontal direction size of the respective blocks to be slightly smaller than a pixel number able to be brought by a signal memory read operation.
The format conversion coefficient generating part generates format conversion coefficients in such a manner that a format conversion coefficient at a starting point of the respective blocks which are divided from an input image into a plurality of blocks under the control of the block division and control signal generating part is in conformity with a format conversion coefficient at a point when the input image is processed by a single block.
The synchronizing signal generating part generates vertical and horizontal synchronizing signals equal or different for the respective blocks, which are divided under the control of the block division, and control signal generating part.
The format conversion part comprises a memory buffer part including a plurality of buffers for temporarily storing images input per block unit, a vertical format conversion part for converting an image signal output from the memory buffer part in the vertical direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a vertical synchronizing signal generated from the synchronizing signal generating part, and a horizontal format conversion part for converting an image signal output from the vertical format conversion part in the horizontal direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a horizontal synchronizing signal generated from the synchronizing signal generating part.
The block division and control signal generating part determines a block size according to a size of the memory buffer when dividing the input image into a plurality of blocks.
The plurality of buffers in the memory buffer part is disposed in parallel, and a number of the buffers is determined by a number of taps of the vertical filter at a rear end.
The block division and control signal generating part divides a horizontal direction size of a block to be smaller than a pixel number stored in a single buffer when dividing the input image into a plurality of blocks.
The apparatus for converting a format for a digital TV includes a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data, an output image size data and an input and output size data of each block, and generating a control signal for performing format conversion per the divided blocks, a format conversion coefficient generating part for generating a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part, a synchronizing signal generating part for generating vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part, and a format conversion part for performing format conversion per block according to the format conversion coefficient generated from the format conversion coefficient generating part and the vertical and horizontal synchronizing signals generated from the synchronizing signal generating part.
The apparatus for converting a format of a digital TV further includes a read/write address generating part for generating a read address and a write address according to a control signal output from the block division and control signal generating part, and a memory for performing read/write of an input image according to the read address and the write address, wherein blocks read in the format conversion part according to the read address is read by overlapping with neighboring blocks in part, and blocks which are written after the format conversion are written without overlapping with neighboring blocks according to the write address.
The blocks divided in the block division and control signal generating part are overlapped with other neighboring blocks in part.
The format conversion coefficient generating part generates format conversion coefficients differently for the respective blocks which are divided under the block division and control signal generating part for performing the format conversion of blocks with different input and output sizes.
The synchronizing signal generating part generates vertical and horizontal synchronizing signals differently for the respective blocks which are divided under the control of the block division and control signal generating part for performing the format conversion of blocks with different input and output sizes.
The format conversion part includes a memory buffer part including a plurality of buffers for temporarily storing images input per block unit, a vertical format conversion part for converting an image signal output from the memory buffer part in the vertical direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a vertical synchronizing signal generated from the synchronizing signal generating part, and a horizontal format conversion part for converting an image signal output from the vertical format conversion part in the horizontal direction according to a format conversion coefficient generated from the format conversion coefficient generating part and a horizontal synchronizing signal generated from the synchronizing signal generating part.
A vertical filter and a horizontal filter are provided respectively at a front end part of the vertical format conversion part and a front end part of the horizontal conversion part for limiting bandwidth of an input image.
According to the present invention, input images are divided into a plurality of blocks and the blocks are converted vertically and horizontally in the format by using the buffers like the line memories, so that the buffer memory and the bandwidth required for the format conversion are simultaneously reduced greatly, thereby preventing degradation of resolution generated when reducing a size of an image and realizing a high resolution with simple hardware.
The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:
The format conversion part 106 includes a vertical filter 106a for filtering vertical components included in the input images per block with a predetermined bandwidth, a vertical format converter 106b for converting the format of the image signal filtered in the vertical filter 106a in a vertical direction according to a format conversion coefficient generated in the format conversion coefficient generating part 102 and a vertical synchronizing signal generated in the synchronizing signal generating part 103, a horizontal filter 106c for filtering horizontal components included in the image signal, which is converted in the vertical format by the vertical format converter 106b, with a predetermined bandwidth, and a horizontal format converter 106d for converting the format of the image signal filtered in the horizontal filter 106a in the horizontal direction according to a format conversion coefficient generated in the format conversion coefficient generating part 102 and a horizontal synchronizing signal generated in the synchronizing signal generating part 103.
Wherein, the vertical filter 106a or the horizontal filter 106c may alternatively be used or unused, but both filters are used in this embodiment of the present invention.
That is, the vertical filter 106a or the horizontal filter 106c are used for preventing aliasing, possibly generated in output images, by limiting bandwidth of the input images when reducing the input images in the vertical or horizontal direction.
According to the present invention constructed as above, the block division and control signal generation part 101 outputs a control signal for dividing the input images into a plurality of blocks according to the input image size data and the output image size data.
At this time, the blocks divided in the block division and control signal generating part 101 are overlapped with other neighboring blocks in part. For example, with blocks "A" and "D" as shown in
That is, an amount of the input image data is necessary more than an amount of the output image data for filtering and format conversion. In particular, as for the horizontal and vertical format conversion, data of left and right parts of the image are more required so that the block diagram and control signal generating part 101 outputs a control signal to overlap neighboring images more or less as shown in
At this time, output image blocks, of which the format is converted, are not required to overlap as shown in
When dividing the input images with a plurality of blocks, the block division and control signal generating part 101 determines a size of blocks according to a memory buffer size, or a necessary memory bandwidth. If the size of the block becomes larger, the memory buffer size should be enlarged but the memory bandwidth is increased smaller than in case of the line memory. On the other hand, if the block size becomes smaller, the memory buffer size is preferably reduced, but the memory bandwidth is relatively largely increased. In general, a minimum memory amount and a minimum memory bandwidth may be obtained by determining a horizontal size of the block to be slightly smaller than a pixel number obtained by a memory read operation.
The memory buffer may be included in the vertical filter 106a of the format conversion part 106, as shown in
Then, the read address generating part 105 generates a read address to the memory 107, according to the determined block size and a processing sequence. Then, the image signals stored in the memory 107 are read by a block unit, according to the read address to be inputted to the vertical filter 106a of the format conversion part 106.
The divided blocks may be processed in various sequences as shown in
The FC coefficient generating part 102 generates FC coefficients required for the vertical and horizontal format conversion per the divided block. That is, as shown in
Particularly, the FC coefficient generating part 102 generates FC coefficients required around borders of the divided areas. Since a single input image is divided into a plurality of blocks, an FC coefficient at boundary points of the respective blocks should be in conformity with an FC coefficient at points when the input image is processed by a single block. By doing so, a format conversion result with a single block becomes equal to a format conversion result with a plurality of blocks in a single input image. 581 The synchronizing signal generating part 103 generates vertical and horizontal signals per the divided block under the control of the block division and control signal generating part 101, wherein the format conversion is performed by the respective divided blocks, a length of the vertical and the horizontal synchronizing signals required for the respective divided blocks may be different. Therefore, the synchronizing signal generating part 103 generates vertical and horizontal synchronizing signals for the respective divided blocks in consideration of the difference.
On the other hand, the format conversion part 106 performs the format conversion of images input by the block unit according to the FC coefficient generated in the FC coefficient generating part 102 and the vertical and horizontal synchronizing signals output from the synchronizing signal generating part 103. Then, the memory 107 stores the respective blocks not to be overlapped, according to the write address generated from the write address generating part 104, as shown in
At this time, the format conversion part 106 may alternatively use the vertical filter 106a of the format conversion part. However, in the case of the format conversion via the block division, as an example, if the block "D" is processed after the block "A" as shown in
If the vertical filter 106a is used and the number of the vertical filter tap 106a is five, then the memory buffer may include a first memory buffer 201 and a second memory buffer 202, each having five buffers, as shown in FIG. 5. That is, the number of buffers included in the first and second memory buffers 201 and 202 is different depending on the tap number of the vertical filter 106a.
In order to optimize the memory bandwidth, an image in a same position in the memory 107 should be prevented from being read repeatedly. Therefore, as shown in
That is, the vertical filter 106a in the format conversion part 106 prevents the aliasing, which may be generated in the output image, by limiting the bandwidth of the images output from the first and second memory buffers 201 and 202, and the output from the vertical filter 106a is input to the vertical format converter 106b.
The vertical format converter 106b converts the vertical format of the image signal, which is filtered in the vertical filter 106a, according to the FC coefficient generated in the FC coefficient generating part 102 and the vertical synchronizing signal generated from the synchronizing signal generating part 103 and outputs to the horizontal filter 106c.
The horizontal filter 106c prevents the aliasing by limiting the bandwidth of images to be output from the vertical format converter 106b before the horizontal format conversion. The horizontal format converter 106d converts the horizontal format of the image signal, which is filtered in the horizontal filter 106c, according to the FC coefficient generated from the FC coefficient generating part 102 and the horizontal synchronizing signal generated in the synchronizing signal generating part 103 and outputs to the memory 107.
That is, the format conversion part 106 performs most effective format conversion per the blocks divided in the block division and control signal generating part 101 according to the FC coefficients generated in the FC coefficient generating part 102 and the vertical and horizontal synchronizing signals generated in the synchronizing signal generating part 103.
By doing so, a same image is read once more only in boundary parts and the required amount of the memory bandwidth is similar to the line memories. Further, the required amount of hardware is greatly reduced by using buffers instead of the line memories. Even though a control part for the block division is added and accordingly the hardware is added therefor, such increase of the hardware is negligible in consideration of the reduction of the hardware due to the substitution of the line memories to the buffers.
On the other hand, as shown in
For example, in the case that an input image having a screen ratio of 4:3 is converted in its format to an output image having a screen ratio of 16:9, it is possible to linearly expand the horizontal components of the input image after assigning the input and output sizes per the divided block equally. As shown in
The block division and control signal generating part 101 performs the block division and generation of control signals by receiving input image and block size data and output image and block size data of both input and output images as shown in FIG. 6. The operations are similar to those of FIG. 2. That is, the FC coefficient generating part 102 generates different FC coefficients per the divided block according to a control signal of the block division and control signal generating part 101.
The synchronizing signal generating part 103 generates different vertical and horizontal signals per the divided block according to a control signal of the block division and control signal generating part 101. The format conversion part 106 performs the format conversion of the images input by the block unit according to the FC coefficient and the vertical and horizontal synchronizing signals, thereby the images of which screen ratios are different are output as shown in
As described hereinabove, the apparatus for converting a format for a digital TV according to the present invention has several effects.
First, buffer memory and bandwidth required for the format conversion may be reduced simultaneously by performing the vertical and horizontal format conversions after dividing input images into a plurality of blocks. Accordingly, the tap number of the vertical filter may be simply increased and, as a result, the degradation of resolution generated when reducing the image size is prevented, so that a high resolution screen may be realized with a simple hardware construction.
Second, a screen ratio conversion system for converting an input image having a screen ratio of 4:3 to an output image having a screen ratio of 16:9 or vice versa may be simply constructed without any additional hardware.
The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims . Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.
Patent | Priority | Assignee | Title |
10063808, | Oct 08 2008 | Samsung Electronics Co., Ltd. | Apparatus and method for ultra-high resolution video processing |
6667773, | Oct 12 1999 | LG Electronics Inc. | Apparatus and method for format converting video |
7006112, | Mar 15 2002 | VIA Technologies, Inc. | Method for scaling image frame |
7030932, | Jul 18 2000 | LG Electronics Inc. | Apparatus and method for converting multi-source input images |
7050113, | Mar 26 2002 | International Business Machines Corporation | Digital video data scaler and method |
7209260, | Jul 19 1999 | Sharp Kabushiki Kaisha | Image processing apparatus |
7349032, | Sep 17 2004 | SOCIONEXT INC | Circuit to resize and enlarge an image signal and resizing and enlargement method for an image signal |
7375764, | May 17 2002 | MAGNOLIA LICENSING LLC | Method and system for VFC memory management |
7388620, | Oct 23 2003 | Saturn Licensing LLC | Method and system for pan-scan using motion vectors presentation |
7421150, | Jan 17 2004 | LG Electronics Inc. | Coordinate conversion apparatus and method |
7551803, | Oct 15 2003 | STMICROELECTRONICS, S A | Image adapter with tilewise image processing, and method using such an adapter |
7583851, | Dec 28 2004 | SOCIONEXT INC | Apparatus and method for processing an image |
7813243, | Jan 11 2003 | LG Electronics Inc. | Optical disc of write once type, method, and apparatus for managing defect information on the optical disc |
7925119, | Oct 15 2003 | STMicroelectronics S.A. | Image adapter with tilewise image processing, and method using such an adapter |
8072853, | Jan 27 2003 | LG Electronics Inc. | Optical disc of write once type, method, and apparatus for managing defect information on the optical disc |
8520147, | Jun 16 2011 | Marseille Networks, Inc. | System for segmented video data processing |
8666192, | Oct 08 2008 | Samsung Electronics Co., Ltd. | Apparatus and method for ultra-high resolution video processing |
8938133, | Oct 18 2010 | MEGACHIPS CORPORATION | Image resizing apparatus and method that interpolates image blocks with abuttal regions |
9030609, | Jun 16 2011 | Marseille Networks, Inc. | Segmented video data processing |
9143804, | Oct 29 2009 | NEC Corporation | Method and apparatus for parallel H.264 in-loop de-blocking filter implementation |
9471843, | Oct 08 2008 | Samsung Electronics Co., Ltd. | Apparatus and method for ultra-high resolution video processing |
Patent | Priority | Assignee | Title |
5469223, | Oct 13 1993 | CREATIVE TECHNOLOGY LTD | Shared line buffer architecture for a video processing circuit |
5475442, | Sep 07 1992 | Kabushiki Kaisha Toshiba | Television signal processor for processing any of a plurality of different types of television signals |
5790714, | Nov 01 1994 | IBM Corporation | System and method for scaling video |
5825424, | Jun 19 1996 | Thomson Consumer Electronics, Inc | MPEG system which decompresses and recompresses image data before storing image data in a memory and in accordance with a resolution of a display device |
6097438, | Jun 06 1997 | Pioneer Electronic Corporation | System for processing a picture data signal for an image display device |
6151425, | Apr 14 1995 | PANASONIC LIQUID CRYSTAL DISPLAY CO , LTD | Resolution conversion system and method |
6226039, | Dec 24 1996 | LG Electronics Inc | Automatic aspect ratio converting apparatus for television receiver |
6256068, | May 08 1996 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Image data format conversion apparatus |
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