A method of making a semiconductor device is described. That method comprises forming a copper containing layer on a substrate, introducing a void nucleation site into the copper containing layer, and forming a via that is located a distance removed from where the void nucleation site was introduced into the copper containing layer.
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1. A method of making a semiconductor device comprising:
forming a copper containing layer on a substrate; introducing a void nucleation site into the copper containing layer; and forming a via that is located a distance removed from where the void nucleation site was introduced into the copper containing layer.
18. A method of making a semiconductor device comprising:
forming a copper containing layer on a substrate; introducing a void nucleation site into the copper containing layer; forming a dielectric layer on the copper containing layer; and etching a via through the dielectric layer such that the via is located a distance removed from where the void nucleation site was introduced into the copper containing layer.
14. A method of making a semiconductor device comprising:
forming a copper containing layer on a substrate; masking a first part of the copper containing layer; introducing a void nucleation site into a second part of the copper containing layer; forming a via that contacts the copper containing layer at a location which is removed from the second part of the copper containing layer; and generating a void in the copper containing layer where the void nucleation site was introduced into the copper containing layer.
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The present invention relates to a method of making semiconductor devices, in particular, devices that include copper damascene interconnects.
When making advanced semiconductor devices, copper interconnects may offer a number of advantages over those made from aluminum. For that reason, copper has become the material of choice for making such devices' interconnects. As device dimensions shrink so does conductor width--leading to higher resistance and current density. Increasing current density can increase the rate at which copper atoms are displaced when current passes through a copper conductor. Such electromigration can cause vacancies, which may lead to voids, e.g., at the interface between the copper conductor and a barrier layer that may be formed on the conductor. If a void grows to a size that creates metal separation, e.g., near a via that contacts the conductor, it may cause an open-circuit failure.
One way to prevent electromigration from causing interconnect failure is to limit the amount of current that passes through the conductor. That solution to the electromigration problem is impractical, however, because devices will operate at progressively higher currents, even as they continue to shrink. As an alternative, reliability can be enhanced by doping the interconnect--as adding dopants to the conductor can reduce the rate at which copper diffuses. Doping the interconnect, however, can raise its resistance significantly. To reduce RC delay that is associated with high resistance, it may be necessary to limit dopant concentration--or dispense with doping altogether, e.g., when forming high speed conductors. When low level doping is required to limit conductor resistance, the electromigration mitigating impact that such doping provides is reduced.
Accordingly, there is a need for an improved process for making a semiconductor device that includes copper interconnects. There is a need for such a process that reduces electromigration without significantly raising conductor resistance. The method of the present invention provides such a process.
A method for making a semiconductor device is described. That method comprises forming a copper containing layer on a substrate, introducing a void nucleation site into the copper containing layer, and forming a via that is located a distance removed from where the void nucleation site was introduced into the copper containing layer. The void nucleation site preferably is introduced into the copper containing layer before a barrier layer is formed on it, and may be generated in various ways--several of which will be described in more detail below. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.
At this stage of the process, copper containing layer 101 may be undoped, or lightly doped with an electromigration retarding amount of an element that will not significantly increase layer 101's resistance. Appropriate dopants that may be used are well known to those skilled in the art. The optimum dopant concentration will depend upon layer 101's dimensions and other characteristics, the type of dopant used, and the function layer 101 will perform.
In this embodiment of the present invention, a photoresist layer may be deposited and patterned to form patterned photoresist layer 110, which masks a first part of copper containing layer 101 and exposes a second part of copper containing layer 101. As an alternative to forming masking layer 110 from photoresist, such a masking layer may be made from silicon nitride or silicon carbide. To form a hard mask from such a material, a relatively thin layer of silicon nitride or silicon carbide may be deposited on layer 101, then etched to expose part of the copper containing layer, using conventional techniques. Void nucleation site 111 will be introduced into layer 101 to induce void formation in that layer at that site. Void nucleation site 111 may be created by any process that promotes void formation--without adversely affecting device performance.
As
Alternatively, void nucleation site 211 may be introduced into copper containing layer 201 by removing part of that layer using a sputtering process-as illustrated in FIG. 2. In a preferred embodiment, after covering the bulk of layer 201 with mask 210, a conventional sputtering process is used to bombard the exposed part of layer 201 with an inert gas, e.g., argon. This technique may, in itself, create a void that performs an electromigration retardation function. In an embodiment that employs sputtering to introduce such a defect, a void that such a process creates is considered to be a void nucleation site.
As an alternative to implanting ions, or relying on sputtering, to create the void nucleation site, that site may be introduced into the copper containing layer by excluding part of that layer from process steps that promote adhesion between it and a barrier layer to be formed on the copper containing layer. In the embodiment that
After masking shunt layer 330, using either photoresist or a hard mask, the exposed part of that layer is removed to define a void nucleation site. Conventional process steps may be used to form the
After the void nucleation site is introduced into the copper containing layer, a barrier layer 502 may be formed on layer 501, as shown in FIG. 5. (In this embodiment, a shunt layer was not formed, nor was a hard mask retained, prior to forming the barrier layer.) Barrier layer 502 may serve to minimize diffusion from copper containing layer 501 into dielectric layer 503, which will be formed on barrier layer 502. Barrier layer 502 may also act as an etch stop to prevent a subsequent via etch step from exposing copper containing layer 501 to materials used to clean the via.
Barrier layer 502 preferably is made from silicon nitride, silicon oxynitride or silicon carbide, but may be made from other materials. When photoresist is used to mask layer 501 prior to creating a void nucleation site, it must be removed prior to forming the barrier layer. When a hard mask is used to enable creation of a void nucleation site, it may be removed prior to forming barrier layer 502 or instead retained.
Dielectric layer 503 may comprise silicon dioxide, or a material with a lower dielectric constant, e.g., SiOF, carbon doped oxide, or a porous oxide. Other low k materials that may be used to make dielectric layer 503 include organic polymers such as a polyimide, parylene, polyarylether, polynaphthalene, or polyquinoline. In this embodiment of the present invention, via 504 is etched through dielectric layer 503 and part of barrier layer 502 to expose part of copper containing layer 501.
When the finished device is subject to substantial high current operation, void 520 may form at the void nucleation site. (In some embodiments of the present invention, e.g., those that employ sputtering to remove part of the copper containing layer, void 520 may be present prior to device operation.) When current flows from left to right in the
Electromigration induced voiding in copper interconnects occurs primarily near the cathode via at the copper/barrier layer interface. The process of the present invention improves interconnect electromigration by deliberately introducing a defect into the copper containing layer, which will induce a void, then forming the via at a distance that is removed from where the defect was created. Intentionally forming a void "downstream" from the via may retard electromigration that may otherwise have occurred "upstream" from that void. This may help prevent an open-circuit failure, which might otherwise have occurred due to void nucleation near the via. Unlike current methods, which rely on relatively substantial doping of the copper line to reduce electromigration, the method of the present invention may serve to reduce electromigration without significantly increasing conductor resistance.
Although the foregoing description has specified certain steps and materials that may be used in the above described method for making a semiconductor device with a copper containing layer that has improved electromigration reliability, those skilled in the art will appreciate that many modifications and substitutions maybe made. It is intended that any such modification, alteration, substitution and/or addition to the specific embodiments described above be considered to fall within the spirit and scope of the invention as defined by the appended claims.
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