A direct digital synthesizer (DDS) generates a sinusoidal waveform having a variable frequency within a time duration. The DDS has a memory for storing pre-computed digital values defining the sinusoidal waveform, a barrel shifter for reading the contents of the memory and for presenting the digital values from the memory to a multiplexer at a first rate determined by a first clock. The multiplexer is connected to a digital to analog converter. The digital to analog converter converts the digital values presented by the multiplexer to the analog output at a second rate determined by a second clock. The barrel shifter shifts the digital values using a plurality of pipelines and n-bit wrap-around registers. pre-computed digital values defining the sinusoidal waveform are stored within a memory, then routed using a bus exchange switch to the barrel shifter.
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1. A direct digital synthesizer for generating an analog output, said analog output is a sinusoidal waveform having a variable frequency within a time duration, comprising:
a memory for storing pre-computed digital values defining said sinusoidal waveform; a barrel shifter for reading contents of said memory and for presenting said digital values from said memory to an input of a multiplexer at a first rate determined by a first clock; said multiplexer having an output connected to a digital to analog converter, said digital to analog converter converting said digital values presented by said multiplexer to said analog output at a second rate determined by a second clock.
8. A method for generating an analog output using a direct digital synthesizer said analog output is a sinusoidal waveform having a variable frequency within a time duration, comprising the steps of:
loading into a memory pre-computed digital values defining said sinusoidal waveform; reading from said memory said pre-computed digital values into a barrel shifter; rotating said pre-computed digital values within said barrel shifter to obtain rotated values; presenting said rotated values from said memory to an input of a multiplexer at a first rate determined by a first clock; multiplexing said rotated values using a multiplexer having an output connected to a digital to analog converter, said digital to analog converter converting said digital values presented by said multiplexer to said analog output at a second rate determined by a second clock.
3. A direct digital synthesizer of
4. A direct digital synthesizer of
5. A direct digital synthesizer of
6. A direct digital synthesizer of
7. A direct digital synthesizer of
9. A method as described in
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This invention is in the field of direct digital signal synthesizers generating periodic signals at microwave frequencies.
Direct digital synthesizers (DDS) use a plurality of digital data processing blocks to generate a frequency and phase tunable output referenced to a fixed frequency clock source. Generally, the fixed frequency clock source is divided down within the DDS architecture by a scaling factor specified using a digital tuning word. This digital tuning word is typically 24 to 48 bits long, allowing a wide degree of tuning resolution with respect to the fixed frequency clock source.
Another aspect of DDS operation is that in addition to the output frequency, the phase of the output can also be specified using a digital input. Thus, the parameters of the output from a DDS is not only frequency, but also phase, referenced to the clock source.
Typical DDS structures can generate an output signal specified in terms of both frequency and phase upon digital command for applications such as local oscillators quadrature (I/Q) synthesizers, GMSK and ramped FSK, and the like.
It is desirable to make frequency/phase changes quickly, even within one cycle of the waveform. In general, the constraints precluding high output frequency or rapid phase change come from various device limitations. One example of a device limitation is that the clock source frequency required for fast, sub-cycle change may be too high for devices created using existing semiconductor processes. Currently, high speed operation requires that the digital circuitry generating the output waveform switch at full clock speed frequencies. Such high speed operation uses substantial amounts of power, as well as imposing the need for high quality transistors having high frequency operating capability (high unity current gain transition frequency, fT). High power consumption, coupled to high cost process for high ft, structures, burdens state of the art systems with disadvantageous economic constraints.
Some configurations require the use of high speed random access memories to store digital bits required for conversion. Reducing the speed of these memories is an objective of the invention.
A direct digital synthesizer (DDS) is described for generating an analog output. The analog output is a sinusoidal waveform having a a variable frequency within a time duration.
The DDS comprises:
a memory (402, 404, 406, 335) for storing pre-computed digital values defining said sinusoidal waveform;
a barrel shifter (311, 408, 410, 412) for reading contents of said memory (402, 404, 406, 335) for presenting said digital values from said memory to an input of a multiplexer (321, 323, 325, 327, 416, 418, 420) at a first rate determined by a a first clock (434, 333).
The multiplexer (416, 418, 420) has an output connected to a Digital to Analog converter (329, 432). The Digital to Analog converter converts the digital values presented by the multiplexer (416, 418, 420) to the analog output at a second rate determined by a second clock (331).
The barrel shifter shifts the digital values using a plurality of pipelines and n-bit wrap-around registers (436).
The pre-computed digital values defining said sinusoidal waveform are pre-computed and stored within a storage means (memory) during said duration. Some of said pre-computed digital values are pre-computed using a numerically controlled oscillator (315). Others of said pre-computed digital values are pre-computed using a simulation of a ΔΣ modulator (337).
Pre-computed digital values are routed from a storage means (335) using a bus exchange switch (309) to the barrel shifter (311). Other values are computed within NCO 315, routed through Bus exchange switch 309 to either a storage location (RAM 335) or barrel shifter 311.
This invention details the use of a novel DDS structure using a barrel shifter coupled to a multiplexer structure within a specially programmed FPGA to reduce the internal operating frequency of DDS storage. This reduces the need for high quality, high ft switching transistors forming the DDS memory, as well as reducing the power consumption related thereto. For ΔΣ DDS, the invention uses a 3 bit DAC instead of a prior art typical 1 bit DAC, while minimizing increases in the size, and speed of the internal RAM. In prior art applications, digital output waveforms presented to the DAC are pre-computed in external, system processors, and downloaded into RAM. Because digital data has to be read out directly from RAM to the DAC for waveform synthesis, a fast RAM, typically without wait states, is used. The speed of the RAM places a limit to conversion speed in the prior art.
Shown in
Phase accumulator 101 receives as an input a digital tuning word 109 specifying the output frequency to be generated as a fraction of the reference clock frequency. The operation of a prior art digital signal processor is detailed in A Technical Tutorial on Digital Signal Synthesis published by Analog Devices and incorporated herein in its entirety by reference.
Amplitude/Sine wave converter 103 converts a truncated version of the phase accumulator output from phase accumulator 101 by adding non-linearities descriptive of, for example, a sine wave. As shown, the phase accumulator 101, as well as Amplitude/sine conversion converter 103 operate at the frequency of reference clock 105.
The structure of
The structure shown in
The direct digital synthesizer of this invention is for generating an analog output, a sinusoidal waveform having a a variable frequency within a time duration. Considering FIG. 3 and
a 3 bit numerically controlled oscillator (NCO) 315 for computing some of the required digital values defining the output waveform;
a memory (402, 404, 406, 335) for storing pre-computed digital values defining the output sinusoidal waveform;
a bus exchange switch 309 for steering digital values from and to NCO 315, storage 335, and connecting to barrel shifter 311;
barrel shifters (311, 408, 410, 412) adapted to reading contents of memory (402, 404, 406 or 335) and for presenting the digital values from the memory in sequence to an input of multiplexers (323, 325, 327, 416, 418, 420) at a first rate determined by a a first clock (428, 426, 424, 422, 333). The multiplexers (416, 418, 420) have outputs connected to a Digital to Analog converter (D/A) (329, 432). D/A (329, 432) converts the digital values presented by the multiplexing mechanism (416, 418, 420, 26323, 325, 327) to the analog output at a second rate determined by a second clock (331, 430). The first clock rate is lower than the second clock rate. In this example, the first clock (430, 331) is divided down by a factor of two in dividers 428, 426, 424 and 422, for a total reduction factor of 16. The reduced rate clock is delivered to various stages within 16:1 multiplexers 416, 418, 420, as shown in FIG. 7.
Barrel shifter 311, having a plurality of 16 bit barrel shifters 408, 410, 412 in this example, shifts the digital values from memory 335 (402, 404 and 406 in
Pre-computed digital values defining the sinusoidal waveform are stored within memory 335. Some of the pre-computed digital values are generated using an accumulator based numerically controlled oscillator 315. Others are pre-computed using a simulation of a ΔΣ modulator 337 using an Accumulator based NCO image from NCO 315 in FPGA 347, definitions for a ΔΣ modulator 343 and phase codes 345. A MATLAB Software Multi Bit ΔΣ Modulator 343 within 337 generates, for example, the Least Significant Bit (LSB). (For more bits, the same software can generate the necessary bits.) For this example, a first order Feedback Quantizer will limit the error to within 1 bit. As in the prior art, a 1-Bit, ΔΣ phase coding may optionally phase modulate the output of the ΔΣ modulator. This "modulated data" is either subtracted as shown in subtract 602, in
Only the LSBs are picked off, per
Timing and control 321 supplies addressing to RAM 335 and barrel shifter 311. The barrel shifter is required for random access across the 16 bit bits supplied to 16:1 multiplexers 323, 325, and 327 because the multiplexers are unable to make random access transitions across the 10 bit wide input (3 bits deep, 323, 325, 327). Barrel shifter 311 makes up for random access capability of the 16:1 Multiplexers by rotating the bits as shown in FIG. 5 and shifting their order as shown in FIG. 7.
In
The NCO parameters computed by NCO 315 are either transferred from pole 305 to pole 303 and barrel shifter 311, or passed to pole 301 for storage in memory 335.
The LSB of modulation data from Software Compute 337, as described in
The method of the invention for generating an analog output using a direct digital synthesizer comprises the steps of:
a) loading into a memory pre-computed digital values defining a sinusoidal waveform. These can be computed either by a 3 bit NCO or simulation software such as can b obtained from MATLAB.
b) reading from said memory said pre-computed digital values into a barrel shifter;
c) using the barrel shifter to rotating said pre-computed digital values to obtain rotated values;
d) presenting said rotated values obtained from said memory to an input of a multiplexer at a first rate determined by a a first clock;
e) multiplexing the rotated values using a multiplexer having an output connected to a Digital to Analog converter, said Digital to Analog converter converting said digital values presented by said multiplexer to said analog output at a second rate determined by a second clock.
Routing of pre-computed digital values from/to memory 335, or NCO, to said barrel shifter 311 is performed using a bus exchange switch.
All references cited in this document are incorporated herein in their entirety by reference.
Those skilled in the art will also appreciate that numerous changes and modifications could be made to the embodiment described herein without departing in any way from the invention. These changes and modifications and all obvious variations of the disclosed embodiment are intended to be embraced by the claims to the limits set by law.
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