A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.
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12. A method of plasma etching a layer of a dielectric material comprising:
exposing a layer of hfo2 to a plasma comprising carbon monoxide and a halogen containing gas.
1. A method of plasma etching a layer of a dielectric material having a dielectric constant that is greater than 4, comprising:
exposing the layer to a plasma comprising carbon monoxide and a halogen containing gas, wherein the dielectric material is at least one of hfo2, ZrO2, Al2O3, ZrSiO2, HfSiO2, and TaO2.
17. A method for plasma etching a workpiece having a layer of hafnium-oxide comprising the steps of:
supplying between 20 to 300 sccm of chlorine and between 2 to 200 sccm of carbon monoxide; maintaining a gas pressure of between 2-100 mTorr; applying a bias power to a cathode electrode of between 5 to 100 W; applying power to an inductively coupled antenna of between 200 to 2500 W to produce a plasma containing said chlorine gas and said carbon monoxide gas; maintaining said workpiece at a temperature between 100 and 500 degrees Celsius.
5. The method of
supplying 20 to 300 sccm of Cl2 and 2 to 200 sccm of CO.
7. The method of
applying a bias power to a cathode electrode of 20 W.
8. The method of
applying an inductive source power to an inductively coupled antenna of 1100 W.
9. The method of
maintaining a gas pressure of between 2-100 mTorr.
10. The method of
applying a bias power to a cathode electrode of 5 to 100 W.
11. A The method of
applying an inductive source power to an inductively coupled antenna of 200 to 2500 W.
13. The method of
maintaining a workpiece containing the layer of hfo2 at a temperature between 100 to 500 degrees Celsius.
14. The method of
maintaining a workpiece containing the layer of hfo2 at a temperature of 350 degrees Celsius.
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1. Field of Invention
The present invention relates generally to a method of dry etching semiconductor wafers. More specifically, the invention relates to a method of etching high K dielectric materials using a gas mixture comprising a halogen gas and a reducing gas.
2. Description of the Background Art
Field effect transistors that are used in forming integrated circuit generally utilize a polysilicon gate electrodes deposited upon a gate dielectric that separates the electrode from the channel between source and drain regions. In prior art transistor structures, the gate dielectric is typically fabricated of silicon dioxide (SiO2). However, as integrated circuit transistors have become smaller (on the order of 100 nanometers in width), the thickness of the dielectric material in the gate structure has become thinner than 10 Angstroms. With such a thin dielectric, electrons can propagate from the polysilicon gate electrode into the transistor channel causing the transistor to operate improperly or become defective.
This leakage of electrons from the gate electrode through the gate oxide has led researchers to investigate the use of more stable high K dielectric materials. One very stable dielectric material having a high dielectric constant is hafnium-oxide (HfO2). However, hafnium-oxide is such a stable dielectric material that it is very difficult to etch using conventional oxide etchants to form into gate structures without damaging other layers of material residing on the wafer. As such, hafnium-oxide has found limited use in semiconductor devices.
Therefore, there is a need in the art for a high K material etching process having very high selectivity to silicon oxide, polysilicon and silicon.
The disadvantages associated with the prior art are overcome by the present invention for etching materials with high dielectric constants (high K materials have a dielectric constant greater than 4.0) such as HfO2, ZrO2, Al2O3, BST, PZK, ZrSiO2, HFSiO2, TaO2, and the like using a gas mixture comprising a halogen gas and reducing gas. In one embodiment of the invention, an etch gas (or mixture) comprising chlorine (Cl2) and carbon monoxide (CO) is used for etching hafnium-oxide films. In one example, the gas flow rates are in the range 20-300 sccm Cl2 and about 2-200 sccm CO (i.e., a CL2/CO flow ratio (0.1-1):(1-0.1)), with a total chamber pressure in the range of 2-100 mTorr.
A decoupled plasma source etch reactor is illustratively used to practice one embodiment of the present invention. In general, the reactor uses an inductive source power of about 200-2500 W for plasma generation, and applies a cathode bias power of about 5-100 W to a wafer support pedestal. The reactor maintains the pedestal within a temperature range of about 100 to 500 degrees Celsius. The invention can be practiced, for example, by supplying to the reactor a combination of about 40 sccm of chlorine gas and about 40 sccm of carbon monoxide gas, while maintaining a total chamber pressure of about 4 mTorr. The gas mixture is supplied to the reaction chamber wherein a plasma is formed and a hafnium-oxide layer is etched.
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical element that are common to the figures.
The present invention is a method of etching materials with high dielectric constants (high K materials have dielectric constants greater than 4.0) using a plasma generated from a gas (or gas mixture) comprising gases containing a halogen gas (such as Cl2, HCl and the like) and a reducing gas (such as carbon monoxide (CO). The high K materials include HfO2, ZrO2, Al2O3, BST, PZK, ZrSiO2, HfSiO2, TaO2, and the like. The type of halogen gas is selected to best remove the metal from the dielectric layer and the type of reducing gas is selected to best remove the oxygen from the dielectric layer. The etch process of the present invention can be reduced to practice in a Decoupled Plasma Source (DPS) Centura® etch system or a DPS-II etch system available from Applied Materials, Inc. of Santa Clara, Calif.
In operation, the semiconductor substrate 114 is placed on the substrate support pedestal 116 and gaseous components are supplied from a gas panel 138 to the process chamber 110 through entry ports 126 to form a gaseous mixture 150. The gaseous mixture 150 is ignited into a plasma 152 in the process chamber 110 by applying RF power from the RF sources 118 and 122 respectively to the antenna 112 and the cathode 116. The pressure within the interior of the etch chamber 110 is controlled using a throttle valve 127 situated between the chamber 110 and a vacuum pump 136. The temperature at the surface of the chamber walls 130 is controlled using liquid-containing conduits (not shown) that are located in the walls 130 of the chamber 110.
The temperature of the substrate 114 is controlled by stabilizing the temperature of the support pedestal 116 and flowing helium gas from source 148 to channels formed by the back of the substrate 114 and grooves (not shown) on the pedestal surface. The helium gas is used to facilitate heat transfer between the pedestal 116 and the substrate 114. During the etch process, the substrate 114 is heated by a resistive heater within the pedestal to a steady state temperature and the helium facilitates uniform heating of the substrate 114. Using thermal control of both the dome 120 and the pedestal 116, the substrate 114 is maintained at a temperature of between 100 and 500 degrees Celsius.
The RF power applied to the inductive coil antenna 112 has a frequency between 50 kHz and 13.56 MHz and has a power of 200 to 2500 Watts. The bias power applied to the pedestal 116 may be DC or RF and is between 5 and 100 Watts.
Those skilled in the art will understand that other forms of etch chambers may be used to practice the invention, including chambers with remote plasma sources, microwave plasma chambers, electron cyclotron resonance (ECR) plasma chambers, and the like.
To facilitate control of the chamber as described above, the CPU 144 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and subprocessors. The memory 142 is coupled to the CPU 144. The memory 142, or computer-readable medium, may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 146 are coupled to the CPU 144 for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. An etching process 200 is generally stored in the memory 142 as a software routine 202. The software routine 202 may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 144.
The specific embodiment of the etching process 200 depicted in
The foregoing steps of the process 200 need not be performed sequentially. For example, some or all of the steps may be performed simultaneously to etch a hafnium-oxide or other high K dielectric layer.
The foregoing steps of the process 200 need not be performed sequentially. For example, some or all of the steps may be performed simultaneously to etch a hafnium-oxide or other high K dielectric layer.
The software routine 202 is discussed with respect to FIG. 1 and FIG. 2. The software routine 202 is executed after a wafer 114 is positioned on the pedestal 116. The software routine 202 when executed by the CPU 144, transforms the general purpose computer into a specific purpose computer (controller) 140 that controls the chamber operation such that the etching process 200 is performed. Although the process of the present invention is discussed as being implemented as a software routine, some of the method steps that are disclosed therein may be performed in hardware as well as by the software controller. As such, the invention may be implemented in software as executed upon a computer system, in hardware as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware.
Continuing to refer to FIG. 1 and
Once the gas mixture 150 is present above the wafer 114, step 212 applies 200-2500 Watts of RF power to the antenna 112, and plasma 152 is formed. The wafer 114 is heated to 100-500 degrees Celsius in step 214. Etching of the wafer 114 occurs in step 216. One specific recipe for etching hafnium-oxide uses a pedestal bias power of 20 watts, 40 sccm of Cl2, 40 sccm of CO, a chamber pressure of 4 mTorr, an antenna power of 1100 watts and a pedestal temperature of 3500°C C.
One illustrative embodiment of the inventive process is used for etching a wafer 114 containing a film stack 310 of
The result of the inventive etching method is best appreciated by referring to a gate structure depicted in
The invention may be practiced in other etching equipment wherein the processing parameters may be adjusted to achieve acceptable etch characteristics by those skilled in the arts by utilizing the teachings disclosed herein without departing from the spirit of the invention.
Kumar, Ajay, Jin, Guangxiang, Nallan, Padmapani C.
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Mar 05 2002 | JIN, GUANGXIANG | Applied Materials, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012713 | /0992 | |
Mar 05 2002 | KUMAR, AJAY | Applied Materials, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012713 | /0992 |
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