The present invention provides a method for making an integrated circuit capacitor having a Ta2O5 dielectric which includes a high-temperature nitrogen anneal and a low-temperature ozone anneal of the dielectric.
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18. An integrated circuit capacitor comprising:
a bottom electrode formed over an oxidizable polycrystalline silicon plug, said polycrystalline silicon plug having an initial resistance value; an annealed tantalum pentoxide dielectric formed over said bottom electrode; an upper electrode formed over said tantalum pentoxide dielectric, wherein said oxidizable polycrystalline silicon plug has a post-anneal resistance value which is no more than fifty percent higher than said initial resistance value.
11. An integrated circuit capacitor comprising:
an oxygen/nitrogen gas annealed structure comprising: a polycrystalline silicon plug, said polycrystalline silicon plug having an annealed resistance value which is no more than fifty percent higher than an initial resistance value; a bottom electrode formed over said polycrystalline silicon plug, said bottom electrode comprising at least one of a platinum, rhodium, and a platinum-rhodium alloy layer; and a tantalum pentoxide layer formed over said bottom electrode, said annealed tantalum pentoxide having crystal growth primarily in <001> direction; and an upper electrode formed over said tantalum pentoxide layer, said upper electrode comprising at least one of a platinum, rhodium, and a platinum-rhodium alloy layer.
1. An integrated circuit capacitor comprising:
an oxygen/nitrogen gas annealed structure comprising: a polycrystalline silicon plug, said polycrystalline silicon plug having an annealed resistance value which is no more than fifty percent higher than an initial resistance value; a bottom electrode formed over said polycrystalline silicon plug, said bottom electrode comprising at least one of a platinum, rhodium, and a platinum-rhodium alloy layer; and a tantalum pentoxide layer formed over said bottom electrode, said annealed tantalum pentoxide having crystal growth primarily in the <200> direction; and an upper electrode formed over said tantalum pentoxide layer, said upper electrode comprising at least one of a platinum, rhodium, and a platinum-rhodium alloy layer.
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This application is a division of application Ser. No. 10/137,424, filed May 3, 2002.
1. Field of the Invention
The present invention relates to the field of semiconductors, and more particularly to a method for making a capacitor in an integrated circuit.
2. Description of the Related Art
A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance C, defined by C=kk0A/d, where k is the relative dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode surface area and d is the distance between electrodes.
As integrated circuits are continually scaled down and achieve ever higher levels of integration, the area available for memory cells is being reduced. Nevertheless, each capacitor is still required to maintain a minimum capacitance. It is therefore important that capacitors achieve a high stored charge per footprint or unit of chip area occupied. However, the use of silicon nitride (Si3N4) as the dielectric in DRAM capacitors is reaching some fundamental limitations as DRAM cells are scaled down. For example, as the Si3N4 film is continually made thinner, leakage current arising from electron tunneling through the dielectric increases. A thicker Si3N4 film is of course unacceptable since a higher distance between electrodes results in lower capacitance and a lowering of the charge able to be stored in the capacitor. Before long, such a limitation will present a barrier to the development of future generations of DRAM cells.
Several techniques have been considered for increasing the total charge capacity of the DRAM cell capacitor without significantly affecting the chip area occupied by the cell. Perhaps the most promising solution is the use of new capacitor dielectrics with higher dielectric constant k values. The decrease in capacitance that would occur were a thicker Si3N4 film to be used is offset by a higher k value. That is, the higher dielectric constant allows a thicker film to be deposited than would be practicable with Si3N4, while reducing leakage current and providing a level of capacitance that would be unattainable with Si3N4 films. One promising dielectric candidate is tantalum pentoxide (Ta2O5), which is characterized by an effective dielectric constant significantly higher than conventional dielectrics such as Si3N4. Whereas k=9 for silicon nitride, Ta2O5 has a dielectric constant of about 25. Therefore, using Ta2O5 enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement.
However, difficulties have been encountered in incorporating Ta2O5 into conventional fabrication flows. For example, after Ta2O5 is deposited on a capacitor electrode, it must be annealed at a high temperature in the presence of a highly oxidizing plasma or ambient. The high temperature converts the amorphous Ta2O5 to crystalline Ta2O5, which is preferred to achieve a higher dielectric constant. The highly oxidizing plasma or ambient reduces leakage current by ensuring maintenance of the appropriate oxygen content in the dielectric. However, the oxygen diffuses through the Ta2O5 layer and oxidizes elements of the integrated circuit including the bottom electrode of the capacitor, for example, a metal electrode, a diffusion barrier, and an underlying polycrystalline silicon (polysilicon) plug. This oxidization negates the advantages realized by utilizing Ta2O5 over Si3N4 as the capacitor dielectric in the first place. For example, oxygen diffusing through the bottom electrode oxidizes the polysilicon plug. This creates a layer of insulating SiO2 at the surface of the polysilicon plug which significantly increases resistance at the capacitor to plug interface. One solution is to employ a conductive oxygen barrier to halt the diffusion of the oxidant to structures in the capacitor and integrated circuit. This, however, has proven very difficult and costly to achieve.
Thus, there is a need for an improved method for making a DRAM cell capacitor with a crystalline Ta2O5 dielectric exhibiting low leakage while at the same time possessing a crystalline structure which provides high capacitance.
The present invention provides a method for making a DRAM cell capacitor that utilizes crystalline Ta2O5 having low leakage characteristics as the dielectric while mitigating oxidation problems. A diffusion barrier layer formed of tantalum nitride (TaN), titanium nitride (TiN), or tantalum silicon nitride (TaSiN) is formed on top of the polysilicon plug, and a bottom capacitor electrode formed from platinum, rhodium, or a platinum-rhodium alloy is formed on the diffusion barrier layer. Ta2O5 is deposited on the bottom electrode and is then annealed at least two times. One of the anneals is a high-temperature anneal in a nitrogen (N2) ambient which crystallizes Ta2O5 in an orientation that provides a high dielectric constant. Another anneal is accomplished at low temperature in an ozone (O3) ambient, achieving a reduction in leakage current. After the anneals are completed, an upper electrode of platinum, rhodium, or platinum-rhodium alloy is deposited on top of the crystalline Ta2O5.
Additional advantages and features of the present invention will be apparent from the following detailed description provided in connection with the accompanying drawings which illustrate exemplary embodiments of the invention.
In the following description, reference is made to the accompanying drawings which will serve to illustrate exemplary embodiments of the invention. The description provides sufficient detail to enable those skilled in the art to practice the invention. Of course other embodiments may be used and various changes may be made without departing from the scope of the present invention. The scope of this invention is defined by the appended claims.
Referring now to the drawings, one embodiment of a method for making a DRAM cell capacitor is represented in FIG. 1. The DRAM capacitor is made according to a process which begins with the structure of FIG. 2. The capacitor manufacture begins after the formation of most of the elements of the memory cell, including a word line gate 32 formed over a gate oxide 31 and source/drain areas 34 and 36 which together form an access transistor 38 on the semiconductor substrate 30.
Following the fabrication of the transistor 38, an insulating layer 40, made of a material such as borophosphosilicate glass (BPSG) is formed over the semiconductor substrate 30 as well as the transistor 38. An conductive plug 42 made from an oxidizable material such as polysilicon is formed in insulating layer 40 and provides a conductive contact with active area 34. A second insulating layer 44 is formed over the first insulating layer 40 and an opening 72 is provided therein over the plug 42 for construction of a capacitor. Insulating layer 44, like insulating layer 40, may be formed of BPSG.
The capacitor that is the subject of this invention is formed in opening 72. Referring to FIG. 1 and
Referring now to FIG. 1 and
FIG. 1 and
Referring to FIG. 1 and
After the Ta2O5 layer 52 is formed on the bottom electrode, it is twice annealed as depicted in
In another embodiment of the present invention, the Ta2O5 layer 52 is annealed first in an ozone ambient at a temperature of about 25°C C. to about 550°C C. as shown in step 22, followed by an N2 anneal at a temperature of about 650°C C. to about 900°C C., as shown in step 20. In either embodiment, little oxidation of DRAM cell components such as polysilicon plug 42 occurs in the annealing process because of the relatively low temperature used in the ozone anneal step 22.
In both these embodiments, the temperature maintained during the ozone anneal is about 550°C C. or less. Performing an anneal with an oxygen-containing (and thus highly oxidizing) ambient at a relatively low temperature mitigates oxidation of the polysilicon plug and other parts of the memory cell. The acceptable amount of oxidation allowable in a memory capacitor utilizing a Ta2O5 dielectric can be expressed in terms of resistance of the polysilicon plug. An anneal in the presence of an oxygen containing ambient that results in a post-anneal polysilicon plug resistance of not more than about 50% greater than pre-anneal polysilicon plug resistance represents an acceptably low level of oxidation occurring during the anneal sequence, meaning that a memory cell capacitor with a Ta2O5 dielectric that is subject to this level of resistance or less will display less leakage than capacitors annealed in nitrogen only.
As shown in
Referring now to FIG. 8 and
The anneal sequence represented by a triangle in FIG. 8 and
The second anneal sequence performed according to the present invention (represented in FIG. 8 and
The third anneal sequence performed according to the present invention (represented in FIG. 8 and
Referring now to FIG. 10 and
While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
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