A capacitive charge pump that can be implemented in such devices as e.g. a phase locked loop (PLL). The charge pump includes at least one capacitor in the charge path and discharge path for limiting the amount of charge provided to or removed from a filter capacitor of a PLL. In one example, a second capacitor may be provided in the charge path or discharge path to reduce the capacitance (if provided in series) or increase the capacitance (if provided in parallel) to adjust the maximum amount of charge transferred to a filter capacitor. In one example, multiple capacitive stages may be implemented in parallel to increase the maximum amount of charge transferred to a filter capacitor. Each stage is enabled after a delayed period of time from when the previous stage was enabled.
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32. A charge pump comprising:
an output node;
a charge path including a first capacitor;
a first switch including a control electrode coupled to receive a first charge control signal, wherein the first capacitor selectively provides charge based on the first charge control signal, to the output node via the first switch;
a discharge path including a second capacitor;
a second switch having a control electrode coupled to receive a second charge control signal, wherein the second capacitor selectively receives charge, based on the second charge control signal, from the output node.
11. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a second terminal of the first capacitor and a second terminal coupled to a first voltage supply.
31. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
wherein the first switch includes a pass gate, the pass gate having a second control electrode coupled to receive an inverse of the first switch control signal.
1. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node; and
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a second circuit node;
a second switch having a first current electrode coupled to the second circuit node, a second current electrode coupled to the output node;
a delay circuit having an input coupled to receive the first switch control signal and an output coupled to a control electrode of the second switch.
13. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive it first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a terminal of the first capacitor and a second terminal coupled to a first voltage supply;
a second switch having a first current electrode coupled to the first terminal of the second capacitor, a second current electrode coupled to the first voltage supply, and a control electrode coupled to receive an inverse of the first switch control signal.
18. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a first supply voltage;
a second switch having a control electrode coupled to receive the first switch control signal, a first current electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a second terminal of the second capacitor wherein, the second switch selectively couples, based on the first switch control signal, the first capacitor and the second capacitor in series.
9. A charge pump, comprising:
an output node;
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a potential setting circuit coupled to the first circuit node, wherein the potential setting circuit selectively sets, based on the first switch control signal, the first circuit node to a first potential;
wherein the potential setting circuit has a first current electrode coupled to a node whose voltage is dependent upon a voltage of the output node and a second current electrode coupled to the first circuit node, wherein the first potential is dependent upon on the voltage of the output node.
14. A charge pump, comprising:
an output node:
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a second circuit node; and
a second switch having a first current electrode coupled to the second circuit node, a control electrode coupled to receive a second switch control signal, and a second current electrode coupled to the output node, wherein the second switch control signal controls charge transfer between the second capacitor and the output node;
a first potential setting circuit coupled to the first circuit node, wherein the first potential setting circuit selectively sets, based on the first switch control signal, the first circuit node to a first potential, wherein the first potential is dependent upon on a voltage of the output node
a second potential setting circuit coupled to the second circuit node wherein the second potential setting circuit selectively sets, based on the second switch control signal, the second circuit node to a second potential, wherein the second potential is dependent upon on the voltage of the output node.
41. A charge pump, comprising:
an output node:
a first capacitor having a first terminal coupled to a first circuit node;
a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node;
a second capacitor having a first terminal coupled to a second circuit node; and
a second switch having a first current electrode coupled to the second circuit node, a control electrode coupled to receive a second switch control signal, and a second current electrode coupled to the output node, wherein the second switch control signal controls charge transfer between the second capacitor and the output node;
a third capacitor having a first terminal coupled to a third circuit node;
a third switch having a first current electrode coupled to the third circuit node, a second current electrode coupled to the output node;
a first delay circuit having an input coupled to receive the first switch control signal and an output coupled to a control electrode of the third switch;
a fourth capacitor having a first terminal coupled to a fourth circuit node;
a fourth switch having a first current electrode coupled to the fourth circuit node, a second current electrode coupled to the output node;
a second delay circuit having an input coupled to receive the second switch control signal and an output coupled to a control electrode of the fourth switch.
24. A phase locked loop (PLL) circuit comprising:
a filter capacitor;
a phase frequency detector circuit having a first input to receive a first clack, a second input to receive a second clock, and a first output to provide a first clock control signal based on the first clock and the second clock, wherein the phase frequency detector circuit has a second output to provide a second clock control signal based on the first clock and the second clock;
a voltage controlled oscillator having an input coupled to a first terminal of the filter capacitor and an output to provide an output clock;
a charge pump having a first input to receive the first clock control signal and an output coupled to the first terminal of the filter capacitor and the input of the voltage controlled oscillator, the charge pump comprising:
a first capacitor having a first terminal:
a first switch having a first current electrode coupled to the first terminal of the first capacitor, a control electrode coupled to receive the first clock control signal, and a second current electrode coupled to the first terminal of the filter capacitor, tho first switch selectively coupling the first capacitor to the filter capacitor, based on the first clock control signal;
a second capacitor;
a second switch having a first current electrode coupled to a first terminal of the second capacitor, a second current electrode coupled to the first terminal of the filter capacitor, and a control electrode coupled to receive the second clock control signal, the second switch selectively coupling the second capacitor to the filter capacitor, based on the second clock control signal;
a potential setting circuit coupled to the first terminal of the first capacitor, wherein the potential setting circuit selectively sets, based on the first clock control signal, the first terminal of the first capacitor to a first potential;
a second potential setting circuit coupled to the first terminal of the second capacitor, wherein the second potential setting circuit selectively sets, based on the second clock control signal, the first terminal of the second capacitor to a second potential;
wherein the first and second potentials are dependent upon a voltage of the output node.
2. The charge pump of
3. The charge pump of
4. The charge pump of
5. The charge pump of
6. The charge pump of
the first capacitor and the first switch are implemented on an integrated circuit;
the second capacitor and the second switch are implemented on the integrated circuit.
7. The charge pump of
a potential setting circuit coupled to the second circuit node and selectively sets, based on the first switch control signal, the second circuit node to a first potential.
8. The charge pump of
10. The charge pump of
a comparator having a first input coupled the output node;
a current source coupled to an output of the comparator; and
a second switch having a first current electrode coupled to a second input of the comparator, a control electrode coupled to the output node, and a second current electrode coupled to the current source.
12. The charge pump of
a third switch having a first current electrode coupled to the first terminal of the second capacitor, a second current electrode coupled to the first voltage supply, and a control electrode coupled to receive an enable signal, wherein the third switch selectively enables the second capacitor in response to the enable signal.
15. The charge pump of
16. A phase locked loop circuit including the charge pump of
a filter capacitor having a first terminal coupled to the output node;
a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide the first switch control signal based on the first clock and the second clock and a second output to provide the second switch control signal based on the first clock and the second clock;
a voltage controlled oscillator having an input coupled to the output node and an output to provide an output clock.
17. The charge pump of
the first potential setting circuit has a first current electrode coupled to a node whose voltage is dependent upon the voltage of the output node and a second current electrode coupled to the first circuit node;
the second potential setting circuit has a first current electrode coupled to a node whose voltage is dependent upon a voltage of the output node and a second current electrode coupled to the second circuit node.
19. The charge pump of
20. The charge pump of
21. The charge pump of
22. The charge pump of
a first potential setting circuit coupled to the first capacitor, the potential setting circuit selectively setting, based on the first switch control signal, the first circuit node to a first potential;
a second potential setting circuit coupled to the second terminal of the second capacitor and selectively setting, based on the first switch control signal and a second switch control signal, the second terminal of the second capacitor to the first potential.
23. The charge pump of
25. The PLL circuit of
28. The PLL circuit of
a frequency divider having an input to receive the output clock and an output to provide the second clock.
29. The PLL circuit of
30. The PLL circuit of
33. The charge pump of
a first potential setting circuit coupled to a first terminal of the first capacitor, wherein the first potential setting circuit selectively sets, based on the first charge control signal, the first terminal of the first capacitor to a first potential; and
a second potential setting circuit coupled to a first terminal of the second capacitor, wherein the second potential setting circuit selectively sets, based on the second charge control signal, the first terminal of the second capacitor to a second potential.
35. The charge pump of
36. The charge pump of
a third capacitor, wherein the third capacitor is coupled in series with the first capacitor, and wherein the first and third capacitors selectively provide charge, based on the first charge control signal and an enable signal, to the output node via the first switch; and
a fourth capacitor, wherein the fourth capacitor is coupled in series with the second capacitor, and wherein the second and fourth capacitors selectively receive charge, based on the second charge control signal and an enable signal, from the output node via the second switch.
37. The charge pump of
when the enable signal has a first value, the first capacitor and not the third capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch, and
when the enable signal has a second value, the first capacitor and the third capacitor selectively provide charge, based on the first charge control signal, to the output node via the first switch.
38. The charge pump of
a third capacitor, the third capacitor selectively provides charge, based on a signal dependent upon the first charge control signal, to the output node;
a fourth capacitor, the fourth capacitor selectively receives charge, based on a signal dependent upon the second charge control signal, from the output node.
39. A phase locked loop circuit including the charge pump of
a filter capacitor having a first terminal coupled to the output node;
a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide the first charge control signal based on the first clock and the second clock and a second output to provide the second charge control signal based on the first clock and the second clock;
a voltage controlled oscillator having an input coupled to the output node and an output to provide an output clock.
40. The charge pump of
the first switch has a first current electrode coupled to a first terminal of the first capacitor and has a second current electrode coupled to the output node;
the first capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch:
the second switch has a first current electrode coupled to a first terminal of the second capacitor and has a second current electrode coupled to the output node;
the second capacitor selectively receives charge, based on the second charge control signal, from the output node via the second switch.
42. The charge pump of
43. The charge pump of
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1. Field of the Invention
This invention relates in general to electronic devices and specifically to charge pumps.
2. Description of the Related Art
Phase locked loops (PLL) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal maybe at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal.
Typically, a PLL utilizes a charge pump which receives clock control signals from a phase frequency detector (PFD) and provides current to a filter capacitor to control the voltage of a frequency control input of a voltage controlled oscillator (VCO).
With PLLs implemented in semiconductor devices, the filter capacitor may be constructed by utilizing CMOS technology. The drive to reduce the size of electronic devices has increased the difficulty of implementing filter capacitors in a semiconductor device. For example, reducing the thickness of gate oxides increases the gate leakage currents of a capacitor implemented in a semiconductor device. Also, reducing the size of semiconductor devices means that a proportionally larger area of the device must be allocated to obtain the same capacitance.
In addition, conventional charge pumps typically require high tolerance transistors and resistors to ensure reliable operation. As the size of semiconductor devices decreases, providing high tolerance transistors, resistors, and diodes becomes more difficult. What in needed is an improved charge pump for electronic circuits such as phase locked loops.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.
The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.
In the embodiment of
In one embodiment, phase locked loop 105 is implemented in an integrated circuit utilizing CMOS technology. Phase locked loop 105 may be integrated with other devices which utilize phase locked loop 105 such as e.g. with a processor in an integrated circuit. With other embodiments, the circuits of phase locked loop 105 may be implemented with other types of circuitry including e.g. with silicon on insulator (SOI) transistors or with discrete components.
Limiting the amount of charge provided to or removed from a filter capacitor by capacitors 211 and 217 may advantageously limit the change in frequency of VCO 113 due to a noisy event (such as, e.g., in the REF CLK and CLK OUT signals) causing input phase error. With conventional charge pumps, the amount of charge provided to (or discharged from) a filter capacitor is proportional to the input phase error over a wide phase differential range. If one of the two inputs to PFD circuit 109 momentarily drifts due e.g. to noise, the error in the output of the VCO is relatively large due to that error. However, with the capacitive charge pump of
Referring back to
Capacitive charge pump 111 includes two node potential setting circuits for setting the voltage of nodes 212 and 216 prior to the assertion of the UP* and DOWN signals, respectively. The first potential setting circuit includes a transistor 209 that when made conductive by the inverted UP* signal (inverted via inverter 205), shorts node 212 to VDD, thereby removing the charge from capacitor 211. The second potential setting circuit includes transistor 219, which when made conductive by the inverted DOWN signal (inverted via inverter 207) shorts node 216 to ground, thereby removing the charge from capacitor 217.
When PFD circuit 109 asserts the UP* signal, the asserted UP* signal makes conductive transistor 213 and makes non conductive (via inverter 205) transistor 209 for charge to flow from VDD through capacitor 211 and transistor 213 to filter capacitor 115 to raise the voltage level of the Vctrl signal. As current flows through capacitor 211, the charge in capacitor 211 increases, thereby reducing the amount of charge flowing into filter capacitor 115, until the voltage level (which is falling as capacitor 211 charges) of node 212 is equal to the voltage of Vctrl (which is rising as capacitor 115 is rising). The voltage where the voltage level of node 212 equals the voltage level of Vctrl can be represented by the formula:
Vctrlfin=((Vctrlin+K)/(1+K))*(VDD)
Where Vctrlfin is the voltage level of node 212 when node 212 equals the voltage of Vctrl; Vctrlin is the voltage level of the Vctrl signal prior to the assertion of the UP* signal; and K is the ratio of the capacitance of capacitor 211 to the capacitance of filter capacitor 115.
When PFD circuit 109 deasserts the UP* signal (at the end of the UP* signal pulse in some embodiments) transistor 213 is made non conductive and transistor 209 is made conductive. When the UP* signal is deasserted, the voltage level on each terminal of capacitor 211 is at VDD, wherein capacitor 211 is discharged.
When PFD circuit 109 asserts the DOWN signal, the asserted DOWN signal makes conductive transistor 215 and makes non conductive (via inverter 207) transistor 219 for charge to flow from filter capacitor 115, via transistor 215 and capacitor 217, to lower the voltage level of signal Vctrl. As current flows through capacitor 217, the charge in capacitor 217 increases thereby reducing the amount of charge flowing out of filter capacitor 115 until the voltage level (which is rising as capacitor 217 charges) of node 216 is equal to Vctrl (which is falling as the charge in capacitor 115 is falling). This voltage level where the voltage level of node 212 equals the voltage level of Vctrl can be represented by the formula:
Vctrlfin=Vctrlin/(1+K)
Where Vctrlfin is the voltage level of node 216 when node 216 equals the voltage level of the Vctrl signal; Vctrlin is the voltage level of the Vctrl signal prior to the assertion of the DOWN signal; and K is the ratio of the capacitance of capacitor 217 to the capacitance of filter capacitor 115.
When PFD circuit 109 deasserts the DOWN signal (at the end of a DOWN signal pulse in some embodiments) transistor 215 is made non conductive and transistor 219 is made conductive. At this time, the voltage level on each terminal of capacitor 217 is at system ground, wherein capacitor 217 is discharged.
Capacitors 211 and 217 are sized to control the maximum change in the voltage level of the Vctrl signal when the UP* and DOWN signals are asserted, respectively. For example, the greater the ratio (K) of the capacitance of capacitor 211 to the capacitance of filter capacitor 115, the greater the increase in the voltage level of Vctrl (and accordingly, the greater the increase in the frequency of CLK OUT in the embodiment shown) for the period of the assertion of the *UP signal. Also, the greater the ratio of the capacitance of capacitor 217 to the capacitance of filter capacitor 115, the greater the decrease in Vctrl for the period of the assertion of the DOWN signal. In some embodiments, the capacitance of filter capacitor 115 is significantly greater (e.g. ≧100×) than the capacitance of capacitor 211 or 217. In one embodiment, the capacitance of filter capacitor 115 is 2000 times greater than the capacitance of capacitor 211 or capacitor 217.
Because the change in the voltage level of Vctrl is dependent upon the (K) ratio, a reduction in device technology may not necessarily require an increase in the percentage of the area of a device needed for a filter capacitor. With some embodiments, capacitors 211 and 217 may be size such that they are the minimum capacitor size that can be reliably manufactured for the device technology size. With some decreasing technologies sizes, the minimal capacitor size may be reduced. Thus, the size of capacitors 211 and 217 would be reduced with such technologies. Accordingly, because the change in the voltage level of Vctrl is dependent upon the K ratio, the size of capacitor 115 could be reduced proportionally to maintain the K ratio. Consequently, a reduction in device technology size may allow for a reduction in the total area required for a filter capacitor.
In one embodiment, capacitors 211, 217, and 115 are metal capacitors having metal comb structure that spans multiple metal levels in an integrated circuit implementing phase locked loop 105. However, in other embodiments, the capacitors may be made from transistors configured to provide capacitance or may be implemented by other techniques.
The additional capacitance (e.g. 511 or 533) in the charge pump 501 is enabled by an enable signal (EN) that is provided from a circuit that controls the transfer function characteristics of a phase locked loop implementing charge pump 501. An example of such a circuit may be an I/O device (not shown) that is programmed by a processor (not shown) for setting the transfer function of the phase locked loop via software. In other embodiments, the enable signal may be provided by hardware circuitry in response to a specific condition such as e.g. a power on reset. In some embodiments, the enable signal could be hardwired by the manufacture of the device implementing the phase locked loop.
In the embodiment of
When the EN signal is asserted, transistor 535 is made non conductive via inverter 537. When the EN signal is asserted, the only path from ground to capacitor 525 is through capacitor 533 when the DOWN signal is asserted. When the EN signal is not asserted (a low voltage), transistor 535 is made conductive to short node 532 to system ground, thereby bypassing capacitor 533. Accordingly, when EN is not asserted, only capacitor 525 is in the discharge path when the DOWN signal is asserted.
Charge pump 501 includes a node potential setting circuit that includes transistor 502 for pulling node 512 to VDD and a node potential setting circuit that includes transistor 500 for pulling node 514 to VDD when the UP* signal is not asserted. Transistors 500 and 502 are made conductive by a non asserted UP* via inverter 505. Pulling nodes 512 and 514 to VDD discharges capacitors 511 and 513 in that both terminals of each capacitor is at the same voltage potential.
Charge pump 501 also includes two node potential setting circuits (transistors 519 and 531) for pulling node 524 and 532 to ground, respectively, to discharge capacitors 525 and 533 when the DOWN signal is non asserted.
The charge path of capacitive charge pump 701 includes three capacitive stages with each stage having a capacitor (709, 715, and 731) that may be coupled in parallel with the other two capacitors to provide capacitance to the charge path. Each capacitor stage also includes a coupling transistor (711, 717, and 733) to couple the capacitor of the capacitive stage to be part of the charge path. For example, when coupling transistor 717 is conductive, capacitor 715 is part of the charge path wherein the capacitance of capacitor 715 provides capacitance to the charge path. Each capacitive stage also includes a node potential setting circuit that includes a transistor (707, 713, and 729) that when made conductive by a non asserted UP* signal (via inverter 705), pull nodes 710, 716, and 732 to VDD, respectively, to discharge capacitors 709, 715, and 731, respectively.
The discharge path also includes three capacitive stages that each include a capacitor (747, 751, and 767) a coupling transistor (745, 757, and 763), and a node potential setting circuit that includes a transistor (743, 749, and 765) for discharging the capacitor (747, 751, and 767) of its stage to ground in response to a non asserted DOWN signal via inverter 741.
In the embodiment of
Because of the delay provided by inverters 721 and 723, capacitor 715 is not implemented in the charge path until the UP* signal has been asserted for a predetermined period of time. This predetermined time corresponds to an input phase error having a predetermined value (IPE3). For input phase errors of greater than IPE3, the output/phase voltage response increases at a rate (as shown by line portion 806) set by the combined resistance of transistors 711 and 717 in parallel. Accordingly, line portion 806 has a steeper slope than line portion 804 (whose slope is determined by the resistance of transistor 711). Capacitor 731 is not implemented in the charge path until the UP* signal has been asserted for another predetermined period of time which corresponds to an input phase error of IPE4. In one embodiment, IPE3 corresponds to a delay time of 20 picoseconds and IPE4 corresponds to a delay time of 40 picoseconds.
As shown by the transfer function of
In a modification of
Other embodiments may include more than three capacitive stages in both the charge and discharge paths. Also, as a further modification of
Setting node 906 to 4/3 Vctrl and setting node 910 to 2/3 Vctrl enables the charge path of charge pump 901 to provide the same magnitude of charge in response to a positive input phase error as the magnitude of charge that the discharge path removes in response to a negative input phase error of the same magnitude regardless of the voltage level of Vctrl. With the embodiment of
Charge pump 901 includes a potential setting circuit for setting node 906 to a potential of 4/3 the voltage of Vctrl. The potential setting circuit includes a pass gate 937 having one control terminal coupled to received the UP* signal and the other control terminal coupled to receive an inverted UP* signal via inverter 935. When the UP* signal is non asserted, pass gate 937 allows node 906 to be pulled to a voltage of 4/3 Vctrl (the voltage at node 950). Setting the voltage of node 906 to 4/3 Vctrl charges capacitor 905 to a predetermined charge level when the UP* signal is non asserted. When the UP* signal is asserted, charge stored in capacitor 905 is transferred to filter capacitor 115 to raise the voltage of Vctrl.
In the embodiment shown, the potential setting circuit includes a level shifter 941 (that includes transistors 942, 945, 947 and 949) whose output voltage (node 950) matches its input voltage (node 948). Node 948 is connected to node 916 of voltage generator 971. A level shifter is implemented so that the charging of capacitor 905 does not drain current from fractional voltage generator 971. If node 950 exceeds 4/3 Vctrl, transistors 945, 947, and 949 turn on to drain current from node 950 to reduce the voltage of node 950 back to 4/3 Vctrl. In the embodiment shown, the transistors 945, 947, and 949 are implemented with SOI transistors with their transistor bodies being connected as shown in FIG. 9. In other embodiments, other types of level shifters may be utilized.
Charge pump 901 also includes a potential setting circuit for setting the potential of node 910 to a voltage of 2/3 Vctrl when the DOWN signal is non asserted. This second potential setting circuit includes a pass gate 931 and a level shifter 951 similar to level shifter 941.
Charge pump 901 includes a fractional voltage generator 971 for generating fractional voltages of Vctrl, which are provided to level shifters 941 and 951. The fractional voltages generated are used to set the voltage levels of nodes 906 and 910 to fractions of Vctrl. Voltage generator 971 includes a comparator 913 whose inverting input is connected to receive the Vctrl signal and its non inverting input connected to the drain electrode of transistor 917. The output of comparator 913 is connected to the gate of transistor 915, which acts as a current source. In one embodiment, transistor 915 is smaller than transistors 917, 919, 921, and 923. Comparator 913 controls transistor 915 such that the voltage level at the drain of transistor 917 is equal to Vctrl. In the embodiment of
The circuit of
Charge pump 1001 includes an enabling transistor 1013, that when an enable signal (EN*) is non asserted, is non conductive such that capacitor 1007 is only coupled to ground via capacitor 1011 when the UP* signal is asserted. When the enable signal is non asserted (EN* is high), transistor 1013 is made conductive to short node 1012 to ground such that the charge path does not include capacitor 1011. When the enable signal (EN*) is asserted (EN* is low), transistor 1013 is non conductive such that charge flows from capacitor 1011 to capacitor 1007 when the UP* signal is asserted. As with the embodiment of
Charge pump 1001 also includes a second capacitor 1025 that is implemented in the discharge path when the enable signal (EN*) is asserted and the DOWN signal is asserted. When transistor 1023 is conductive due to the enable signal (EN*) being non asserted, node 1020 is shorted to ground thereby removing capacitor 1025 from the discharge path. When the enable signal (EN*) is asserted, charge is removed from Vctrl via capacitor 1021 and capacitor 1025 when the DOWN signal is asserted.
Charge pump 1001 also includes a potential setting circuit for setting the voltage of node 1008 to 4/3 Vctrl when the UP* signal is non asserted and includes a second potential setting circuit for setting the potential of node 1018 to 2/3 Vctrl when the DOWN signal is non asserted. Both potential setting circuits of charge pump 1001 each include a level shifter (1041 and 1051) that is similar to level shifter 941 of FIG. 9. Charge pump 1001 also includes a fractional voltage generator 1071 for providing a voltage that is 4/3 of Vctrl to level shifter 1041 and a voltage that is 2/3 of Vctrl to level shifter 1051. Fractional voltage generator 1071 is similar in design to fractional voltage generator 971 of FIG. 9.
Charge pump 1001 also includes another potential setting circuit that includes transistor 1009 for setting the voltage of node 1012 to ground when the UP* signal is non asserted. Charge pump 1001 includes still another potential setting circuit including transistor 1027 for setting the voltage of node 1020 to ground when the DOWN signal in non asserted.
Referring back to
In another modification of charge pump 901, nodes 906 and 910 would be set to VDD and ground, respectively, when the UP* signal and the DOWN signal are non asserted, respectively. These modifications would not utilize fractional voltage generator 971 (and in some embodiments level shifter 941 and level shifter 951). An example of a charge pump modified in such a way would appear similar to charge pump 111 of
When the UP* signal is asserted to provide charge to filter capacitor 115, pass gates 1111 and 1115 are conductive and pass gates 1113, 1118 and 1119 and transistor 1109 are non conductive to provide a charge path from capacitor 1105 via pass gate 1111, capacitor 1107, pass gate 115 to Vctrl. Because both capacitor 1107 and 1105 are precharged to have a voltage drop of 2/3 of Vctrl, the voltage at node 1108 when the UP* is first asserted is at 4/3 Vctrl. The UP signal and the DOWN signal are the inverted UP* signal and inverted DOWN signal, respectively, provided by inverters (not shown).
When the DOWN signal is asserted to remove charge from filter capacitor 115, pass gate 1113 is conductive and pass gates 1111, 1115, 1117 are non conductive to provide a discharge path from capacitor 115 to capacitor 1105 via pass gate 1113. Because capacitor 1105 is precharged to have a voltage drop of 2/3 Vctrl, the voltage at node 1106 is at 2/3 Vctrl when the DOWN signal is first asserted.
Charge pump 1101 includes potential setting circuits for setting the voltages at nodes 1108 and 1106 at 2/3 Vctrl when the DOWN signal and UP* signal are non asserted. Pass gate 1119 and transistor 1109 are conductive and pass gates 1111 and 1115 are non conductive with the UP* signal is non asserted to pull node 1108 to 2/3 of the voltage of Vctrl, thereby charging capacitor 1107 such that the voltage drop across capacitor 1107 is 2/3 Vctrl.
When the UP* is non asserted and the DOWN signal is non asserted, pass gates 1117 and 1118 are conductive and pass gates 1111 and 1113 are non conductive to pull node 1106 to 2/3 of the voltage of Vctrl, thereby charging capacitor 1105 such that the voltage drop across capacitor 1105 is 2/3 Vctrl.
Charge pump 1101 includes fractional voltage generator 1136 that includes transistors 1131, 1133, and 1135 and level shifter 1127. Fractional voltage generator 1136 has an input connected to receive the Vctrl signal and provides at an output to level shifter 1121 a voltage of 2/3 Vctrl. Level shifter 1121 signal, which is similar in design to level shifter 941, provides at its output a voltage of 2/3 Vctrl to pass gates 1119 and 1117.
Those of skill in the art will recognize that, based upon the teachings herein, several modifications may be made to the embodiments shown and described herein. For example a capacitive charge pump as shown in the Figures may be implemented with other types of devices e.g. such as with other types of transistors and/or have other types of configurations. Also, features shown or described with regard to one embodiment may be included in other embodiments shown or described herein. Also charge pumps shown or described herein may be implemented in other types of circuits such as is in control loops with feedback (e.g. power, temperature, or frequency control).
In one aspect of the invention, a charge pump includes an output node and a first capacitor having a first terminal coupled to a first circuit node. The charge pump also includes a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node. The first switch control signal controls charge transfer between the first capacitor and the output node.
In another aspect of the invention, a phase locked loop (PLL) circuit includes a filter capacitor and a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide a first clock control signal based on the first clock and the second clock. The phase locked loop circuit also includes a voltage controlled oscillator having an input coupled to a first terminal of the filter capacitor and an output to provide an output clock. The phase locked loop circuit further includes a charge pump having a first input to receive the first clock control signal and an output coupled to the first terminal of the filter capacitor and the input of the voltage controlled oscillator. The charge pump includes a first capacitor having a first terminal and a first switch having a first current electrode coupled to the first the first terminal of the first capacitor. The first switch also includes a control electrode coupled to receive the first clock control signal and a second current electrode coupled to the first terminal of the filter capacitor. The first switch selectively couples the first capacitor to the filter capacitor, based on the first clock control signal.
In another aspect of the invention, a charge pump includes an output node, a charge path including a first capacitor, and a first switch including a control electrode coupled to receive a first charge control signal. The first capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch.
The charge pump also includes a discharge path including a second capacitor and a second switch having a control electrode coupled to receive a second charge control signal. The second capacitor selectively receives charge, based on the second charge control signal, from the output node.
While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention.
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