Analog signal interpolation

Abstract

A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.

Description

TECHNICAL FIELD

This invention relates generally to the interpolation of analog signals, and more particularly to the linear interpolation of analog signals.

BACKGROUND

Interpolation of signals is widespread in fields such as image processing and communication. Accordingly, much effort has been expended in the development of methods and systems to perform the necessary interpolation. But this interpolation will generally occur digitally, i.e., either the desired amount of interpolation is a digital value and/or the signals being interpolated are digital signals. Surprisingly little development has occurred regarding the interpolation of analog signals.

This difference in the prior art between the development for interpolation of digital signals vs. the development for interpolation of analog signals is understandable given the widespread nature of digital systems. However, even in digital systems such as those used for digital communications, the need arises for interpolation of analog signals such as that which occurs in adaptive timing control and recovery schemes. Existing analog signal interpolators have proven to be inappropriate for use in these schemes because they typically provide non-linear interpolation that is subject to gain variation. However, linear interpolation is often required and is essential when implemented in adaptive timing control and recovery techniques.

Accordingly, there is a need in the art for improved techniques and devices for the linear interpolation of analog signals.

SUMMARY

In accordance with one aspect of the invention, a linear interpolator for interpolating a first input voltage V_in1 and a second input voltage V_in2 according to a factor r, wherein 0≦r≦1 is provided. The interpolator includes a first differential pair of transistors adapted to split a differential current proportional to V_in1 such that a first transistor in the first differential pair conducts a differential current proportional to r*V_in1 and a second transistor conducts a differential current proportional to (1−r)*V_in1 and a second differential pair of transistors adapted to split a current proportional to V_in2 such that a first transistor in the second differential pair conducts a differential current proportional to (1−r)*V_in2 and a second transistor in the second differential pair conducts a differential current proportional to r*V_in2. Advantageously, a voltage generated from the sum of the differential currents proportional to r*V_in1 and (1−r)V_in2 produces the desired linear interpolation.

In accordance with another aspect of the invention, a linear interpolator for interpolating a first input voltage V_in1 and a second input voltage V_in2 according to a factor r, wherein 0≦r≦1 is provided. The linear interpolator includes a first differential pair adapted to split a current proportional to r² such that a first transistor in the first differential pair conducts a differential current proportional to V_in1*r and a second transistor in the first differential pair conducts a differential current proportional to −V_in1*r; and a second differential pair adapted to split a current proportional to (1−r)² such that a first transistor in the second differential pair conducts a differential current proportional to V_in2*(1−r) and a second transistor in the first differential pair conducts a differential current proportional to −V_in2*(1−r).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual illustration of a generic linear interpolator.

FIG. 2 is a schematic illustration of a differential pair of transistor used to split a current according to a desired splitting factor r in response to a splitting input voltage.

FIG. 3 is a graphical representation of the relationship between the splitting factor r and the ratio of the splitting input voltage to the overdrive voltage for the differential pair of FIG. 2.

FIG. 4a is a schematic illustration of a linear interpolator according to an embodiment of the invention.

FIG. 4b is a schematic illustration showing output nodes in FIG. 4a coupling to a supply voltage Vcc through output resistors.

FIG. 5 is a schematic illustration of a linear interpolator according to another embodiment of the invention.

FIG. 6 is a block diagram of a linear interpolator arranged within a feedback loop according to another embodiment of the invention.

DETAILED DESCRIPTION

Referring now to FIG. 1, a linear interpolator 100 is provided for the linear interpolation of voltages V_in1 and V_in2. Interpolator 100 functions to provide an output voltage V_out that is a linear interpolation of the two input voltages based upon a factor r that may range between 0 and 1. The input voltage V_in1 is multiplied by a linear interpolation factor “r” in a multiplier 20 whereas input voltage V_in2 is multipled by the complement factor (1−r) in a multiplier 25. The resulting outputs of multipliers 20 and 25 are summed in a summer 30 to produce an output voltage V_out that equals the summation of r*V_in1 and (1−r)*V_in2. Linear interpolator 100 has many uses such as in a variable delay cell wherein V_in1(t) equals V_in2(t−j), where j is a variable delay factor.

To provide the interpolation according to variable factor r, linear interpolator 100 exploits the current splitting property of differential pairs. For example, a differential pair 200 of matched NMOS transistors is shown in FIG. 2. A current source I biases an NMOS transistor 205 and an NMOS transistor 210. The resulting current and gate-to-source voltage (V_gs) from this biasing will be the same for each transistor 205 and 210. A splitting voltage V_r is applied across the gates of NMOS transistors 205 and 210. Thus, with respect to NMOS transistor 205, it is as if its bias voltage Vgs has been altered by an additional voltage V_r+ equaling V_r/2. Similarly, with respect to NMOS transistor 210, it is as if its bias voltage V_gs has been altered by the addition of a voltage V_r− equaling −V_r/2, where V_r=(V_r+−V_r−). Because transistors 205 and 210 are matched, if the voltage V_r is zero, each will conduct of I/2. However, as V_r is increased positively from zero, more and more current will be steered to transistor 205 and away from transistor 210. In general, depending upon the value of V_r, an arbitrary portion r of current I flows in transistor 205 and the complement of this portion (namely, 1−r) of current I flows in transistor 210. It can be shown that the factor r is given by
r=½*[1+sqrt{m*(1−m/4)}]  Eq (1)
where the factor m is given by
m=(V_r/ΔV)²  Eq. (2)
and where the factor ΔV is denoted as the overdrive voltage and equals the difference between V_gs and the transistors' 205 and 210 threshold voltage. As can be seen from equations (1) and (2), by proper selection of the splitting voltage V_r, the current splitting factor r may be arbitrarily varied in the range 0≦r≦1. The variation of the splitting factor r as a function of V_r/ΔV is shown in FIG. 3. In addition, although described with respect to MOS transistors, equations analogous to equations (1) and (2) may be derived for the current splitting properties of differential pair of bipolar transistors as well.

The current splitting behavior of a differential pair as determined through equation (1) may be implemented in a linear interpolator in a number of fashions. For example, FIG. 4a illustrates a linear interpolator 400 having six differential pairs of transistors. A differential pair 401 responds to an input voltage V_in1 whereas a differential pair 405 responds to an input voltage V_in2. Differential pairs 401 and 405 are each biased to provide a current I through operation of matched transistors M1 through M3. Transistor M1 is driven by a current source 410 with a current I and couples in a current mirror configuration to transistors M2 and M3 such that these transistors will also conduct a current I (or a current proportional to current I depending upon the relative channel sizes). The following discussion will assume that the channel dimensions of transistors M1 through M3 are the same such that each will conduct the same current I.

Differential pair 401 supplies the current I to transistor M2 whereas differential pair 405 supplies the current I to transistor M3. Thus, current source 410 acts to bias transistors M4 and M5 in differential pair 401 with the same gate-to-source voltage (V_gs) analogously as discussed with respect to FIG. 2. Similarly, current source 410 acts to bias transistors M6 and M7 in differential pair 405 with the same gate-to-source voltage V_gs. Thus, current source 410 sets the DC bias voltage V_gs for transistors M4 through M7. The input voltages V_in1 and V_in2 act to alter V_gs analogously to the operation of V_r as discussed with respect to FIG. 2. In other words, input voltage V_in1 may be broken down into equal and opposite differential components V_in1+=V_cm+V_in1/2 and V_in1=V_cm−V_in1/2 such that V_in1 equals equals (V_in1+−V_in1−), where V_cm is the common mode voltage required to bias the transistors. Similarly, V_in2 may be decomposed into equal and opposite differential components V_in2+=V_cm+V_in2/2 and V_in2−=V_cm−V_in2/2 such that V_in2 equals (V_in2+−V_in2−). The gates of transistors M4 and M5 in differential pair 401 may be considered to receive differential input voltages V_in1+ and V_in1−, respectively. The gates of transistors M6 and M7 in differential pair 405 may be considered to receive differential input voltages V_in2+ and V_in2−, respectively.

Transistors M4 and M5 in differential pair 401 will thus each pass a current I/2 if input voltage V_in1 is zero. Similarly, transistors M6 and M7 in differential pair 405 will each pass a current I/2 if input voltage V_in2 is zero. As input voltages V_in1 and V_in2 are increased positively, more and more current will be steered to transistors M4 and M6, respectively. Using the transconductance gm for transistors M4 and M5, the current excited through each transistor in response to the input voltage V_in1 is given by (I/2+gm*V_in1/2) and (I/2−gm*V_in1/2), respectively. Similarly, the current excited through each transistor M6 and M7 in response to input voltage V_in2 is given by (I/2+gm*V_in2/2) and (I/2+gm*V_in2/2), respectively.

Since I/2 is a constant, the following discussion will ignore this current and consider only the currents induced by the input voltages V_in1 and V_in2. Since these input voltages are applied differentially, as used herein, the currents induced by the input voltages Vi_n1 and V_in2 shall be denoted as “differential currents.” In this regard, transistor M4 conducts a differential current of gm*V_in1/2 whereas transistor M5 conducts a differential current of −gm*V_in1/2. Similarly, transistor M6 conducts a differential current of gm*V_in2/2 whereas transistor M7 conducts a differential current of −gm*V_in2/2.

The respective differential currents through transistors M4, M5, M6, and M7 may be split as discussed with respect to FIG. 2 using differential pairs 415, 420, 425, and 430, respectively. For example, differential pair 415 supplies the current conducted through transistor M4. The splitting voltage V_r (equaling differential component voltages V_r+−V_r−) is applied across transistors M8 and M9 in differential pair 415. Thus, differential current gm*V_in1/2 is split into a portion r*gm*V_in1/2 that passes through transistor M8 and a portion (1−r)*gm*V_in1/2 that passes through transistor M9. Similarly, differential pair 420 supplies the current conducted through transistor M5. The splitting voltage V_r is applied across transistors M11 and M10 in differential pair 420. Thus, differential current −gm*V_in1/2 is split into a portion −r*gm*V_in1/2 that passes through transistor M11 and a portion −(1−r)*gm*V_in1/2 that passes through transistor M10.

Differential pairs 425 and 430 split the differential currents corresponding to input voltage V_in2 in the same fashion. For example, differential pair 425 supplies the current conducted through transistor M6. The splitting voltage V_r (equaling V_r+−V_r−) is applied across transistors M12 and M13 in differential pair 425. Thus, differential current gm*V_in2/2 is split into a portion r*gm*V_in2/2 that passes through transistor M12 and a portion (1−r)*gm*V_in2/2 that passes through transistor M13. Similarly, differential pair 430 supplies the current conducted through transistor M7. The splitting voltage V_r is applied across transistors M15 and M14 in differential pair 430. Thus, differential current (−1)*gm*V_in2/2 is split into a portion −r*gm*V_in2/2 that passes through transistor M15 and a portion −(1−r)*gm*V_in2/2 that passes through transistor M14. Note the symmetry exhibited by the differential currents in the pair of differential pairs 415 and 420 and also in the pair of differential pairs 425 and 430. For example, the differential currents through transistors M11 and M10 are the opposites of the corresponding differential currents through transistors M8 and M9, respectively.

Having split the differential currents in this fashion, they may be combined as follows to produce the desired interpolation of input voltages V_in1 and V_in2. A node A supplies the currents to transistors M8 and M13. Thus, a current I_out+ through node A equals r*gm*V_in1/2+(1−r)*gm*V_in2/2. Similarly, a node D supplies the currents to transistors M11 and M14 so that a current I_out− through node D equals −(r*gm*V_in1/2+(1−r)*gm*V_in2/2). Each node A and D may couple to a supply voltage VCC through loads such as separate resistors of equal resistances R as shown in FIG. 4b. Thus, a voltage V_out+ at node A equals VCC−R*(r*gm*V_in1/2+(1−r)*gm*V_in2/2). Similarly, a voltage V_out− at node D equals VCC+R*(r*gm*V_in1/2+(1−r)*gm*V_in2/2). In general, loads of arbitrary impedance may be used in place of the resistors. For example, active, inductive, or capacitive loads could be used to produce the voltages V_out+ and V_out−. By combining these voltages to provide an output voltage V_out equaling V_out−−V_out+, the output voltage V_out is proportional to the desired linear interpolation of input voltages V_in1 and V_in2 such that V_out equals k*(rV_in1+(1−r)V_in2), where k equals R*gm. Similarly, voltages V₊ and V₋ may be produced at nodes B and C, respectively. The complementary output voltage thus equals (V₋−V₊), which equals k*((1−r)V_in1+rV_in2). It will be appreciated that linear interpolator 400 shown in FIG. 4 is merely an exemplary embodiment that may be modified in a number of fashions. For example, MOS transistors M1 through M15 may be replaced by bipolar transistors. In addition, an alternative topology for a linear interpolator 500 is shown in FIG. 5.

Linear interpolator 500 in FIG. 5 exploits the property of a MOS transistor wherein its transconductance is proportional to the square root of the current passed through the MOS transistor. For example, if a MOS transistor passes a current proportional to the square of the splitting factor r², its transconductance (denoted as gm) will be proportional to splitting factor r. Similarly, if a MOS transistor passes a current proportional to the square of the complement of the splitting factor (1−r)², its transconductance gm will be proportional to the complement of the splitting factor (1−r). In linear interpolator 500 of FIG. 5, a differential pair 501 splits a current I provided by a current source 505. Transistors M16 and M17 in differential pair 501 receive differential input voltages V_r+ and V_r−, respectively, as their gate voltages corresponding to splitting voltage V_r. Transistor M16 provides a current r*I to a differential pair 510 consisting of transistors M18 and M19. The gate of transistor M18 receives differential input voltage V_r+ whereas the gate of transistor M19 receives differential input voltage V_r−. Thus, transistor M18 will conduct a current proportional to r²*I.

A corresponding current (1−r)²I may be produced as follows. Transistor M17 in differential pair 501 provides a current (1−r)I to a differential pair 520 consisting of transistors M20 and M21. Transistor M21 receives differential voltage V_r− as its gate voltage such that it conducts the current (1−r)²I. Currents r²I and (1−r)²I are received at matched transistors M22 and M23. A pair of matched transistors M24 and M25 are coupled in a current-mirror configuration to matched transistors M22 and M23, respectively. Thus, transistor M24 will conduct a current equal or proportional to r²I, depending upon the matching between the transistors. Similarly, transistor M25 will conduct a current equal or proportional to (1−r)²I. A differential pair 525 consisting of transistors M26 and M27 provides the current to transistor M24. Similarly, a differential pair 530 consisting of transistors M28 and M29 provides the current to transistor M25. Thus, the transconductance for transistors M26 and M27 will be proportional to r whereas the transconductance for transistors M28 and M29 will be proportional to (1−r). Input voltage V_in1 is applied across transistors M26 and M27 such that the gate of transistor M26 receives differential input voltage V_in1+ whereas the gate of transistor M27 receives differential input voltage V_in1−. Similarly, input voltage V_in2 is applied across transistors M28 and M29 such that the gate of transistor M28 receives differential input voltage V_in2+ whereas the gate of transistor M29 receives differential input voltage V_in2−. In this fashion, transistors M26 and M27 conduct differential currents proportional to r*V_in1/2*I and −r*V_in1/2*I, respectively. Similarly, transistors M28 and M29 conduct differential currents proportional to (1−r)*V_in2/2*I and −(1−r)*V_in2/2*I, respectively. A node E supplies the currents to transistors M26 and M28. Similarly, a node F supplies the currents to transistors M27 and M29. Each node E and F may couple to VCC through identical resistors (not illustrated) having a resistance R in an analogous fashion discussed with respect to FIG. 4b. In general, loads of arbitrary impedance may be used in place of the resistors. For example, active, inductive, or capacitive loads could be used to couple these nodes to VCC. A voltage V₊ at node E is proportional to VCC−R*(rV_in1/2+(1−r)*V_in2/2). Similarly, a voltage V₋ at node F is proportional to VCC+R*(rV_in1/2+(1−r)*V_in2/2). By combining these voltages to provide an output voltage V_out equaling V₋−V₊, the output voltage V_out is proportional to the desired linear interpolation of input voltages V_in1 and V_in2 such that V_out is proportional to (rV_in1+(1−r)V_in2). Referring back to transistors M19 and M20, each provides a mixed current r(1−r)I. Although these mixed currents are unneeded, they are dumped to ground through diode-connected matched transistors M30 and M31, respectively, to maintain the biasing in differential pairs 510 and 520. For example, if transistor M19 passed its current directly to ground, the DC biasing for transistors M18 and M19 in differential pair 510 would be different, thereby preventing a differential pair current splitting operation as discussed with respect to FIG. 2.

Regardless of the topology used, it will be appreciated that linear interpolators in accordance with the present invention are configurable to provide a linear interpolation of input voltages V_in1 and V_in2 according to an arbitrary splitting factor r, where 0≦r≦1. In turn, this arbitrary splitting factor r is driven by the ratio between splitting voltage V_r and the overdrive voltage as discussed with respect to FIGS. 2 and 3. As can be seen from FIG. 3, r depends non-linearly upon V_r, thus making it difficult to specify a straightforward mapping between V_r and the desired splitting factor r. By incorporating linear interpolator 10 within a feedback loop 600 as seen in FIG. 6, the necessary level for V_r to provide a desired splitting factor r may be readily achieved. From linear interpolator 10, the actual splitting factor r being used to interpolate input voltages V_in1 and V_in2 may be derived. An error amplifier 605 receives splitting factor r derived from linear interpolator 10 and compares it to a desired splitting factor r⁰ to generate an error signal 610. A generator 620 for splitting voltage V_r receives error signal 610 and adjusts the level for splitting voltage V_r accordingly. For example, as can be surmised from FIG. 2, a simple negative feedback mechanism may be used to adjust V_r. Thus, if splitting factor r is less than r⁰, error signal 610 is such that V_r is increased. Alternatively, if splitting factor r is greater than r⁰, error signal 610 is such that V_r is decreased. In this fashion, the level of V_r is adjusted until the desired splitting factor is achieved.

Although the invention has been described with respect to particular embodiments, this description is only an example of the invention's application and should not be taken as a limitation. Consequently, the scope of the invention is set forth in the following claims.

Claims

1. A linear interpolator for interpolating a first input voltage v_in1 and a second input voltage v_in2 according to a factor r, wherein 0≦r≦1, comprising:

a first differential pair of transistors adapted to split a differential current proportional to v_in1 such that a first transistor in the first differential pair conducts a differential current proportional to r*v_in1 and a second transistor conducts a differential current proportional to (1−r)*v_in1; and

a second differential pair of transistors adapted to split a current proportional to v_in2 such that a first transistor in the second differential pair conducts a differential current proportional to (1−r)*v_in2 and a second transistor in the second differential pair conducts a differential current proportional to r*v_in2.

2. The linear interpolator of claim 1, further comprising:

a third differential pair of transistors adapted to split a differential current proportional to −V_in1 such that a first transistor in the third differential pair conducts a differential current proportional to −r*v_in1 and a second transistor in the third differential pair conducts a differential current proportional to (1−r)*v_in1; and

a fourth differential pair of transistors adapted to split a differential current proportional to −V_in2 such that a first transistor in the fourth differential pair conducts a differential current proportional to −(1−r)*v_in2 and a second transistor in the fourth differential pair conducts a current proportional to −r*v_in2.

3. The linear interpolator of claim 2, wherein the first and second transistors in the first and second differential pairs are MOS transistors.

4. The linear interpolator of claim 2, wherein the first and second transistors in the first and second differential pairs are bipolar transistors.

5. The linear interpolator of claim 2, further comprising:

a first load coupled between a supply voltage and the first transistors in the first and second differential pairs such that the differential currents conducted by the first transistors in the first and second differential pairs are supplied through the first load, thereby inducing a first voltage across the first load.

6. The linear interpolator of claim 5, further comprising:

a second load coupled between the supply voltage and the first transistors in the third and fourth differential pairs such that the differential currents conducted by the first transistors in the third and fourth differential pairs are supplied through the second load, thereby inducing a second voltage across the second resistor, and wherein the difference between the second and first voltages is proportional to r*v_in1+(1−r)v_in2.

7. The linear interpolator of claim 6, wherein the impedances of the first and second loads are equal.

8. The linear interpolator of claim 2, further comprising a fifth differential pair of transistors adapted to split a current such that a first transistor in the fifth differential pair conducts the differential current proportional to v_in1 that is split by the first differential pair and such that a second transistor in the fifth differential pair conducts the differential current proportional to −V_in1 that is split by the third differential pair.

9. The linear interpolator of claim 8, further comprising a sixth differential pair of transistors adapted to split a current such that a first transistor in the sixth differential pair conducts the differential current proportional to v_in2 that is split by the second differential pair and such that a second transistor in the sixth differential pair conducts the differential current proportional to −V_in2 that is split by the fourth differential pair.

10. The linear interpolator of claim 9, wherein the current split by the fifth differential pair equals the current split by the sixth differential pair.

11. A linear interpolator for interpolating a first input voltage v_in1 and a second input voltage v_in2 according to a factor r, wherein 0≦r≦1, comprising:

a first differential pair adapted to split a differential current proportional to r² such that a first transistor in the first differential pair conducts a differential current proportional to v_in1*r and a second transistor in the first differential pair conducts a differential current proportional to −V_in1*r; and

a second differential pair adapted to split a differential current proportional to (1−r)² such that a first transistor in the second differential pair conducts a differential current proportional to v_in2*(1−r) and a second transistor in the second differential pair conducts a differential current proportional to −V_in2*(1−r).

12. The linear interpolator of claim 11, further comprising:

a first load coupled between a supply voltage and the first transistors in the first and second differential pairs such that the differential currents conducted by the first transistors in the first and second differential pairs are supplied through the first load, thereby inducing a first voltage across the first load.

13. The linear interpolator of claim 12, further comprising:

a second load coupled between the supply voltage and the second transistors in the first and second differential pairs such that the differential currents conducted by the second transistors in the first and second differential pairs are supplied through the second load, thereby inducing a second voltage across the second load, and wherein the difference between the second and first voltages is proportional to r*v_in1+(1−r)v_in2.

14. The linear interpolator of claim 11, further comprising:

a third differential pair adapted to split a current such that a first transistor in the third differential pair conducts a differential current proportional to r and a second transistor in the third differential pair conducts a differential current proportional to (1−r).

15. The linear interpolator of claim 14, further comprising: a fourth differential pair adapted to split the differential current from the first transistor in the third differential pair such that a first transistor in the fourth differential pair conducts the differential current proportional to r² that is split by the first differential pair.

16. The linear interpolator of claim 15, further comprising a fifth differential pair adapted to split the differential current from the second transistor in the third differential pair such that a first transistor in the fifth differential pair conduct the differential current proportional to (1−r)² that is split by the second differential pair.