A method for manufacturing a semiconductor device including an electrode having a lower silicon layer and an upper silicon layer which is formed on the lower silicon layer. A concentration of impurities in the upper silicon layer is higher than a concentration of impurities in the lower silicon layer.
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8. A method for manufacturing a semiconductor device including a transistor and memory capacitor connected to the transistor, comprising:
providing a semiconductor base;
forming source and drain regions of the transistor in a surface of the semiconductor base;
forming an insulating layer on the semiconductor base, the insulating layer including a contact hole located over the source region or the drain region;
filling an entirety of the contact hole with a first layer containing silicon; and
forming a second layer containing silicon on the first layer, the second layer having an impurity concentration which is higher than an impurity concentration of the first layer,
wherein an interface between the first layer and the second layer is located outside of the contact hole, wherein edges of the first layer that extend in a first direction are substantially aligned with edges of the second layer that extend in the first direction, and wherein the first direction is substantially perpendicular to a channel direction that extends from the source region to the drain region.
1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor base;
forming source and drain regions in a surface of the semiconductor base;
forming an insulating layer having a contact hole over the surface of the semiconductor base, wherein the contact hole is aligned over the source region or the drain region;
forming a first silicon layer over the insulating layer such that the first silicon layer entirely fills the contact hole;
forming a second silicon layer on the first silicon layer, wherein a concentration of conductive impurities in the second silicon layer is higher than a concentration of conductive impurities in the first silicon layer; and
patterning the first and second silicon layers in a same patterning process, wherein edges of the patterned first silicon layer that extend in a first direction are substantially aligned with edges of the patterned second silicon layer that extend in the first direction, wherein the first direction is substantially perpendicular to a channel direction that extends from the source region to the drain region.
2. The method according to
3. The method according to
4. The method according to
forming a third silicon layer on the insulating layer;
removing a part of the third silicon layer to form a gap therein which exposes a part of the insulating layer located above the source region or the drain region;
forming a side wall layer on an interior surface of the gap in the third silicon layer; and
forming the contact hole to expose the source region or the drain region using the side wall layer and the third silicon layer as a mask.
5. The method according to
6. The method according to
forming a third silicon layer on the insulating layer;
removing a part of the third silicon layer to form a gap therein which exposes a part of the insulating layer located above the source region or the drain region;
forming a side wall layer on an interior surface of the gap in the third silicon layer; and
forming the contact hole to expose the source region or the drain region using the side wall layer and the third silicon layer as a mask.
7. The method according to
covering an upper surface of the second silicon layer and side surfaces of the first silicon layer and the second silicon layer with a dielectric layer; and
forming a polycrystalline silicon layer on the dielectric layer.
9. The method according to
roughening a surface of the second layer in an atmosphere which is introduced with silane at a temperature of 560–580° C.; and
introducing an impurity into the roughened second layer.
10. The method according to
forming a third layer containing silicon on the insulating layer;
removing a part of the third layer to form a gap therein which exposes a part of the insulating layer located above the source region or the drain region;
forming a side wall layer on an interior surface of the gap in the third layer; and
forming the contact hole to expose the source region or the drain region using the side wall layer and the third layer as a mask.
11. The method according to
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This a divisional of and claims priority to U.S. application Ser. No. 09/497,861, filed Feb. 4, 2000, now U.S. Pat. No. 6,589,885 the entirety of which are incorporated herein by reference.
The present invention relates to a semiconductor device and method of manufacture, and particularly, the present invention relates to a semiconductor memory device having a capacitor which includes a silicon layer having introduced impurities therein, and to a method of manufacturing such a semiconductor memory device.
In a semiconductor device, a silicon layer is used in various portions, such as a conductive layer, a resistant element, a gate electrode of transistor, and a capacitor of a memory cell. As is well known, in a Dynamic Random Access Memory (DRAM), a capacitor of the memory cell is comprised of a silicon layer. The silicon layer composes a storage electrode and a cell-plate electrode of the capacitor. A method for manufacturing such capacitors of the DRAM is shown in Japanese Laid Open Patent “Toku-Kai-Hei 7-235616”, which was published on Sep. 5th, 1995.
In the DRAM of the publication, the silicon storage electrode of the capacitor is composed of a polycrystalline silicon layer and an amorphous silicon layer. Generally, if the silicon layers are applied as the conductive layers, the silicon layers are introduced with an impurity having a high concentration in order to reduce the resistance and maintain good conduction therein. In the polycrystalline silicon layer of the publication, which is connected to diffusion regions (source or drain of transistors) formed in a semiconductor substrate, a conductive impurity having a deep concentration is introduced therein.
In heat treatment processes after forming the storage electrode including the silicon layer which is introduced with the deep impurity, the impurity in the silicon layer is frequently diffused in the semiconductor substrate. The diffused impurity influences an impurity concentration of the diffusion region (source or drain) formed below the storage electrode. Also, the diffused impurity brings an unexpected extension of the diffusion region during the heat treatment after forming the storage electrode.
Therefore, the characteristics of the transistors, typically a threshold voltage of the transistor, is changed to unexpected results.
If an excess of the impurity is introduced into the silicon layer, the impurity can easily diffuse into the semiconductor substrate. As above, the characteristics of the transistors are then influenced.
The smaller the size of the DRAM, the more significant is the leakage current that occurs under a field oxidation layer. Such diffusing of the impurity accelerates the leakage current. Therefore, the date-retention-time may be shorten to less than a predetermined desired date-retention-time.
An object of the present invention is to provide a semiconductor device which is capable of reducing adverse influences to characteristics of the transistor and securing a predetermined data-retention-time.
Another object is to provide a method of manufacturing such semiconductor device without the addition of many process steps.
To achieve the objects, in a semiconductor device having a silicon, the silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer, wherein a concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.
According to the present invention, a semiconductor device is realized which is capable of reducing changes in characteristics of the device.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:
The present invention will be described hereinafter with reference to the accompanying drawings. The drawings used for this description typically illustrate major characteristic parts in order that the present invention will be easily understood. In this description, one embodiment is shown in which the present invention is applied to a DRAM (Dynamic Random Access Memory).
N-type diffusion regions 3 (source or drain of a transistor in the memory cell) are formed in a semiconductor substrate 1. A P-type semiconductor substrate or P-type well is used as the semiconductor substrate in this embodiment.
A gate oxide film 15 and a field oxide film 5 which is thicker than that of the gate oxide film 15, are formed in and on the surface of the substrate 1. As is well known, the gate oxide film and field oxide film are an oxidized silicon.
A gate electrode 7 of the transistor of the memory cell is formed on the gate oxide film 15 which is located between the n-type diffusion regions 3. The gate electrode 7 is comprised of polycrystalline silicon.
A first intermediate insulating film 9 is formed on the gate oxide film 15, the field oxide film 5 and the gate electrode 7. The first intermediate insulating layer film 9 is comprised of an oxidized silicon or a BPSG film.
A bit line 21 is formed on the first insulating film 9. This bit line is electrically connected to the diffusion region 3 (one of the source or drain of the transistor in the memory cell) through a contact hole CH1 formed in the first insulating film 9.
A second intermediate insulating layer 11 is formed on the bit line 21. The second intermediate insulating layer film 9 is comprised of an oxidized silicon or BPSG film. A contact hole CH2 is formed to be through the first and second insulating layers 9,11, and reaches to the diffusion region 3 (the other of the source or drain, which is not connected to the bit line 21).
The capacitor of the first preferred embodiment includes a storage node electrode which is comprised of a first silicon later 51 and a second silicon layer 53, a capacitor dielectric layer which is comprised of a nitride layer 57 and a cell plate electrode which is comprised of silicon layer 59. In this preferred embodiment, the first and silicon layers 51,53 and the silicon layer 59 are a polycrystalline silicon. Other silicon materials, for example amorphous silicon, can be used as the second silicon layer 53. However, in consideration of the adherence and interaction between the lower layer (the first silicon layer 51) and the upper layer (the second silicon layer 53), the use of polycrystalline silicon is preferable.
The first silicon layer 51 is filled in the contact hole CH2 which is formed in the first and second insulating layers 9 and 11. The first silicon layer 51 extends to the surface of the second insulating layer 11 in the vicinity of the contact hole CH2. The second silicon layer 53 is formed on the first silicon layer 51. Therefore the storage electrode, which is comprised of these silicon layers, is electrically connected to the diffusion region 3 (either the source or drain which is not connected to the bit line 21) through the contact hole CH2.
In order to cover the storage electrode, the nitride layer 57 is formed to extend from the surface of the second insulating layer 11 to the upper surface of the second silicon layer 53 through the side surfaces of the first and second silicon layers 51,53. The silicon layer 59 is formed on the nitride layer 57 and covers the storage electrode through the nitride layer 57. The silicon layer 59 (cell plate electrode) is patterned in the vicinity of the storage electrode as shown in
The first silicon layer 51, which forms the lower portion of the storage electrode, is not introduced with an impurity or is introduced with an impurity having a lower concentration than that of the second silicon layer 53. Thus, if an excess of the impurity is introduced into the second silicon layer 53, it is difficult for the impurity to diffuse in the semiconductor substrate since the first silicon layer 51, which is not introduced with an impurity or is introduced with the small concentration of impurity, is arranged between the second silicon layer 53 and the substrate 1. In this embodiment, the impurity is a conductive impurity which provides a conductivity to the silicon layer, for example phosphorus.
Therefore, especially in the DRAM, it is possible to restrain the adverse influences on the date-retention-time.
As mentioned above, the first silicon layer 51 includes no impurities or a small impurity concentration. However, in the case where an impurity is introduced to the first silicon layer 51, the concentration of the impurity may be set within limits. In this case, an upper limit of the concentration is set such that the impurity would not diffuse into the substrate more than a predetermined amount, and the lower limit is set to avoid a reduction in effective capacitance that occurs as the result of the widening of an extremity depletion layer which forms in the lower portion of the storage electrode.
In this embodiment, the lower limit of the lower layer is set at 2×1020/cm3 and the upper limit of the lower layer is set at 5×1020/cm3. Likewise, the upper layer concentration would be set within upper and lower limits. The upper limit is set such that the impurity would not diffuse into the substrate more than a predetermined amount. In this embodiment, the upper limit is about 5×1020/cm3. The lower limit of the upper layer concentration is set to be greater than the concentration of the lower layer, which is this embodiment is at least 2×1020/cm3.
According to the figure of the storage electrode, another structure can be considered, that is, a part of the second silicon layer 53 is fallen in the contacting hole CH2 shown in
It is preferable to use the same material, for example polycrystalline silicon, according to the first silicon layer 51 and the second silicon layer 53 in order to control the diffusing of the impurity having the high concentration. That is, it is easy to think about the diffusing and expanding of the impurity, if the same material would be used.
A method of manufacturing the semiconductor device described above, will be shown hereinafter referring to
In
In
In
It is possible to advance to the next step without introducing an impurity into the polycrystalline silicon 71. However, in this embodiment, an impurity at a concentration which is lower than that of a polycrystalline layer 81 mentioned below is introduced to the polycrystalline silicon 71. Phosphorus (P) is used as the impurity in this embodiment. The concentration of the phosphorus is within 2×1020/cm3–5×1020/cm3. An ion implantation method is used to introduce the impurity and then, an anneal process is carried out for about thirty minutes in a N2 atmosphere at 850° C. The anneal process activates the impurities introduced into the polycrystalline layer silicon 71. Thus, the polycrystalline layer silicon 71 becomes conductive.
Also, it is possible to deposit a polycrystalline silicon which has been introduced with an impurity in advance. Such deposition can be realized using a LPCVD (Low Pressure Chemical Vapor Deposition) method. If this method is used, separate steps of impurity introduction and annealing could be omitted.
Then, a polycrystalline silicon layer 81 is formed on the polycrystalline silicon layer 71 as shown in
A resist layer 91 is then formed on the polycrystalline silicon layer 81 and is patterned such that portions thereof above the storage electrode mentioned below, as shown in
Then, the polycrystalline silicon layers 81 and 71 are etched using the resist layer 91 as a mask, as shown in
Then, a dielectric layer 57, in this embodiment a nitride layer, is formed on the second insulating layer 11 and on the sides and upper surfaces of the first and second silicon layers 51 and 53, as shown in
Then, a polycrystalline silicon layer 59 is formed on the nitride layer 57 and is patterned to form a cell-plate electrode, as shown in
After forming other insulating layers and conductive lines (not shown in the figures), the semiconductor device mentioned above is completed.
According to the first preferred embodiment of the present invention, as the lower portion of the storage electrode, that is the first silicon layer 51, includes the conductive impurity which is less than that of the upper portion of the storage electrode, diffusion of the impurities of the silicon layer of the storage electrode is restrained. Especially, it is difficult for the impurity introduced in the upper portion of the storage electrode (that is the second silicon layer 53 in this embodiment) to diffuse into the diffusion region 3 of the substrate 1.
In this embodiment, the first and second silicon layers are used to form the storage electrode. However, a single silicon layer may be used as the storage electrode, in which case a conductive impurity could be introduced into the single silicon layer so as to be unevenly distributed such that most of the impurity exists in the upper portion of the single silicon layer.
According to the invention, as the difference in the concentration of the impurities which are introduced in the silicon layers is relatively easy to achieve, the addition of many new process steps is not necessary.
If the first and second silicon layers 51 and 53 are comprised of the same material, for example a polycrystalline silicon, the process steps are complex, compared with using different materials.
According to the present invention, it is possible to provide a semiconductor device which is capable of reducing adverse influences to the characteristics of the transistors and secure a predetermined data-retention-time.
Further, it is possible to realize a method of manufacturing such a semiconductor device without the addition of many process steps.
The first embodiment is described relative to the capacitor of the DRAM. The present invention can also be applied for the structure of the gate electrodes of transistors.
In the second preferred embodiment, the surface of the second silicon layer 153 is roughened. That is, the second silicon layer 153 of the storage electrode has a rugged surface 163. Also, the nitride layer 57 formed on the rugged surface 163 has a configuration which according to the rugged surface 163.
According to this embodiment, as an effective surface area can be increased, the capacitance of the capacitor is increased, compared with the first preferred embodiment. Therefore, a sufficient capacitance which can restrain a soft error in the DRAM is realized.
A method of manufacturing the second embodiment will be shown hereinafter referring to
After forming the second silicon layer 81 which is introduced the impurity (phosphorous) on the first silicon layer 71, a rugged polycrystalline silicon layer 160 is formed on the second silicon layer 81. The thickness of the rugged polycrystalline silicon 160 is 500–1000 Å. The rugged polycrystalline silicon layer 160 can be formed in an atmosphere which is introduced with silane SiH4 at a temperature of 560–580° C. Then an anneal treatment is carried out, and the rugged polycrystalline silicon layer 160 becomes conductive. Also, after forming the storage electrode by patterning, the patterned surface of the polycrystalline silicon layer 81 can be roughened.
A resist layer is formed on the rugged polycrystalline silicon layer 160 and is patterned such that a part of the resist layer 170 remains above the storage electrode, as shown in
Then, the rugged polycrystalline silicon layer 160 and the polycrystalline layers 81 and 71 are etched using the resist layer 170 as a mask, as shown in
Then, the nitride layer 57 is formed on the second insulating layer 11 and on the sides and upper surfaces of the first and second silicon layers 51 and 153. In this embodiment, the nitride layer 57 is formed on the rugged surface 163 so as to correspond to the rugged surface 163. After this step, the description on the first embodiment can be referenced.
According to the second embodiment, by the addition of the step which forms the rugged surface, an increased capacitance can be realized.
As the rugged surface 163 is formed by the same material (polycrystalline silicon), the adherence between the rugged surface 163 and the silicon layer 153 is efficient. Using the same material reduces the process become complexity, compared with using different materials.
A side wall layer 201 is formed on the sides of the first and second insulating layers in the contact hole which is filled with the first silicon layer.
The side wall layer 201 is comprised of a polycrystalline silicon which is not introduced with a conductive impurity. The side wall 201 makes it possible to form a contact hole having a small width than that which is obtainable by an optical aligner.
Also, the side wall 201 can be comprised of an oxide layer or a nitride layer. If a part of the gate electrodes 7 located in the vicinity of the contact hole is exposed in the contact hole during formation of the contact hole, the exposed part of the gate electrodes could be covered by the insulating side wall 201. As such, a short circuit between the gate electrode and the storage electrode is prevented.
A method of manufacturing the third embodiment will be shown hereinafter referring to
After the etching step using a resist layer 211 (corresponds to the resist layer 60) as a mask shown in
Then, the protection layer 213 is etched by anisotropic etching and the side wall 201 remains on the side of the contact hole, shown in
The resist layer 211 can be removed before forming the protection layer 213. If the material of the side wall 201 is the same as the second insulating layer 11, however, it is necessary for the resist layer 211 to remain to protect the second insulating layer 11 during etching of the protection layer 213.
The third embodiment can be applied to the second embodiment. The resultant structure is shown in
According to this combination, the effects of both the second and third embodiments can be obtained. A method of manufacturing of this combination can be understood easily from the description mentioned above.
A silicon layer 401 and a side wall 403 which both comprise a polycrystalline silicon is arranged between the second insulating layer 11 and the first silicon layer 51, as shown in
According to the fourth embodiment, the contact hole CH2 can be formed using the silicon layer 401 and the side wall 403 as a mask. Therefore, it is possible to form a contact hole which has a smaller size than that obtained by an optical aligner, in addition to the effect which is obtained by the first preferred embodiment. Further, as the silicon layer 401 can be used as a part of the storage electrode, the capacitance may be increased according to the thickness of the silicon layer 401. The silicon layer 401 and the side wall 403 are not limited to polycrystalline silicon. However, it is preferable for adherence between the layers 401, 403 and the first silicon layer 51 to use the same material.
A method of manufacturing the fourth embodiment will be shown hereinafter referring to
A polycrystalline silicon layer 410 for the silicon layer 401 is formed on the second insulating layer 11 using a CVD method, as shown in
A resist layer 420 is formed on the polycrystalline silicon 410, with the resist layer 420 having an opening portion 421 which corresponds to the location of a storage electrode to be formed later, as shown in
A part of the polycrystalline silicon 410 is etched using the resist layer 420 as a mask, and an opening 423 is formed in the polycrystalline silicon 410, as shown in
A polycrystalline silicon layer 430 for the side wall 403 is deposited to fill in the opening 423 and is deposited on the polycrystalline silicon layer 410 using a CVD method. The thickness of the polycrystalline layer 430 is 1000–2000 Å. Similarly, the polycrystalline silicon 430 can be not introduced a conductive impurity or can be introduced the impurity (phosphorus) at a concentration of 2×1020/cm3–5×1020/cm3.
Then, the polycrystalline silicon layer 430 is etched by anisotropic etching and the side wall 403 remains on the side of the polycrystalline silicon layer 410, as shown in
In
Then, a polycrystalline silicon layer 481 is formed on the polycrystalline silicon layer 471 as shown in
A resist layer is formed on the polycrystalline silicon layer 481 and is patterned such that a part of the resist layer 491 remains above a storage electrode, as shown in
Then, the polycrystalline silicon layers 481, 471 and 410 are etched using the resist layer 491 as a mask, as shown in
According to the fourth embodiment, the silicon layer 401 and 403 can be used as a mask and a part of the storage electrode, and the capacitance may be increased according to the thickness of the silicon layer 401.
The fourth embodiment can be applied to the second embodiment, and the resultant structure is shown in
According to this combination, the effects of both the second and fourth embodiments mentioned above can be obtained. A method of manufacturing of this combination can be easily understood from the description above.
A conductivity type of the substrate and the diffusion region is not limited to the above embodiments and can be set flexibility.
The embodiments of the present invention are directed to the capacitor of a DRAM. The invention can also be applied to the gate electrodes and conductive lines.
It is possible to apply the invention to another DRAM, as shown in
Diffusion regions 603, 613, 623 (the source or drain of a transistor of the memory cell) are formed in a semiconductor substrate 1.
A gate oxide film 15 is formed on the surface of the substrate 1. Gate electrodes 607, 617 of the transistor of the memory cell are formed on the gate oxide film 15, which is located between the diffusion regions 3. A first intermediate insulating film 9 is formed on the gate oxide film 15 and the gate electrodes 607, 617.
A plurality of contact holes are formed in the first insulating layer 9. The silicon layer 51-1 is electrically connected to the diffusion region 603 through one of the contact holes. The first silicon layer 51-2 is connected to the diffusion region 613 through another one of the contact holes. Second silicon layers 53-1, 53-2 are respectively formed on the first silicon layers 51-1, 51-2. The first silicon layer 51-1 and the second silicon layer 53-1 compose one storage electrode. The first silicon layer 51-2 and the second silicon layer 53-2 compose to another storage electrode.
A nitride layer 57-1 is formed on the upper surface of the second silicon layer 53-1 and the side surfaces of the first and second silicon layers 51-1,53-1. Similarly, a nitride layer 57-2 is formed on the upper surface of the second silicon layer 53-2 and the side surfaces of the first and second silicon layers 51-2,53-2.
The silicon layer 59 is formed on the nitride layer 59 and covers the storage electrode through the nitride layer 57. The silicon layer 59 (cell plate electrode) is patterned in the vicinity of the storage electrode as shown in
A second intermediate insulating layer 611 is formed on the nitride layers 57-1,57-2 and the silicon layers 59-1, 59-2. A contact hole is formed through the first and second insulating layers 9, 611, to the diffusion region 3. A bit line 621 is formed on the second insulating layer 611 and is electrically connected to the diffusion region 623 through this contact hole.
The first silicon layers 51-1, 51-2, the second silicon layers 53-1, 53-2, and the silicon layer 59-1, 59-2 are comprised of polycrystalline silicon. The insulating layers 9,611 are comprised of an oxide film or BPSG.
According to the structure shown in
Further, the invention can be applied to a fin type or a cylinder type capacitors.
The present invention has been described with reference to illustrative embodiments, however, this description must not be considered to be confined only to the embodiments illustrated. Various modifications and changes of these illustrative embodiments and the other embodiments of the present invention will become apparent to one skilled in the art from reference to the description of the present invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
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