The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising alxGa1−xN. The al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.
|
1. A heterostructure semiconductor device having:
a buffer layer comprising alxG1−xN, where x is in the range of 1% to 4%; and
a channel layer disposed on the buffer layer, thereby defining a first interface located between the buffer layer and the channel layer, the channel layer comprising GaN, and having a thickness in the range of 40–100 nm.
19. A heterostructure semiconductor device comprising:
a buffer layer; and
a channel layer disposed on the buffer layer, thereby defining a first interface located between the buffer layer and the channel layer, the channel layer comprising a GaN;
wherein the buffer layer and channel layer define a portion of a conduction band, a valence band, and a fermi level, and wherein the portion of the conduction band defined by the buffer layer at the first interface is at a greater potential than the portion of the conduction band defined by the channel layer at the first interface;
wherein the portion of the conduction band defined by the buffer layer at the first interface and the portion of the conduction band defined by the channel layer at the first interface are at a potential higher than the fermi level at the first interface; and
wherein the portion of the valence band defined by the buffer layer at the first interface and the portion of the valence band defined by the channel layer at the first interface are at a potential lower than the fermi level at the first interface.
7. A heterostructure semiconductor device comprising:
a buffer layer comprising alxGa1−xN; and
a channel layer disposed on the buffer layer, thereby defining a first interface located between the buffer layer and channel layer, the channel layer comprising GaN; wherein the value of x falls within a range contained between a curve A, a curve b, a line c, and a line d in a graph showing a relation between the value of x and the thickness of the channel layer, wherein:
the curve A smoothly connects six points of an upper x value of 10% at the channel layer thickness of 15 nm, an upper x value of 8.5% for the channel layer thickness of 20 nm, an upper x value of 4% for the channel layer thickness of 40 nm, an upper x value of 2.8% for the channel layer thickness of 60 nm, an upper x value of 2% for the channel layer thickness of 80 nm, an upper x value of 1.6% for the channel layer thickness of 100 nm;
the curve b smoothly connects six points of a lower x value of 2.7% for the channel layer thickness of 15 nm, a lower x value of 2% for the channel layer thickness of 20 nm, a lower x value of 1% for the channel layer thickness of 40 nm, a lower x value of 0.65% for the channel layer thickness of 60 nm, a lower x value of 0.52% for the channel layer thickness of 80 nm, a lower x value of 0.39% for the channel layer thickness of 100 nm;
the line c is specified by the channel layer thickness of 15 nm; and
the line d is specified by the channel layer thickness of 100 nm.
13. A heterostructure semiconductor device comprising:
a buffer layer comprising alxGa1−xN; and
a channel layer disposed on the buffer layer, thereby defining a first interface located between the buffer layer and channel layer, the channel layer comprising GaN;
a barrier layer disposed on the channel layer, thereby defining a second interface located between the barrier layer and the channel layer, the barrier layer comprising AlGaN;
a cap layer disposed on the barrier layer, the cap layer comprising GaN;
ohmic metal contacts deposited on the cap layer, wherein the ohmic metal contacts are in contact with the channel layer;
a gate in contact with the barrier layer;
wherein the value of x and the thickness of the channel layer fall within a range surrounded by a curve A, a curve b, a line c, and a line d in a graph showing a relation between the value of x and the thickness of the channel layer, wherein:
the curve A smoothly connects six points of an upper x value of 10% at the channel layer thickness of 15 nm, an upper x value of 8.5% for the channel layer thickness of 20 nm, an upper x value of 4% for the channel layer thickness of 40 nm, an upper x value of 2.8% for the channel layer thickness of 60 nm, an upper x value of 2% for the channel layer thickness of 80 nm, an upper x value of 1.6% for the channel layer thickness of 100 nm;
the curve b smoothly connects six points of a lower x value of 2.7% for the channel layer thickness of 15 nm, a lower x value of 2% for the channel layer thickness of 20 nm, a lower x value of 1% for the channel layer thickness of 40 nm, a lower x value of 0.65% for the channel layer thickness of 60 nm, a lower x value of 0.52% for the channel layer thickness of 80 nm, a lower x value of 0.39% for the channel layer thickness of 100 nm;
the line c is specified by the channel layer thickness of 15 nm; and
the line d is specified by the channel layer thickness of 100 nm.
2. The heterostructure semiconductor device of
3. The heterostructure semiconductor device of
4. The heterostructure semiconductor device of
5. The heterostructure semiconductor device of
6. The heterostructure semiconductor device of
8. The heterostructure semiconductor device of
9. The heterostructure semiconductor device of
10. The heterostructure semiconductor device of
11. The heterostructure semiconductor device of
12. The heterostructure semiconductor device of
14. The heterostructure semiconductor device of
15. The heterostructure semiconductor device of
16. The heterostructure semiconductor device of
17. The heterostructure semiconductor device of
18. The heterostructure semiconductor device of
20. The heterostructure semiconductor device of
|
This application claims the benefit of U.S. Provisional Patent Application No. 60/475,545 filed Jun. 2, 2003, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to a GaN-based double-heterojunction field-effect transistor (DHFET) with improved performance characteristics. More specifically, the present invention relates to a GaN-based HFET comprising a buffer layer containing Al, and a channel layer, wherein the Al content in the buffer layer is related to the thickness of the channel layer.
Heterojunction field-effect transistors (HFETs) are commonly used for applications requiring low noise and high power. These transistors typically contain a channel layer surrounded by a barrier layer and a buffer layer. Generally, there are two types of HFETs: single-heterojunction field-effect transistors (SHFETs) and double-heterojunction field-effect transistors (DHFETs). In SHFETs, the buffer layer and channel layer are comprised of the same material, and the barrier layer is comprised of a different material. The channel/barrier interface is the single heterojunction in this structure. In DHFETs the buffer layer and barrier layer are comprised of different materials than the channel layer. Thus, the buffer/channel and channel/barrier interfaces are both heterojunctions. The key feature of a HFET is that the channel/barrier heterojunction induces a highly conductive, two-dimensional electron gas (2DEG) in the channel near the interface.
Shown in
The barrier layer 9 induces a highly conductive, two-dimensional electron gas (2DEG) in the channel layer 7 near the interface with the barrier layer 9 and also acts as an insulator between the gate 15 and the channel layer 7. When electrons “spill” from the channel layer 7 into the buffer layer 5, the performance of the transistor is reduced; thus, confinement of electrons in the channel layer 7 is highly desirable. The barrier layer 9 is located on the channel layer 7. A cap layer 11 is also provided on a portion of the barrier layer 9. The cap layer 11 helps prevent oxide and other impurities from damaging the barrier layer 9 during processing. Ohmic metal contacts 13 are also provided. The ohmic contacts 13 are annealed at a high temperature such that they diffuse into the cap layer 11 and barrier layer 9, where they contact the channel layer 7.
The following will describe some typical HFETs making reference to the above description and the HFET structure shown in
The confinement of the 2DEG in the channel layer 7 can be improved by using a double-heterojunction structure in which the buffer layer 5 comprises a material having a wider bandgap than that of the channel layer 7. For example, in InP-based HFETs (so called because the device layers are grown on InP substrates), double-heterojunction field effect transistors (DHFETs) have been utilized. DHFETs are also discussed in U.S. Pat. No. 4,827,320 and in Loi. D. Nguyen et al., IEEE Transaction on Electron Devices, vol. 39, pp 2007–2014 (1992). A band-edge diagram of an InP-based DHFET where the buffer layer 5 comprises Al0.48In0.52As, the channel layer 7 comprises In0.53Ga0.47As and the barrier layer 9 comprises Al0.48In0.52As is shown in
Designs for DHFETs implemented in GaN-based materials have mimicked designs for DHFETs implemented in InP-, GaAs-, and InAs-based materials. One attempt at demonstrating such an analogous device is discussed in N. Maeda et al., physica status solidi (b) pp. 727–731 (1999). Shown in
These GaN DHFETs contain large polarization charges at the interface between the buffer layer 5 and channel layer 7. These charges result in exceptionally large electric fields at that interface which cause the valence band edge on the channel layer 7 side to rise above the Fermi level at the interface, as shown in
As a result, there is a need for a HFET that provides the bandgap characteristics of GaN-based HFETs, confines the 2DEG to the channel layer, and reduces the 2DHG.
In order to achieve the need outlined above, and according to one aspect of this invention, there is provided a DHFET having a channel layer comprising GaN and a buffer layer comprising AlxGa1−xN, where the Al content (i.e. x) is varied depending on the thickness of the channel layer. The Al content in the buffer layer is significantly lower than the previously thought optimal value. Reducing the Al content used in the buffer layer also helps cause a misalignment between the conduction band and valence band associated with the channel layer and buffer layer, which helps to reduce the 2DHG, thereby enhancing the performance of the transistor.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
A preferred embodiment of the present invention will now be described with reference to
The buffer layer 105 helps prevent the 2DEG in the channel layer 107 from spilling into the substrate 101 and the nucleation layer 103. The Al content (i.e. x) in the AlxGa1−xN buffer layer 105 is directly dependent on the thickness of the channel layer 107, and will be discussed later. A barrier layer 109 is deposited on the channel layer 107, as shown in
In order to calculate the optimal value of x for a given channel layer 107 thickness, a one-dimensional model for calculating GaN DHFET band diagrams that accounts for polarization charges at heterojunction interfaces was developed. The model is used to calculate the band diagram of the DHFET by numerically solving a set of coupled Poisson and Schrödinger equations using AlGaN material parameters taken from O. Ambacher et al., Journal of Applied Physics 85, pp. 3222–3233 (1999). Using the model to analyze the failure of conventional GaN DHFET structures, it was found that the high Al content used for the barrier and buffer layers in conventional GaN DHFET's resulted in a band structure similar to the one shown in
Using this model, a more optimal value of x (that is, the aluminum mole fraction in the buffer layer 105) versus the thickness of the channel layer 107, was calculated and will now be discussed with reference to
TABLE 1
POINTS
X (%)
THICKNESS (nm)
1A
32
5
2A
8.5
20
3A
4
40
4A
2.8
60
5A
2
80
6A
1.6
100
1B
8
5
2B
2
20
3B
1
40
4B
0.65
60
5B
0.52
80
6B
0.39
100
From Table 1 and graph 6, the shaded region can be defined as the region contained by curve A, curve B, line C, and line D, wherein:
The thickness of the channel layer 107 generally does not fall below 5 nm because the energy of the ground state of the 2DEG increases rapidly as the channel layer 107 thickness is reduced below this value. In the limit of an infinitely thin channel layer 107, the ground state rises to the top of the channel layer 107, electrons are no longer confined to the channel layer 107, and the 2DEG ceases to exist.
For purposes of comparison,
Shown in
Referring back to
Next, an opening for a gate is created. Using the ohmic contacts 115 or the optional SiN layer as a mask, a portion of the cap layer 111 is removed preferably using a reactive ion etch with a chlorine gas, or a wet chemical etch. A gate 119 preferably having a T-shaped structure is then deposited using bi-layer e-beam lithography on the barrier layer 109, as shown in
Let it be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the spirit of the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances which fall within the scope of the appended claims.
Hashimoto, Paul, Hussain, Tahir, Micovic, Miroslav, Deelman, Peter W.
Patent | Priority | Assignee | Title |
10090439, | Jan 27 2014 | SUZHOU LEKIN SEMICONDUCTOR CO , LTD | Light emitting device, light emitting device package, and light unit |
10276705, | Feb 25 2016 | Raytheon Company | Group III—nitride double-heterojunction field effect transistor |
10580871, | Sep 02 2016 | IQE plc | Nucleation layer for growth of III-nitride structures |
10636899, | Nov 15 2016 | Infineon Technologies Austria AG | High electron mobility transistor with graded back-barrier region |
7800132, | Oct 25 2007 | Northrop Grumman Systems Corporation | High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof |
7989277, | Sep 11 2007 | HRL Laboratories, LLC | Integrated structure with transistors and Schottky diodes and process for fabricating the same |
8368119, | Sep 11 2007 | HRL Laboratories, LLC | Integrated structure with transistors and schottky diodes and process for fabricating the same |
8592865, | Oct 29 2009 | HRL Laboratories, LLC | Overvoltage tolerant HFETs |
9231064, | Aug 12 2014 | Raytheon Company | Double heterojunction group III-nitride structures |
9259819, | Nov 06 2012 | Entegris, Inc | CMP method for forming smooth diamond surfaces |
9583607, | Jul 17 2015 | Mitsubishi Electric Research Laboratories, Inc. | Semiconductor device with multiple-functional barrier layer |
9773884, | Mar 15 2013 | HRL Laboratories LLC | III-nitride transistor with engineered substrate |
9876102, | Jul 17 2015 | Mitsubishi Electric Research Laboratories, Inc. | Semiconductor device with multiple carrier channels |
9917156, | Sep 02 2016 | IQE, plc | Nucleation layer for growth of III-nitride structures |
9960262, | Feb 25 2016 | Raytheon Company | Group III—nitride double-heterojunction field effect transistor |
Patent | Priority | Assignee | Title |
4827320, | Sep 19 1986 | University of Illinois | Semiconductor device with strained InGaAs layer |
5548139, | Jun 28 1993 | NEC Corporation | Schottky gate field effect transistor |
5929467, | Dec 04 1996 | Sony Corporation | Field effect transistor with nitride compound |
6064082, | May 30 1997 | Sony Corporation | Heterojunction field effect transistor |
6140169, | Dec 04 1996 | Sony Corporation | Method for manufacturing field effect transistor |
6399430, | Mar 27 1997 | Renesas Electronics Corporation | Field effect transistor and method of manufacturing the same |
20040029330, | |||
JP10335637, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Apr 13 2004 | MICOVIC, MIROSLAV | HRL Laboratories, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015272 | /0172 | |
Apr 13 2004 | HASHIMOTO, PAUL | HRL Laboratories, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015272 | /0172 | |
Apr 14 2004 | HUSSAIN, TAHIR | HRL Laboratories, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015272 | /0172 | |
Apr 19 2004 | DEELMAN, PETER W | HRL Laboratories, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015272 | /0172 | |
Apr 26 2004 | HRL Laboratories, LLC | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Feb 04 2010 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Feb 17 2010 | ASPN: Payor Number Assigned. |
Feb 27 2014 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Feb 21 2018 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Aug 29 2009 | 4 years fee payment window open |
Mar 01 2010 | 6 months grace period start (w surcharge) |
Aug 29 2010 | patent expiry (for year 4) |
Aug 29 2012 | 2 years to revive unintentionally abandoned end. (for year 4) |
Aug 29 2013 | 8 years fee payment window open |
Mar 01 2014 | 6 months grace period start (w surcharge) |
Aug 29 2014 | patent expiry (for year 8) |
Aug 29 2016 | 2 years to revive unintentionally abandoned end. (for year 8) |
Aug 29 2017 | 12 years fee payment window open |
Mar 01 2018 | 6 months grace period start (w surcharge) |
Aug 29 2018 | patent expiry (for year 12) |
Aug 29 2020 | 2 years to revive unintentionally abandoned end. (for year 12) |