A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.

Patent
   7161399
Priority
Aug 03 2001
Filed
Sep 02 2004
Issued
Jan 09 2007
Expiry
Aug 03 2021
Assg.orig
Entity
unknown
0
14
EXPIRED
38. A method of improving efficiency of a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB);
detecting four or more timing conditions based upon phases of CIN and CKFB; and
selectively inputting a clock signal (CLK) or inverted clock signal (CLK′) from a dealy line into a clock tree driver (CTD) based on the detected timing condition to reduce a number of effective delay stages in the DLL.
11. A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics;
determining four or more phases based upon the timing characteristics of CIN and CKFB; and
for at least one phase, directing a clock signal (CLK) from a dealy line into a clock tree driver (CTD) based on the plurality of phases to reduce a number of delay stages.
1. A method of improving efficiency of a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB);
detecting by way of only a single phase detector four or more timing conditions based upon phases of CIN and CKFB; and
selectively inputting a clock signal (CLK) or inverted clock signal (CLK′) from a delay line into a clock tree driver (CTD) based on which of the timing conditions is met to reduce a number of effective delay stages in the DLL.
42. A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;
determining four or more phases based upon the timing characteristics of CIN and CKFB; and
for at least one phase, directing a clock signal (CLK) into a clock tree driver (CTD) such that a reduced number of delay stages is achieved, wherein a delay line is configured to output the CLK based on the plurality of phases.
6. A method of improving efficiency of a delay-locked loop, comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB);
interposing a phase detector and selection system between an external clock signal and a clock tree driver (CTD);
wherein the selection system is interposed between the clock tree driver (CTD) and a delay line
determining which of a number of four or more timing conditions is met based upon phases of the signals; and
selectively directing the signals based upon the phase of the signals.
10. A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;
differentiating, with only a single phase detector, four or more phases based upon the timing characteristics of CIN and CKFB; and
selecting, based on the phases, one of a clock signal (CLK) or inverted clock signal (CLK′) from a delay line to be input into a clock tree driver (CTD), to reduce a number of effective delay stages in the DLL.
40. A method of improving efficiency of a delay-locked loop (DLL), comprising:
providing a clock input signal CIN, and clock feedback signal (CKFB), each signal having timing characteristics;
interposing a phase detector and selection system between an external clock signal and a clock tree driver (CTD) wherein the selection system is interposed between the clock tree driver (CTD) and delay Line;
selecting a clock tree driver input based on a delay line output and at least one output of the phase detector; and
selectively directing the signals based upon the phase of the signals.
41. A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;
differentiating, with a phase detector, four or more phases based upon the timing characteristics of CIN and CKFB; and
selecting a delay line output; based on the phases, the delay line output is selected from one of a clock signal (CLK) or inverted clock signal (CLK′) to be input into a clock tree driver (CTD), thereby reducing a number of effective delay stages in the DLL.
45. A method of improving efficiency of a delay-locked loop (DLL) comprising:
providing a clock input signal (CIN) and a clock feedback signal (CKFB);
detecting four or more timing conditions based upon phases of CIN and CKFB; and
selectively inputting a clock signal (CLK) or inverted clock signal (CLK′) into a clock tree driver (CTD) based on the detected timing condition to reduce a number of effective delay stages in the DLL, wherein a single phase detector detects the timing conditions, wherein a delay line is interposed between the phase detector and a multiplexor, and the multiplexor is interposed between the CTD and the delay line.
14. A memory device, comprising:
a delay-locked loop (DLL), comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector to output a pair of branches each comprising a logical level, wherein the logical levels of the branches define four or more conditions of CIN and CKFB signals based on the timing characteristics, and wherein a clock signal (CLK) or inverted clock signal (CLK′) is output from a delay line into a clock tree driver (CTD) based on the plurality of conditions to reduce a number of effective delay stages in the DLL.
26. A delay-locked loop system, comprising:
a delay-locked loop (DLL), comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, and the phase detector to output a pair of branches each comprising a logical level, the logical levels of the branches define four or more conditions based on the timing characteristics, and at least one of the conditions reduces a number of effective delay stages of the DLL; and
a delay line, the delay line to receive the CIN and to output a clock signal (CLK) and inverted clock signal (CLK′)based on the plurality of conditions.
29. A phase detection and selection circuit, comprising:
a phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, and to generate four or more output signal combinations, each combination based upon the timing characteristics; and
logic associated with the phase detector to select one of the output signal combinations corresponding to the timing characteristics of the signals;
to selectively feed at least one of a clock signal (CLK) and an inverted clock signal (CLK′) provided at least indirectly by a delay line into a portion of the circuit based upon which of the plurality of output signal combinations is generated, and a number of effective delay stages is reduced.
34. A system, comprising:
a processor;
a memory controller;
a plurality of memory devices;
a first bus interconnecting the processor and memory controller;
a second bus interconnecting the memory controller and memory devices;
each of the memory devices comprising:
a delay-locked loop (DLL), comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing conditions, and generating a plurality of output signal combinations, each combination corresponding to four or more phases of the signals based upon the timing conditions; and
logic associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals;
wherein the timing conditions include a period of CIN (tck) and a period from a rising edge in CIN to a rising edge in CKFB (te), and selectively inputting CLK into a clock tree driver (CTD) when te<tck/2 reduces a number of effective delay stages.
20. A delay-locked loop system, comprising:
a delay-locked loop (DLL), comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector to output a pair of branches each having a logical level; and
a delay line, the delay line to receive the CIN and to output a clock signal (CLK) and inverted clock signal (CLK′), the CLK and CLK′ based on a plurality of conditions, wherein the logical levels of the branches define four or more conditions based on the timing characteristics of CIN and CKFB, and at least one of the conditions reduces a number of effective delay stages in the DLL;
wherein the timing characteristics define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and the plurality of conditions include:
a first condition when te>tck/2;
a second condition when te<tck/2;
a third condition when te=tck; and
a fourth condition when te=tck/2.
43. A circuit for use with an external clock signal, comprising:
an input buffer comprising an input connected to an external clock signal and an output connected to a clock input signal (CIN) for comparison with a clock feedback signal (CKFB), each signal comprising timing characteristics; and
a phase detector disposed between the input buffer and an output buffer, the phase detector comprising a first input to receive the CIN, a second input to receive the CKFB, and the phase detector to generate one of four or more output signal combinations, each combination corresponding to a phase of the signals based on the timing characteristics;
the circuit comprising a delay line input, a selection multiplexor connected to the delay line input, a clock tree driver (CTD) to receive an output of the selection multiplexor, and a feedback loop to connect CKFB to the phase detector, and the circuit to selectively input a clock signal (CLK) or inverted clock signal (CLK′) as an input based on the phase of the signals, to reduce a number of effective delay stages for at least one of the phases.
21. A circuit for use with an external clock signal, comprising:
an input buffer comprising an input connected to an external clock signal and an output connected to a clock input signal (CIN), the CIN for comparison with a clock feedback signal (CKFB), each signal comprising timing characteristics;
a phase detector disposed between the input buffer and a clock tree driver (CTD), the phase detector comprising a first input for receiving the CIN, and a second input for receiving the CKFB, and generating one of four or more output signal combinations, each combination corresponding to a respective phase of the signals based on the timing characteristics;
wherein the circuit includes a delay line, a selection multiplexor connected to the delay line, the CTD to receive an output of the selection multiplexor, and a feedback loop to connect CKFB to the phase detector, the selection multiplexor to selectively input a clock signal (CLK) or inverted clock signal (CLK′) from the delay line as an input to the CTD based on the phase of the signals, and for at least one of the phases, a number of effective delay stages of the circuit is reduced.
44. A synchronous dynamic random access memory (SDRAM), comprising:
a delay-locked loop (DLL), comprising:
a phase detection system, comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs comprising a logical level, the logical levels to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN when input into the DLL to achieve locking with an external clock signal with respect to another phase; and
an input selection multiplexor to select either an input clock signal (CLK) or an inverted clock signal (CLK′) into a clock tree driver (CTD) based on the logical levels of the outputs of the phase detector, the CLK and CLK′ to be provided at least indirectly from a delay line;
the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te; and
a first phase is when te>tck/2; and
a second phase is when te<tck/2; and
a third phase is when te=tck; and
a fourth phase is when te=tck/2.
35. A synchronous dynamic random access memory (SDRAM), comprising:
a delay-locked loop (DLL), comprising:
a phase detection system, comprising:
a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs having a logical level, to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN to achieve locking with an external clock signal with respect to another phase; and
an input selection multiplexor to select whether to input a clock signal (CLK) or an inverted clock signal (CLK′) into an additional component based on the logical levels of the outputs of the phase detector, the CLK and CLK′ to be provided at least indirectly from a delay line that is at least indirectly in communication with the phase detector;
the timing characteristics the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te, and
a first phase is when te>tck/2;
a second phase is when te<tck/2;
a third phase is when te=tck; and
a fourth phase is when te=tck/2.
2. The method of claim 1, wherein the timing conditions are determined based upon a period of CIN (tck) and a period from a rising edge in CIN to a rising edge in CKFB (te), and wherein selectively inputting includes inputting CLK into the CTD when te>tck/2 and inputting CLK′ into the CTD when te<tck/2.
3. The method of claim 1, wherein the number of effective delay stages is reduced by about half or greater.
4. The method of claim 1, wherein the number of effective delay stages is equal to or less than about half of a clock period.
5. The method of claim 1, wherein the number of effective delay stages is reduced from 128 to substantially 59.
7. The method of claim 6, wherein selectively directing comprises selectively directing a clock signal (CLK) or inverted clock signal (CLK′) to the clock tree driver (CTD) based upon the phases of CIN and CKFB.
8. The method of claim 6, wherein characteristics of the signals define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and determining comprises:
determining a first timing condition when te>tck/2;
determining a second timing condition when te<tck/2;
determining a third timing condition when te=tck; and
determining a fourth timing condition when te=tck/2.
9. The method of claim 6, wherein the phase detector and selection system include only a single phase detector, the delay line and a multiplexor, wherein the delay line is coupled in between the phase detector and the multiplexor and the multiplexor is coupled to the CTD.
12. The method of claim 11, wherein the timing characteristics define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and the directing occurs when te<tck/2.
13. The method of claim 12, further comprising the step of:
multiplexing the CLK with an input selection multiplexor to select whether to direct the CLK or an inverted clock signal (CLK′) into the CTD based on the phase determined by the timing characteristics of CIN and CKFB.
15. The memory device of claim 14, wherein the timing characteristics include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te, and
a first of the conditions is when te>tck/2;
a second of the conditions is when te<tck/2;
a third of the conditions is when te=tck; and
a fourth of the conditions is when te=tck/2.
16. The memory device of claim 15, wherein when te<tck/2, the reduced number of effective delay stages is achieved.
17. The memory device of claim 14, wherein the number of effective delay stages is reduced by about one-half or greater.
18. The memory device of claim 14, wherein the number of effective delay stages is equal to or less than about one-half of a clock period.
19. The memory device of claim 14, wherein the number of effective delay stages is substantially 59.
22. The circuit of claim 21, wherein the timing characteristics define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and wherein when te>tck/2, CLK is input into the CTD, and when te<tck/2, CLK′ s input into the CTD.
23. The circuit of claim 21, wherein the number of effective delay stages is reduced by about one-half or greater.
24. The circuit of claim 21, wherein the number of effective delay stages is equal to or less than about one-half of a clock period.
25. The circuit of claim 21, wherein the number of effective delay stages is about 59.
27. The system of claim 26, wherein the number of effective delay stages is reduced by about one-half or more.
28. The system of claim 26, wherein the timing characteristics define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and the conditions include:
a first condition when te>tck/2;
a second condition when te<tck/2;
a third condition when te=tck; and
a fourth condition when te=tck/2.
30. The circuit of claim 29, wherein the timing characteristics include a period of CIN defined as tck, a period from a rising edge in CIN to a rising edge in CKFB defined as te, and the output signal combinations are respectively indicative of a plurality of timing conditions that include:
a first condition when te>tck/2;
a second condition when te<tck/2;
a third condition when te=tck; and
a fourth condition when te=tck/2.
31. The circuit of claim 29, wherein the number of effective delay stages is reduced by about one-half or more.
32. The circuit of claim 29, wherein the number of effective delay stages is equal to or less than about one-half of a clock period.
33. The circuit of claim 29, wherein the number of effective delay stages is substantially 59.
36. The SDRAM of claim 35, wherein when te<tck/2, the lock period to lock CIN to the external clock signal is reduced.
37. The SDRAM of claim 35, wherein when te<tck/2, the lock period to lock CIN to the external clock signal is reduced by about one-half or greater.
39. The method of claim 38, wherein the timing conditions are detected by only a single phase detector.

This application is a division of U.S. patent application Ser. No. 09/921,614, now U.S. Pat. No 6,798,259 filed Aug. 3, 2001, which is incorporated herein by reference in its entirety.

The present invention relates generally to the field of integrated circuits. More particularly, the invention relates to circuits that will synchronize the internal timing or clock signals within an integrated circuit such as a synchronous dynamic random access memory (SDRAM) to external timing or clock signals.

Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, and so forth, the processing, storage, and retrieval of information is coordinated with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high-speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.

A continual demand exists for devices with higher data rates; consequently, circuit designers have begun to focus on ways to increase the frequency of the clock signal. In SDRAMs, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. The delay between a rising edge of the system clock (external to the SDRAM) and the appearance of valid data at the output of the memory circuit is known as the clock access time of the memory. A goal of memory circuit designers is to minimize clock access time as well as to increase clock frequency.

One of the obstacles to reducing clock access time has been clock skew, that is, the delay time between the externally supplied system clock signal and the signal that is routed to the memory's output circuitry. An external system clock is generally received with an input buffer and then further shaped and redriven to the internal circuitry by an internal buffer. The time delay of the input buffer and the internal buffer will skew the internal clock from the external clock. This clock skew will cause signals that are to be transferred from the integrated circuit to be out of synchronization with the external system clock. This skew in the clock signal internal to the integrated circuit is furthered by the delays incurred in the signal passing through the clock input buffer and driver and through any associated resistive-capacitive circuit elements. One solution to the problem of clock skew is the use of a synchronous mirror delay, and another is the use of delay-locked loops.

Delay-locked loops (DLL) are feedback circuits used for synchronizing an external clock and an internal clock with each other. Typically, a DLL operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.

A synchronous mirror delay circuit (SMD) is a circuit for synchronizing an external clock and an internal clock with each other. The SMD can acquire lock generally within two clock cycles. The SMD has a period of delay, known as a delay range. The delay range of the SMD determines the actual operating range, or clock frequency, within which the integrated circuits (ICs) can operate. In other words, it is desired to reduce the number of delay stages required in the SMD while maintaining the lock delay range. One goal is to improve the efficiency of the SMD to maintain the proper operating range and to reduce the required area and power consumption of the SMD.

For the conventional SMD implementations, two delay lines are required, one for delay measurement, one for variable mirrored delay. The effective delay length for both delay lines is defined as:
tdelay=tck−tmdl
where tck is the clock period, tmdl is the delay of an input/output (“I/O”) model, including clock input buffer, receiver, clock tree and driver logic. The delay stages required for each delay line is given by:

N = t delay t = t ck - t md 1 t
where td is the delay per stage. The worst case number is given by:

N worst = t ck ( long ) - t md 1 ( fast ) t d ( fast )

For example, where tck (long)=15 ns (as in a 66 MHz bus), tmdl (fast)=1 ns and td (fast)=110 ps,

N worst = 15 ns - 1 ns 110 ps 128

For two delay lines in an SMD, a total of 256 stages are needed to adjust the delay.

When locking, tlock=din+tmdl+(tck−tmdl)(measured)+(tck−tmdl) (variable)+dout. This is the conventional equation to calculate the lock time of the SMD, which is generally two clock cycles, based on sampling from one rising edge to the next rising edge of the internal clock signal.

Therefore, one goal of the present invention is to reduce the effective delay stages used in the SMD while maintaining the lock range.

The present invention solves the aforementioned problems, and improves the efficiency of the synchronous circuitry for the internal clock signal to lock with the external clock signal.

In one aspect of the invention, a phase detection and selection circuit includes a phase detector for receiving a clock input signal CIN and a clock delay signal CDLY. Each signal has timing conditions and generates a plurality of output signal combinations, each combination corresponding to pre-defined phases of the signals based upon the timing characteristics. Logic is associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals. The timing characteristics define a period of CIN as tck and also define a period from a rising edge in CIN to a rising edge in CDLY as tmdl, and wherein when tmdl>tck/2, CIN is input into the SMD, and when tmdl<tck/2, an inverted clock signal CIN′is input into the SMD to reduce the number of delay stages in the SMD.

In another aspect of the invention, a method of improving the efficiency of a synchronous mirror delay circuit comprises the steps of providing a clock input signal CIN, an inverted clock signal (CIN′) and a clock delay signal CDLY, each having timed characteristics. The method includes interposing a phase detector and selection system between an external clock signal and a synchronous mirror delay circuit, and determining which of a number of phases the signals are in based on the timing characteristics, and directing the signals based upon the phase of the signals.

In another aspect of the invention, a phase detection and selection circuit for a delay-locked loop (DLL) includes a phase detector for receiving a clock input signal CIN and a clock feedback signal CKFB. Each signal has timing conditions and generates a plurality of output signal combinations, each combination corresponding to pre-defined phases of the signals based upon the timing characteristics. Logic is associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals. The timing characteristics define a period of CIN as tck and also define a period from a rising edge in CIN to a rising edge in CKFB as te and wherein when te<tck/2, the effective delay of the DLL is less than tck/2.

The drawings illustrate the best mode presently contemplated for carrying out the invention.

In the drawings:

FIG. 1 is a block diagram of a synchronous mirror delay with phase detection in accordance with the present invention.

FIG. 2 is a circuit diagram illustrating the phase detector in accordance with one aspect of the present invention.

FIG. 3 is a signal timing diagram showing the timing of a clock input signal and a clock delay signal in accordance with one aspect of the present invention.

FIG. 4 is a signal timing diagram showing the timing of a clock input signal and a clock delay signal in accordance with one aspect of the present invention.

FIG. 4a is a signal timing diagram showing the timing of a clock input signal and a clock delay signal under lock conditions in accordance with one aspect of the present invention.

FIG. 5 is a chart illustrating the logic combinations of the signals in FIG. 2 based upon the timing characteristics of FIGS. 3 and 4.

FIG. 6 is a flowchart illustrating a method in accordance with one aspect of the present invention.

FIG. 7 is a block diagram of a delay-locked loop with phase detection in accordance with the present invention.

FIG. 8 is a signal timing diagram showing the timing of a clock input signal and a clock feedback signal in accordance with one aspect of the present invention.

FIG. 9 is a signal timing diagram showing the timing of a clock input signal and a clock feedback signal in accordance with one aspect of the present invention.

FIG. 10 is a block diagram illustrating a system in which the present invention may be used.

Referring now to FIG. 1, a system in accordance with the present invention is shown generally by the numeral 10. The system 10 includes a synchronous mirror delay (SMD) circuit 12 and a phase detector control block 14. An external clock signal 16 is input into receiver and buffer 18. This produces clock input signal 20 (CIN), inverted clock input signal (CIN′) 21 and clock delay signal 22 (CDLY). Clock delay signal 22 is delayed by an I/O system delay tmdl illustrated by block 24. CDLY 22 is also directly fed via line 23 into the SMD 12.

Phase detector control block 14 includes phase detector 26 and associated logical circuitry. The goal of the present invention is to take clock input signal 20 and clock delay signal 22 and, by defining certain characteristics and relationships about the timing of the signals, delineate specific conditions under which the circuit is operating, and direct the signal accordingly. Ultimately, the phase of the signals will determine whether CIN 20 or CIN′ 21 is used as the input to the SMD, or whether the SMD is bypassed altogether. Although a specific logic arrangement is shown, it is contemplated that any suitable control logic may be used to define the conditions of the signals and select them accordingly. Associated with the phase detector is a multiplexor 28 which is used as an input selection multiplexor, that is to determine which selection input (CIN or CIN′), based on the difference between CIN signal 20 and CDLY signal 22, to send to the SMD 12. The outputs (collectively 32) of phase detector 26, which will be described in further detail with respect to FIG. 2 are fed into circuitry control block 30. Circuitry block 30 may be, for instance, a decoder, although any suitable logic is contemplated. The outputs 38 and 40 of phase detection circuitry block 30 will be used to select the outputs for multiplexors 28 and 46, respectively. Based on the signal 38 from control circuitry block 30, input multiplexor 28 will select either CIN 20 or CIN′ 21 to be placed on line 48. The output multiplexor 46 is used in combination with the control circuitry block 30 to select which signal is to be put on output line 50. Line 48 (either CIN signal 20 or CIN′signal 21) is directed into the SMD 12. Line 48 is also directed via connection 34 to an input of output selection multiplexor 46. As is known in the art, the SMD 12 includes a measurement delay line composed of a plurality of serially cascaded delay elements (not shown), the measurement delay line having a measurement delay line input and a measurement delay line output. Each delay stage is a delay element with control gates. An output of the measurement delay line is used as the input to a variable delay line. The variable delay line is also a plurality of serially connected delay elements (not shown), the variable delay line having a variable delay line input and a variable delay line output. The output of the variable delay line of the SMD 12 is output signal SMDOUT 44. Output signal SMDOUT 44 is used as the input to output multiplexor 46. In some circumstances, it is desired to entirely bypass SMD 12, and in such a case, control circuitry block 30 will send a control signal 40 selecting line 34 rather than SMDOUT 44 as the output 50 of output selection multiplexor 46. As a result, line 48 (either CIN signal 20 or CIN′signal 21) will be used as the input for output selection multiplexor 46. In other cases, the control circuitry block 30 will send a control signal 40 selecting signal SMDOUT 44 from SMD 12. Having selected one of the signals 34 or signal SMDOUT 44, output signal 50 is used as the input to clock tree 54. As is known, a clock tree is a circuit used for distributing a local clock signal. A clock tree may include an internal buffer in order to amplify, buffer and delay the signal in order to form internal clock signal CLKIN 56. Although not shown, it is contemplated that an inverter may be placed before the clock tree 54 in order to invert the clock signal if desired. In this manner, internal clock signal CLKIN 56 will be matched to the external clock 16.

Referring now to FIG. 2, phase detector 26 is described in more detail. Phase detector 26 receives clock input signal 20 and clock delay signal 22. Clock delay signal 22 is used as clock inputs 58 and 60 into registers 64 and 62 respectively. Although D flip-flops are used as registers 62 and 64, it is contemplated that any suitable logic device suitable for the application may be employed. Signal 22 is input into the clock inputs for the D flip-flops. Clock input signal CIN 20 is input as the D inputs 66 and 68 of flip-flops 62 and 64, respectively. Input 68 is delayed from clock input signal 20 by td 70, which is representative of the delay per stage, and therefore there is a delay between input signals 66 and 68, by a period td 70. Each flip-flop 62 and 64 respectively outputs a signal 34 and 32. The logical level, i.e., a logical 1 or a logical 0, of signal branches 32 and 34 determine the condition under which the relationship of the CIN signal 20 and CDLY signal 22 are operating in. The signal conditions are based on their individual timing characteristics.

Referring now to FIG. 3, a clock diagram is shown illustrating one possible combination of timing characteristics of CIN signal 20 and CDLY signal 22. CIN signal 20 fires first, and the characteristic tmdl, which is the delay of the IO model, is measured from the rising edge 23A to the rising edge 25A of CDLY signal 22. The entire period of CIN signal 20, that is the measurement of rising edge 23A to the next rising edge 23B is defined as the clock period or tck. Therefore, the time defined from the rising edge 25A of CDLY signal 22 to the next rising edge 23B of the CIN signal 20 defines a delay, tdelay 27A, which may be defined by tck minus tmdl. This series of timing characteristics would occur when CDLY signal 22 fires after the first falling edge 29A of CIN signal 20. This sampling of CIN from rising edge to rising edge requires a given number of delay stages to accomplish, where the total delay of these delay stages is tdelay, which is less than half of tck.

Referring now to FIG. 4, an alternate timing diagram is shown for CIN signal 20 and CDLY signal 22. These timing characteristics would occur when the rising edge 25B of CDLY signal 22 occurred prior to the falling edge 29B of CIN signal 20. Again, the delay between the firing at the rising edge 23B of CIN signal 20 and rising edge 25B defines the period of delay for the I/O model tmdl. Because the period of time from rising edge 23B to falling edge 29B represents half of the clock period tck, that portion of the signal may be represented by tck/2. Therefore, that distance minus the delay period for the I/O model tmdl results in the delay period 27B, in this case defined as tck/2 minus tmdl. Therefore, if the phase detector analyzes when the rising edge of CDLY signal 22 occurs with respect to the falling edge of CIN signal 20, a distinction can be made with respect to the timing characteristics of the individual signals 20 and 22. Since the total delay required from the SMD for synchronization is reduced from (tck minus tmdl) to (tck/2 minus tmdl) where tmdl is less than tck/2, more than half of the delay stages ca be saved with this invention. The present invention takes advantage of the ability to sample from a rising edge 23b to falling edge 29b, resulting in fewer delay stages in the SMD to accomplish.

Referring now to FIG. 4a, the timing diagram is shown illustrating the lock conditions. CIN signal is shown as well as CIN plus td, where td represents the delay between the two signals. In lock condition 3, signal CDLY is shown rising between the rising of CIN and CIN plus td, and falling between the falling of CIN and CIN plus td, respectively. Under this circumstance, a lock condition exists and the synchronous mirror delay is bypassed. Under lock condition 4, CDLY signal rises between the falling edge of CIN and the falling edge of CIN plus td. And CDLY falls between the rising edge of CIN and the rising edge of CIN plus td. Again, a lock condition exists and again the synchronous mirror delay is bypassed.

Referring now to FIG. 5, the four possible combinations of the logical levels of PH1 signal 32 and PH2 signal 34 are illustrated. Based on the logical levels of each of these signals, such that the condition of the signals may be determined from the logic levels on these lines.
tmdl>tck/2  Condition (1):

For condition (1), the effective delay length in the SMD is equal to tck−tmdl. When locking, tlock=din+tmdl+(tck−tmdl)(measured)+(tck−tmdl)(variable)+dout=2tck+din+dout−tmdl≈2tck, where din and dout are I/O intrinsic delays on which tmdl is represented or modeled.

This is the conventional equation to calculate the lock time of the SMD, which is two clock cycles.
tmdl<tck/2  Condition (2):

Under this condition, a multiplexor is used to select a different phase of CIN to feed in the SMD and the effective delay length is equal to tck/2−tmdl.

Again, tlock=din+tmdl+(tck/2−tmdl)+(tck/2−tmdl)+dout=tck+din+dout−tmdl≈tck.

The lock time is decreased to only one clock cycle. From the previous example,

N worst = 15 ns / 2 - 1 ns _ = 59 stages
compared to 128 stages without the invention.

Condition (3):

When tmdl=tck, the phase detector would declare a lock condition and the clock signal CIN is output directly without even passing into the SMD. The SMD may be disabled to save power.

Condition (4):

When tmdl=tck/2, the CIN is inverted and the SMD may be disabled to save power.

It is contemplated that the present invention will reduce the effective delay elements used in the SMD, as a function of the signals being found under the condition 2, saving both silicon area and power in the memory device, which is the primary goal.

For conditions (2) and (4), if there is a severe duty cycle distortion, the falling edges of CIN cannot provide a correct reference to adjust the delay, which would result in a large skew (phase error) at the output.

Referring now to FIG. 6, a flowchart illustrating a methodology associated with the present invention is disclosed. At the start 70, the present invention is used for those circuits in which it is desired to reduce the number of delay stages and there is negligible duty-cycle distortion. Therefore, signal CIN, inverted CIN and CDLY are provided in step 72. CDLY is delayed by the delay of the I/O system. In step 74, a phase detector is interposed between the synchronous mirror delay and CIN and CDLY signals. Both CIN and CDLY are input into the phase detector 76, after which it is necessary to determine based on the timing characteristics and relationships of CIN to CDLY, which condition or phase the timing signals are in 78. This leads to a series of four decisions 80a through 80d used to determine the relationship of the particular timing characteristics tmdl versus tck. Although the series of decisions are shown made in a serial fashion, that is, 80a prior to 80b and so on, these operations could also be rearranged to run in other serial fashions or in parallel, so long as the determinations are made. In decision 80a, it is determined whether tmdl is greater than tck/2 but less than tck. If so, 82a condition 1 is triggered 84a in which the lock time is equal to two clock cycles, which is the conventional synchronous mirror delay lock time. In a conventional manner, CIN is then fed into the synchronous mirror delay. The SMDOUT signal is input into the clock tree. If condition 1 is not satisfied 81, it is determined whether tmdl is less than tck/2 in decision 80b. If so 82b, condition 2 is implicated in which the lock time is equal to approximately one clock cycle, or approximately half of the conventional synchronous mirror delay lock time. CIN is then inverted and fed into the synchronous mirror delay. The SMDOUT signal is input into the clock tree. If condition 2 is not satisfied 83, it is determined whether tmdl is equal to tck in decision 80c. If so 82c, condition 3 84c is implicated, and lock has already occurred so a lock is declared and the synchronous mirror delay is bypassed. The CIN signal is input directly into the clock tree for internal production of the clock. If none of these conditions are true 85 and decision 80d is determined whether tmdl is equal to tck/2. If so 82d, condition 4 84d is implicated and it is merely necessary to invert the CIN signal or use an inverted CIN to be input into the clock tree. Again, since there is no need to further delay, the synchronous mirror delay is bypassed and, in a preferred embodiment may be disabled in order to save power. The CIN′ signal is input into the clock tree again to distribute the internal clock signal. The result of all four conditions 84a–d is that lock 86 occurs with an overall reduction in delay stages, which is the purpose of the circuit while maintaining the desired operating range.

Referring now to FIG. 7, the present invention is shown being used in a delay-locked loop or DLL, which is shown generally by the numeral 200. An external clock signal 216 is input into receiver and buffer 218. This produces clock input signal (CIN) 220. The delay in the signal as it passes through buffer receiver 218 is represented by din 219. CIN signal 220 is input via branch 222 into phase detector 226. CIN signal 220 is also directed via branch 224 into delay line 228. Phase detector 226 may include any associated logical circuitry. The goal of the present invention is to take CIN signal 220 as well as a clock feedback signal 230 (CKFB) and, by defining particular characteristics and relationships about the timing of CIN signal 220 and CKFB 230, to delineate specific conditions under which the signals are operating, and selecting and directing the signals accordingly. Although a specific logic arrangement is shown, it is contemplated that any suitable control logic may be used to define the conditions of the signals and then selecting them accordingly. CKFB feedback signal 230 is a typical feedback loop as is found in a common delayed-lock loop (DLL). Phase detector 226 compares the timing of signal CIN and signal CKFB. Based on timing conditions and characteristics of each signal, control signals are sent via control lines 232 to control block 234 and output via lines 236 to delay line 228. The period of the delay is represented by tdelay 230. Associated with the delay line 228 is selector 238 which receives an input 240 from the phase detector 226 as well as inputs 242 and 244 representative of the clock CLK and inverted clock signals respectively. Selector 238 selects, based on the input 240 from the phase detector 226, whether to put signal 242 or 244 to input 246 into clock tree driver 248. The period of delay by the driver is represented by ttree 250. The output 252 of the clock tree driver 248 is sent to an output buffer 254 which has an input data line 256 and a data output line 258. The delay by the output of data is represented by the parameter dout 260. Clock tree driver 248, as part of the delay-locked loop, feeds back into phase detector 226 via line 230. The delay associated with the I/O model 262 is represented by the parameter din and dout.

Generally speaking,

1. In order to synchronize XCLK with DQs,
tdelay=tck−ttree−(din+dout)

In traditional DLLs, the delay stages required are:

N = t delay t = t ck - t tree - ( d in + d out ) t N worst = t ck ( long ) - t tree ( short ) - ( d in + d out ) ( fast ) t d ( fast ) = 15 n - 1 n 110 ps 128

2. Use same method, and adding a selector:
te<tck/2, tdelay=tck/2−te
te>tck/2, tdelay=tck−te

For both cases,

tdelay is less than or equal to tck/2

N worst = t ck / 2 ( long ) - others t d ( fast ) = 7.5 n - 1 n 110 ps 59

Referring now to FIG. 8, a timing diagram for signals CIN and CKFB are shown in a particular arrangement. The period from the rising edge 300 to rising edge 302 is designated as tck. The amount of time from rising edge 300 of CIN and rising edge 304 of CKFB is represented by the parameter te. Additionally, the parameter from the rising edge 304 of CKFB and the falling edge 306 of CIN is represented by the parameter tdelay. In this case, tdelay is less than or equal to half of tck.

Referring now to FIG. 9, the second case is illustrated where CKFB does not fire until after the first pulse of CIN. Again, tck is represented by the rising edge 308 of CIN and the next rising edge 310 of CIN. Additionally, the length of time from the rising edge 308 to the rising edge 312 of CKFB is shown by the parameter te. However, in this instance, tdelay is measured from the rising edge 312 of CKFB until the next rising edge 310 of CIN. Similarly, in this case, tdelay is less than or equal to one-half of the clock period tck.

FIG. 10 is a block diagram of a computer system 100. The computer system 100 utilizes a memory controller 102 in communication with SDRAMs 104 through a bus 105. The memory controller 102 is also in communication with a processor 106 through a bus 107. The processor 106 can perform a plurality of functions based on information and data stored in the SDRAMs 104. One or more input devices 108, such as a keypad or a mouse, are connected to the processor 106 to allow an operator to manually input data, instructions, etc. One or more output devices 110 are provided to display or otherwise output data generated by the processor 106. Examples of output devices include printers and video display units. One or more data storage devices 112 may be coupled to the processor 106 to store data on, or retrieve information from, external storage media. Examples of storage devices 112 and storage media include drives that accept hard and floppy disks, tape cassettes, and CD read only memories.

While the present invention has been described in conjunction with preferred embodiments thereof, many modifications and variations will be apparent to those of ordinary skill in the art. For example, although the present invention is directed to synchronous mirror delay systems, the present invention is contemplated to be used with any implementable logic devices and in other arrangements, such as in a digital delay locked loop (DDLL), to improve the efficiency in that arrangement. The foregoing description and the following claims are intended to cover all such modifications and variations.

Lin, Feng

Patent Priority Assignee Title
Patent Priority Assignee Title
3947697, Sep 28 1973 ALCATEL N V , A CORP OF THE NETHERLANDS Synchronizing circuit including two flip-flops and circuit means to protect a synchronized signal from an unstable state of the flip-flops
5173617, Jun 27 1988 Freescale Semiconductor, Inc Digital phase lock clock generator without local oscillator
5223755, Dec 26 1990 XEROX CORPORATION, A CORP OF NEW YORK Extended frequency range variable delay locked loop for clock synchronization
5771264, Jan 07 1997 ALTERA CORPORATION A DELAWARE CORP Digital delay lock loop for clock signal frequency multiplication
5940608, Feb 11 1997 Round Rock Research, LLC Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
6018259, Feb 05 1997 Samsung Electronics, Co., Ltd. Phase locked delay circuit
6069506, May 20 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method and apparatus for improving the performance of digital delay locked loop circuits
6069507, May 22 1998 Promos Technologies Inc Circuit and method for reducing delay line length in delay-locked loops
6128248, Nov 11 1996 LONGITUDE SEMICONDUCTOR S A R L Semiconductor memory device including a clocking circuit for controlling the read circuit operation
6140854, Jan 25 1999 Freescale Semiconductor, Inc System with DLL
6166990, Nov 26 1998 Renesas Electronics Corporation Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal
6205086, Apr 28 1999 Longitude Licensing Limited Phase control circuit, semiconductor device and semiconductor memory
6281726, Jun 22 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
6373913, Dec 02 1997 Samsung Electronics Co., Ltd. Internal clock signal generator including circuit for accurately synchronizing internal clock signal with external clock signal
/
Executed onAssignorAssigneeConveyanceFrameReelDoc
Sep 02 2004Micron Technology, Inc.(assignment on the face of the patent)
Date Maintenance Fee Events


Date Maintenance Schedule
Jan 09 20104 years fee payment window open
Jul 09 20106 months grace period start (w surcharge)
Jan 09 2011patent expiry (for year 4)
Jan 09 20132 years to revive unintentionally abandoned end. (for year 4)
Jan 09 20148 years fee payment window open
Jul 09 20146 months grace period start (w surcharge)
Jan 09 2015patent expiry (for year 8)
Jan 09 20172 years to revive unintentionally abandoned end. (for year 8)
Jan 09 201812 years fee payment window open
Jul 09 20186 months grace period start (w surcharge)
Jan 09 2019patent expiry (for year 12)
Jan 09 20212 years to revive unintentionally abandoned end. (for year 12)