A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.
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1. A search engine system, comprising:
a memory bank coupled to a bank selection signal;
a plurality of mask logic blocks, wherein each mask logic block is configured to receive a constructed key and an incoming key mask and to provide a masked key;
a plurality of hash function blocks, wherein each hash function block is configured to receive at least two of the masked keys and to provide at least three hash function outputs; and
a multiplex configured to receive a plurality of hash function outputs and to provide the bank selection signal.
18. A method of searching a table populated with a plurality of entries, comprising the steps of:
constructing a plurality of keys;
performing a key masking on each of the plurality of keys to provide a plurality of masked keys, wherein the plurality of masked keys provide for a bit-by-bit search of the plurality of entries;
performing a hashing on each of the plurality of masked keys;
determining if a system is in a shared mode;
if the system is in the shared mode, sharing a plurality of hash functions for an entry of a memory bank;
if the system is not in the shared mode, hard configuring the hash functions for the entry of the memory bank;
selecting a bucket from the memory bank, wherein the bucket includes the plurality of entries;
applying a local mask;
performing a comparison to provide one or more match indications;
determining a precedence from among the one or more match indications; and
selecting a match from the one or more match indications based on the precedence, the match corresponding to one of the plurality of entries.
2. The search engine system of
the memory bank includes memory that is static random access memory (SRAM) type.
3. The search engine system of
the memory bank is arranged as a plurality of buckets, wherein each bucket includes a plurality of entries.
4. The search engine system of
the bank selection signal is configured to select one of the plurality of buckets.
5. The search engine system of
each of the plurality of entries includes a stored key pattern field, a local mask field, and a hash function indication field.
6. The search engine system of
a comparator configured to provide a match indication for each of the plurality of entries in response to a comparison between the constructed key and the stored key pattern.
7. The search engine system of
the comparator includes an AND-function block configured to provide a masking of the constructed key by applying the local mask field.
8. The search engine system of
in a first mode, each of the plurality of entries is configured to be responsive to any of the plurality of hash function outputs; and
in a second mode, each of the plurality of entries is configured to be responsive to a designated one of the plurality of hash function outputs.
9. The search engine system of
the constructed key includes information from a packet header.
10. The search engine system of
each of the plurality of mask logic blocks includes a logical-AND type function.
11. The search engine system of
each of the plurality of hash function blocks includes:
a first hash function generator configure to receive a first masked key and to provide a first hash function output;
a second hash function generator configured to receive a second masked key and to provide a second hash function output; and
a third hash function generator configured to receive the first masked key and the second masked key and to provide a third hash function output.
12. The search engine system of
the third hash function output is configured for a concatenated key type search.
13. The search engine system of
the concatenated key type search includes a same address selection in a first memory bank and a second memory bank.
14. The search engine system of
each of the first, second, and third hash function generators include a Cyclic Redundancy Code (CRC) type function.
15. The search engine system of
the multiplexer is configured to receive at least eight hash function outputs.
16. The search engine system of
the at least eight hash function outputs includes outputs from at least four different hash function blocks.
17. The search engine system of
the multiplexer is configured to select a different one of the outputs from the at least four different hash function blocks in response to a clock signal.
19. The method of searching the table of
the constructing the plurality of keys includes getting information from a packet.
20. The method of searching the table of
the performing the hashing includes using a Cyclic Redundancy Code (CRC) type function.
21. The method of
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The invention relates generally to the field of search engines and, more particularly, to a method and apparatus for implementing a search engine using a static random access memory (SRAM).
In networking systems, routers and/or switches typically move packets of information from one of a number of input ports to one or more output ports. A lookup function, which can be implemented as a hardware “search engine” or the like, can include a content addressable memory (CAM), but this approach may be relatively expensive. Another approach is to use a standard memory, such as static random-access memory (SRAM), commonly accessed using “hashing” to essentially provide a “many-to-one” function. Such an approach can allow for a smaller memory size so that the overall system cost can be reduced.
Referring now to
Consequently, what is needed is a search engine solution that does not include a CAM structure, but still provides at a relatively low cost, features such as key concatenation, masking of incoming keys, local masking for each stored key, and flexibility in rule sharing through the use of different hash function outputs.
The invention overcomes the identified limitations and provides a relatively low cost search engine solution with multiple advantageous features.
According to embodiments of the invention, a search engine system can include a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs, and multiplexers for receiving hash function outputs and for providing the bank selection signal. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.
According to another aspect of embodiments of the invention, a method of searching a table can include the step of (i) constructing keys; (ii) performing a key masking on each of the keys to provide masked keys; (iii) performing a hashing on each of the masked keys; (iv) determining if a system is in a shared mode; (v) if the system is in the shared mode, sharing hash functions for an entry of a memory bank, but if the system is not in the shared mode, hard configuring the hash functions for the entry of the memory bank; (vi) selecting a bucket from the memory bank; (vii) performing a comparison to provide one or more match indications; and (viii) determining a precedence from among the one or more match indications.
Advantages of the invention include providing a relatively low cost search engine system with features such as key concatenation, masking of incoming keys, local masking for each stored key, and shared rule or fixed rule mode operation.
Embodiments of the invention are described with reference to the FIGS, in which:
Embodiments of the invention are described with reference to specific diagrams depicting system arrangements and methods. Those skilled in the art will recognize that the description is for illustration and to provide the best mode of practicing the invention. The description is not meant to be limiting. For example, reference is made to specific hash function generator types, such as Cyclic Redundancy Code (CRC), but the invention is applicable to other types of functions and/or mappings as well. Also, memory bank fields and/or arrangements thereof in a system merely provide example implementations and should not be construed as limiting. Further, while a specific number of key construction portions as well as a number of memory banks in a system are shown, those skilled in the art will recognize that the invention is applicable to other numbers of key constructions and/or memory banks or the like as well.
Referring now to
In
Referring now to
In the particular example shown in
Referring now to
In
Hash Function 412 shown in
In
Referring now to
According to embodiments of the invention, the search engine can generally be operated in one of two modes: shared hashing or fixed/designated hashing. For shared hashing, each stored entry can be associated with one of up to four hash function outputs or rules. With reference to
Referring back to
Referring now to
Each AND-function output 604-0 through 604-7 can provide an input to corresponding Compare 606-0 through 606-7 blocks. The associated stored key patterns (Stored Key Pattern 0 through Stored Key Pattern 7) can provide a second input to the compare blocks. In this fashion, the “stored” keys can be effectively compared against the incoming key, subject to local mask application. Accordingly, Compare 606-0 through 606-7 outputs can indicate a match or mismatch state for each of the entries of the selected bucket. To accommodate the concatenated entry mode, another set of AND-functions 608-0 through 608-7 can be used. Each of 608-0 through 608-7 can receive a match signal from the local computer block as well as a corresponding match signal from the associated entry of another bank. Other Bank Match (OBM) signals OBM_O through OBM_7. Each AND function block 608-0 through 608-7 can provide an output to Priority Encoder 610 in order to decide a “Winner” for the entries of the selected bucket.
Referring now to
Advantages of the invention include providing a relatively low cost search engine system with features such as key concatenation, masking of incoming keys, local masking for each stored key, and shared rule or fixed rule mode operation.
Having disclosed exemplary embodiments and the best mode, modifications and variations may be made to the disclosed embodiments while remaining within the subject and spirit of the invention as defined by the following claims.
Malalur, Govind, Yang, Brian Hang Wai, Kao, Sophia W.
Patent | Priority | Assignee | Title |
10049126, | Sep 06 2015 | Mellanox Technologies, LTD | Cuckoo hashing with selectable hash |
10068034, | Sep 07 2016 | Mellanox Technologies, LTD | Efficient matching of TCAM rules using hash tables in RAM |
10476794, | Jul 30 2017 | Mellanox Technologies, LTD | Efficient caching of TCAM rules in RAM |
10491521, | Mar 26 2017 | Mellanox Technologies, LTD | Field checking based caching of ACL lookups to ease ACL lookup search |
10496680, | Aug 17 2015 | Mellanox Technologies, LTD | High-performance bloom filter array |
10944675, | Sep 04 2019 | Mellanox Technologies, LTD | TCAM with multi region lookups and a single logical lookup |
11003715, | Sep 17 2018 | MELLANOX TECHNOLOGIES, LTD. | Equipment and method for hash table resizing |
11308057, | Dec 12 2016 | Advanced Micro Devices, Inc.; Advanced Micro Devices, INC | System and method for multiplexer tree indexing |
11327974, | Aug 02 2018 | Mellanox Technologies, LTD | Field variability based TCAM splitting |
11539622, | May 04 2020 | MELLANOX TECHNOLOGIES, LTD. | Dynamically-optimized hash-based packet classifier |
11782895, | Sep 07 2020 | Mellanox Technologies, LTD | Cuckoo hashing including accessing hash tables using affinity table |
11782897, | Dec 12 2016 | Advanced Micro Devices, Inc. | System and method for multiplexer tree indexing |
11917042, | Aug 15 2021 | MELLANOX TECHNOLOGIES, LTD. | Optimizing header-based action selection |
7492763, | Jul 16 2004 | RPX Corporation | User-specified key creation from attributes independent of encapsulation type |
7620781, | Dec 19 2006 | Intel Corporation | Efficient Bloom filter |
8031709, | Jul 16 2004 | RPX Corporation | User-specified key creation from attributes independent of encapsulation type |
8127088, | Jan 27 2005 | Hewlett Packard Enterprise Development LP | Intelligent cache management |
8577921, | Nov 07 2003 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and apparatus for enhanced hashing |
8874876, | Mar 22 2011 | Texas Instruments Incorporated | Method and apparatus for packet switching |
Patent | Priority | Assignee | Title |
5530834, | Mar 30 1993 | International Computers Limited | Set-associative cache memory having an enhanced LRU replacement strategy |
6223172, | Oct 31 1997 | RPX CLEARINGHOUSE LLC | Address routing using address-sensitive mask decimation scheme |
7002965, | May 21 2001 | Cisco Technology, Inc | Method and apparatus for using ternary and binary content-addressable memory stages to classify packets |
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