A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is based at least in part upon the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.
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7. A method for establishing a known timing relationship between a first clock signal and a second clock signal, comprising:
clocking data transfer operations from a transmitter domain to a receiver domain using said first clock signal;
detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain, wherein said edge in said GFC signal is detected by a register arrangement that is clocked using said first clock signal;
manufacturing a common alignment signal within said transmitter domain that is at least in part derived from said GFC signal; and
using said common alignment signal for gating said data transfer operations and for controlling a multiplexer arrangement to output said second clock signal from said transmitter domain to said receiver domain.
12. A computer system provided with circuitry for establishing a known timing relationship between a first clock signal and a second clock signal, said circuitry comprising:
means for clocking data transfer operations from a transmitter domain to a receiver domain using said first clock signal;
a register operating responsive to said first clock signal for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
means for manufacturing a common alignment signal within said transmitter domain that is derived at least in part from said GFC signal; and
a multiplexer arrangement operating to output said second clock signal from said transmitter domain to said receiver domain in response to said common alignment signal, wherein said data transfer operations are gated with said common alignment signal.
1. A system for establishing a known timing relationship between a first clock signal and a second clock signal, comprising:
means for clocking data transfer operations from a transmitter domain to a receiver domain using said first clock signal;
means for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain, wherein said means for detecting an edge comprises a register arrangement that is clocked using said first clock signal;
means for manufacturing a common alignment signal within said transmitter domain that is derived at least in part from said GFC signal; and
a multiplexer arrangement operating to output said second clock signal from said transmitter domain to said receiver domain in response to said common alignment signal, wherein said data transfer operations are gated with said common alignment signal.
20. A circuit for establishing a known timing relationship between two clocks, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to said receiver domain, comprising:
a register operating responsive to said first clock signal for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
a register operating responsive to said first clock signal for registering a system reset signal;
a clearable register having its data input coupled to an OR logic gate and its clear terminal coupled to an output from said register for registering said system reset signal, wherein a first input of said OR logic gate is driven by an output from said register for detecting said edge in said GFC signal and a second input of said OR logic gate is coupled to said clearable register's data output in a feedback loop path, said clearable register operating to manufacture a common alignment signal that is derived at least in part from said GFC signal;
a master register operating responsive to said first clock signal for generating a master register output signal by registering said common alignment signal;
a slave register operating responsive to said first clock signal for generating a slave register output signal by registering said master register output signal;
a first 2:1 multiplexer (MUX) element coupled to said master and slave registers such that its logic low input is driven by said master register output signal and its logic high input is driven by said slave register output signal, wherein said common alignment signal operates to control said 2:1 MUX element for generating a MUX selection control signal;
a second 2:1 MUX element operating responsive to said MUX selection control signal for generating a second clock signal dependent on said first clock signal; and
a third 2:1 MUX element operating responsive to said MUX selection control signal for generating said second clock signal's complement.
2. The system for establishing a known timing relationship between two clocks as set forth in
3. The system for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
4. The system for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
5. The system for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
6. The system for establishing a known timing relationship between two clocks said first clock signal and said second clock signal as set forth in
8. The method for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
9. The method for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
10. The method for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
11. The method for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
13. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
14. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
15. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
16. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
17. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
18. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
19. The computer system provided with circuitry for establishing a known timing relationship between said first clock signal and said second clock signal as set forth in
21. The circuit for establishing a known timing relationship between two clocks as set forth in
22. The circuit for establishing a known timing relationship between two clocks as set forth in
23. The circuit for establishing a known timing relationship between two clocks as set forth in
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Digital electronic systems, e.g., computer systems, often comprise a number of circuit domains that need to communicate with one another using different interfaces, each running at an optimized speed for increased performance. Typically, multiple clock signals having related frequencies are utilized for providing appropriate timing to the interfaces. For instance, a clock signal with a particular frequency may be provided separately to two circuits that are physically spaced apart, wherein one circuit is operable to transmit data to the other. Accordingly, where data is to be transferred at high rates between a transmitting circuit and a receiving circuit, a clock signal is also provided by the transmitting circuit via a separate trace such that data may be registered accurately at the receiving end using a local clock signal that is derived from the transmitted clock signal (which may also be referred to as the transported clock signal). In such applications, it would be necessary that the clock signal used for clocking out data towards the receiving circuit be disposed in a known relationship with the transported clock signal so that proper timing reference may be obtained for capturing the data. There are no known mechanisms that address this requirement, however.
A system and method for establishing a known timing relationship between two clock signals are disclosed. In one embodiment, a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. Circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is derived at least in part from the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.
In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale. Referring now to
Another divider block 215 is also provided for generating a global framework clock (GFC) signal 214 that is substantially slower than the core clock signal used by ICD-TX 202. For example, XTAL 210 may generate a raw 500 MHz clock signal that can be divided to a 250 MHz clock for driving the transmitter domain's clock tree 218. On the other hand, the GFC 214 may be manufactured such that it is 32 times slower than the core clock (i.e., the GFC signal has a single tick for every 32 ticks of the core clock). As will be seen in greater detail hereinbelow, the GFC signal 214 is not only used an overall timing/monitoring reference signal that is provided to all ICDs of the system, but it is also used in a circuit embodiment of the present invention for effectuating a known timing relationship between two independent clock signals.
Data transfer operations are effectuated by a data out block 224 of the transmitter domain that is clocked by TX-CLK 222. Data 226 that is to be transmitted is registered by a data out register stage 225 whose output is provided to a driver/buffer stage 227 coupled to an outgoing data path 206. A common alignment block 228 is operable responsive at least in part to another TX-CLK signal 222 and GFC 215 for outputting a transported clock (QUAD-CLK) signal that is provided to a receiving domain ICD-RX 204 via a clock path 208. Further, the common alignment block 228 is also operable to generate a common alignment control signal that controls register block 225 of the data out block 224 such that data may be transferred only when the control signal is asserted. Data received via data path 206 is staged through a driver/buffer 230 whose output is provided to data registration circuitry 232 of the receiver domain. Conditioned/captured data may thereafter be forwarded to the internal core circuitry 234 thereof. As will be seen below, by deriving the common alignment control signal from the GFC signal and using it for gating the data out operations as well as for generating the transported clock signal, repeatability and reliability of inter-domain data transfer functionality may be ensured.
A receiver DLL 236 is operable with reference to the received QUAD-CLK via clock path 208, whose output is provided to a number of clock buffers that form a clock tree 238 of ICD-RX 204. By way of example, reference numerals 240-1 and 240-2 illustrate two such buffers, RX-CLK-BUFF(1) and RX-CLK-BUFF(2), respectively. The output of the clock buffers is operable as a clock signal (RX-CLK) 242 internal to the receiver domain for timing its operations. Since the receiver's clock signal is derived from the transported clock signal provided by the transmitter, it is necessary that the clock signal used for clocking out data on data path 206 be disposed in a known timing relationship with respect to the transported clock signal so that the incoming data may be accurately registered without incurring transfer-related timing errors.
Taking
As will be set forth below in additional detail, a multiplexer/register arrangement is provided for outputting the transported clock signal in response to the common alignment signal. A master/slave register circuit portion comprising a master register 316 whose Q output is coupled to drive the D input of a slave register 318 is operable to register the OAQ-ALIGN 320 signal twice such that the outputs of the registers, M-REG 322 and S-REG 324, respectively, are supplied to the logic low and logic high inputs of a 2:1 multiplexer (MUX) element 326. MUX 326 is controlled by the OAQ-ALIGN 320 in the generation of a MUX-SEL control signal 328. Further, MUX 326 operates in such a manner that the creation of runt pulses is avoided. A pair of 2:1 MUXes 330A and 330B are provided whose control inputs are driven by MUX-SEL 328 so as to toggle between TX-CLK 222 and its complement TX-CLK-BAR 223. The “0” or logic low input of MUX 330A is tied to “0” whereas the “0” input of MUX 330B is tied to “1”, whereby the MUXes respectively output a logic low and a logic high before a clock signal is generated. Upon the occurrence of MUX-SEL 328, the outputs of the 2:1 MUXes 330A and 330B toggle to their respective active inputs, i.e., TX-CLK and TX-CLK-BAR signals. Each clock output is buffered by a corresponding clock buffer stage 332A or 332B in order to generate a QUAD-CLK-LOW 334A or QUAD-CLK-HIGH 334B that are transmitted to the receiving ICD.
Referring now to
Based on the foregoing Detailed Description, it should be appreciated that an embodiment of the present invention has been provided in accordance herewith for advantageously establishing a known timing relationship between two clocks in a digital electronic system. The known timing relationship may be used by a receiving domain for properly registering the incoming data whereby data transfer errors can be avoided, especially in high-speed data transmission applications.
Although the aforesaid Detailed Description has been set forth with reference to certain illustrations, it is to be understood that the forms of the invention shown and described are to be treated as exemplary embodiments only. For instance, various logic modules, control signals and their logic levels illustrated in the FIGURES of the present patent application may be implemented using a number of different electronic devices and/or gate combinations, with any level of integration. Accordingly, various changes, substitutions and modifications can be realized therein without departing from the spirit and scope of the invention as defined by the appended claims.
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