Switching controller having frequency hopping for power supplies and method therefor

Abstract

A switching controller having frequency hopping is used for reducing the EMI of a power supply. A pattern generator generates a digital pattern code in response to a clock signal. An oscillator generates an oscillation signal for determining a switching frequency of a switching signal. A programmable capacitor coupled to the oscillator modulates the switching frequency in response to the variation of the digital pattern code. An attenuator connected to a voltage feedback loop attenuates a feedback signal. The feedback signal controls the pulse width of the switching signal. A programmable resistor coupled to the attenuator determines an attenuation rate of the attenuator in response to the digital pattern code. The attenuation rate is increased as the switching frequency increases. The pulse width of the switching signal is thus reduced, which compensates the decrease of the switching period and keeps the output power and the output voltage constant.

Description

CROSS REFERENCE

This application is a continuation application of a prior application Ser. No. 10/898,389, filed on Jul. 23, 2004 now U.S. Pat No. 7,203,079. All disclosures are incorporated herewith by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power supply, and more specifically relates to the control of a switching mode power supply.

2. Description of Related Art

Power supplies have been used to convert an unregulated power source to a regulated voltage or current. FIG. 1 shows a traditional power supply, in which a PWM controller 10 generates a switching signal V_PWM for switching a transformer 11 via a transistor 20. The duty cycle of the switching signal V_PWM determines the power delivered from an input of a power source to an output of the power supply. Although the switching technology reduces the size of the power supply, switching devices generate electric and magnetic interference (EMI) that interferes the power source. An EMI filter 15 equipped at an input of the power supply is utilized to reduce the EMI. However, the EMI filter 15 causes power consumption and increases the cost and the size of the power supply. In recent development, many prior arts have been proposed to reduce the EMI by using frequency modulation or frequency hopping. For example, “Effects of Switching Frequency Modulation on EMI Performance of a Converter Using Spread Spectrum Approach” by M. Rahkala, T. Suntio, K. Kalliomaki, APEC 2002 (Applied Power Electronics Conference and Exposition, 2002), 17-Annual, IEEE, Volume 1, 10-14, March, 2002, Pages: 93-99. However, the disadvantage of the prior art is that frequency modulation generates undesirable ripple signal at the output of the power supply. The undesirable ripple signal generated by frequency modulation could be realized by the following description. An output power P_o of the power supply is the product of an output voltage V_o and an output current I_o of the power supply, which is given by,
P_o=Vo×Io=η×P_IN  (1)

An input power P_IN of the transformer 11 and a switching current I_P can be respectively expressed by,

$P_{\mathrm{IN}}=\frac{1}{2\times T}\times L_P\times I_P^2$ $I_P=\frac{V_{\mathrm{IN}}}{L_P}\times T_{\mathrm{ON}}$
Where η is the efficiency of the transformer 11; V_IN is an input voltage of the transformer 11; L_P is a primary inductance of the transformer 11; T is a switching period of the switching signal V_PWM; T_ON is an on-time of the switching signal V_PWM.
The equation (1) can be rewritten as,

$\begin{array}{cc}{P}_O=\eta \times \frac{V_{\mathrm{IN}}^2\times T_{\mathrm{ON}}^2}{2\times L_P\times T}& \left(2\right)\end{array}$

The switching period T varies according to frequency modulation. As shown in equation (2), the output power P_o will vary as the switching period T varies. Therefore, an undesirable ripple signal will be generated as the output power P_o varies.

An object of the present invention is to provide a switching controller having switching frequency hopping to reduce the EMI for a power supply, in which the switching controller of the present invention will not generate the undesired ripple signal at the output of the power supply.

SUMMARY OF THE INVENTION

A switching controller having frequency hopping for power supplies according to the present invention includes a pattern generator, receiving a clock signal and generating a digital pattern code in response to the clock signal. An oscillator produces an oscillation signal to determine a switching frequency of a switching signal. A programmable capacitor coupled to the oscillator is utilized to modulate the switching frequency in response to the digital pattern code. An attenuator is connected to a voltage feedback loop for attenuating a feedback signal, in which the feedback signal is utilized to control the pulse width of the switching signal and to control the output power of the power supply. A programmable resistor is connected to the attenuator for programming an attenuation rate of the attenuator in response to the digital pattern code. The attenuation rate is increased as the switching frequency increases. The pulse width of the switching signal is thus reduced, which compensates the decrease of the switching period and keeps the output power and output voltage of the power supply constant.

A method for generating a hopping frequency through a switching controller is provided. The method comprises: generating a clock signal; generating a digital pattern code in response to said clock signal through a pattern generator; determining a switching frequency of a switching signal through an oscillator, wherein said switching signal is utilized to regulate an output of a power supply, and wherein said switching signal is synchronized with said clock signal; and modulating said switching frequency in response to said digital pattern code through a programmable capacitor coupled to said oscillator.

It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 shows a traditional power supply having an EMI filter.

FIG. 2 shows an embodiment of a switching controller having frequency hopping according to the present invention.

FIG. 3 shows an embodiment of an oscillator according to the present invention.

FIG. 4 shows an embodiment of a pattern generator according to the present invention.

FIG. 5 shows another embodiment of the pattern generator according to the present invention.

FIG. 6 shows a PWM control circuit.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1 shows a traditional power supply having an EMI filter. A PWM controller 10 modulates the pulse width of a switching signal VPWM in response to a feedback signal VFB. The feedback signal VFB is obtained from an optical-coupler 85. An operational amplifier 80 and a reference voltage VREF form an error amplifier to drive the optical-coupler 85. Resistors 72, 73 and the error amplifier form a voltage feedback loop to regulate an output voltage VO of the power supply. A switching current IP of a transformer 11 is converted to a switching-current signal VS through a sense resistor 30. The switching-current signal VS is provided to the PWM controller 10 for the pulse width modulation of the switching signal VPWM.

FIG. 2 is an embodiment of a switching controller having frequency hopping according to the present invention. A clock generator 400 generates a clock signal CK. A pattern generator 300 is utilized to generate a digital pattern code [Mn . . . M1] in response to the clock signal CK. An oscillator 200 is used for determining a switching frequency of the switching signal VPWM. The switching signal VPWM is synchronized with the clock signal CK. A programmable capacitor 290 is coupled to the oscillator 200 for modulating the switching frequency in response to the digital pattern code [Mn . . . M1]. A resistor RA and a resistor RB develop an attenuator 500. The resistor RA is coupled to the voltage feedback loop for attenuating the feedback signal VFB, in which a first terminal of the resistor RA is supplied with the feedback signal VFB. The feedback signal VFB is utilized to control the pulse width of the switching signal VPWM via a PWM control circuit 600 and therefore control the output power of the power supply. A second terminal of the resistor RA is connected to a first terminal of the resistor RB. A second terminal of the resistor RB is connected to a ground reference level. A voltage VB at the first terminal of the resistor RB is outputted from an output of the attenuator 500. A programmable resistor 100 is connected to the output of the attenuator 500 for programming an attenuation rate of the attenuator 500 in response to the digital pattern code [Mn . . . M1]. The attenuation rate is increased whenever the switching frequency increases. The pulse width of the switching signal VPWM is thus reduced, which compensates the decrease in the switching period and keeps the output power and output voltage of the power supply constant.

The programmable resistor 100 comprises switching-resistor sets connected to each other in parallel, in which the switching-resistor sets are formed by resistors R1, R2, . . . , Rn and switches S1, S2, . . . Sn. The switch S1 and the resistor R1 are connected in series. The switch S2 and the resistor R2 are connected in series. The switch Sn and the resistor Rn are connected in series. The digital pattern code [Mn . . . M1] controls switches S1, S2, . . . Sn.

The programmable capacitor 290 comprises switching-capacitor sets connected to each other in parallel, in which the switching-capacitor sets are formed by capacitors C1, C2, . . . Cn and switches X1,X2, . . . Xn. The switch X1 and the capacitor C1 are connected in series. The switch X2 and the capacitor C2 are connected in series. The switch Xn and the capacitor Cn are connected in series. The digital pattern code [Mn . . . M1] controls switches X1, X2, . . . Xn.

FIG. 3 shows an embodiment of the oscillator 200 according to the present invention. A current source I10 produces a charge current ICHG. A current source 120 produces a discharge current IDCHG.

A charge switch S31 is connected between the current source I10 and a capacitor C. A discharge switch S41 is connected between the capacitor C and the current source I20. A comparator 210 has a positive input supplied with a threshold voltage VH. A negative input of the comparator 210 is connected to the capacitor C. A comparator 220 has a negative input supplied with a threshold voltage VL. The threshold voltage VH is higher than the threshold voltage VL. The positive input of the comparator 220 is connected to the capacitor C. An output of a NAND gate 230 generates an oscillation signal PLS to turn on/off the discharge switch S41. A first input of the NAND gate 230 is driven by an output of the comparator 210. Two inputs of a NAND gate 240 are respectively connected to the output of the NAND gate 230 and an output of the comparator 220. The output of the NAND gate 240 is connected to a second input of the NAND gate 230 and turns on/off the charge switch S31.

FIG. 4 shows an embodiment of the pattern generator 300 according to the present invention. A timer 310 generates a binary code [bn . . . b0] in response to the clock signal CK. A read-only-memory 320 generate the digital pattern code [Mn . . . M1] in response to the binary code [bn . . . b0]. The address inputs of the read-only-memory 320 are driven by the output of the timer 310.

FIG. 5 shows another embodiment of the pattern generator 300 according to the present invention. A plurality of registers 331, 332 . . . 335 and a XOR gate 339 develop a linear shift register for generating a linear code in response to the clock signal CK. The inputs of the XOR gate 339 determine the polynomials of the linear shift register and decide the output of the linear shift register. Furthermore, the digital pattern code [Mn . . . M1] can be adopt from the part of the linear code to optimize the application.

FIG. 6 shows an embodiment of the PWM control circuit 600 according to the present invention. The PWM control circuit 600 comprises a comparator 610, a D flip-flop 620 and an AND gate 630. The comparator 610 is used to reset the D flip-flop 620. The voltage VB outputted from the attenuator 500 supplies a positive input of the comparator 610. The switching-current signal VS supplies a negative input of the comparator 610. A D input of the D flip-flop 620 is pulled high by a supply voltage VCC. A clock input of the D flip-flop 620 is supplied with the oscillation signal PLS. A first input of the AND gate 630 is supplied with the oscillation signal PLS. A second input of the AND gate 630 is connected to an output of the D flip-flop 620. An output of the AND gate 630 generates the switching signal VPWM.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A switching controller having frequency hopping, comprising:

a pattern generator, receiving a clock signal and generating a digital pattern code in response to said clock signal;

an oscillator, for determining a switching frequency of a switching signal, wherein said switching signal is utilized to regulate an output of a power supply, and wherein said switching signal is synchronized with said clock signal; and

a programmable capacitor, coupled to said oscillator for modulating said switching frequency in response to said digital pattern code.

2. The switching controller having frequency hopping of claim 1, wherein said programmable capacitor comprises:

switching-capacitor sets, connected to each other in parallel, wherein said switching-capacitor sets are formed by couples of switches and capacitors connected in series respectively, wherein said switches are turned on/off by said digital pattern code.

3. The switching controller having frequency hopping of claim 1, wherein said oscillator comprises:

a charge-current source, for producing a charge current;

a discharge-current source, for producing a discharge current;

an osc capacitor, connected in parallel with said programmable capacitor;

an osc-charge switch, connected between said charge-current source and said osc capacitor;

an osc-discharge switch, connected between said discharge-current source and said osc capacitor;

a first comparator, wherein a positive input of said first comparator is supplied with an first osc-threshold voltage, a negative input of said first comparator is connected to said osc capacitor;

a second comparator, wherein a negative input of said second comparator is supplied with a second osc-threshold voltage, a positive input of said second comparator is connected to said osc capacitor, and wherein said first osc-threshold voltage is higher than said second osc-threshold voltage;

a first NAND gate, for producing an oscillation signal for determining said switching frequency, wherein a first input of said first NAND gate is driven by an output of said first comparator, and wherein an output of said first NAND gate turns on/off said osc-discharge switch; and

a second NAND gate, wherein two inputs of said second NAND gate are respectively connected to said output of said first NAND gate and an output of said second comparator, wherein an output of said second NAND gate is connected to a second input of said first NAND gate, and wherein said output of said second NAND gate turns on/off said osc-charge switch.

4. The switching controller having frequency hopping of claim 1, further comprising:

an attenuator, coupled to a voltage feedback loop for attenuating a feedback signal, wherein said feedback signal is utilized to control the pulse width of said switching signal.

5. The switching controller having frequency hopping of claim 4, wherein the switching controller further comprises:

a programmable resistor, connected to said attenuator for programming an attenuation rate of said attenuator in response to said digital pattern code.

6. A method for generating a hopping frequency through a switching controller, comprising:

generating a clock signal;

generating a digital pattern code in response to said clock signal through a pattern generator;

determining a switching frequency of a switching signal through an oscillator, wherein said switching signal is utilized to regulate an output of a power supply, and wherein said switching signal is synchronized with said clock signal; and

modulating said switching frequency in response to said digital pattern code through a programmable capacitor coupled to said oscillator.

7. The method of claim 6, wherein said programmable capacitor comprises:

switching-capacitor sets, connected to each other in parallel, wherein said switching-capacitor sets are formed by couples of switches and capacitors connected in series respectively, wherein said switches are turned on/off by said digital pattern code.

8. The method of claim 6, wherein said oscillator comprises:

a charge-current source, for producing a charge current;

a discharge-current source, for producing a discharge current;

an osc capacitor, connected in parallel with said programmable capacitor;

an osc-charge switch, connected between said charge-current source and said osc capacitor;

an osc-discharge switch, connected between said discharge-current source and said osc capacitor;

a first comparator, wherein a positive input of said first comparator is supplied with an first osc-threshold voltage, a negative input of said first comparator is connected to said osc capacitor;

a second comparator, wherein a negative input of said second comparator is supplied with a second osc-threshold voltage, a positive input of said second comparator is connected to said osc capacitor, and wherein said first osc-threshold voltage is higher than said second osc-threshold voltage;

a first NAND gate, for producing an oscillation signal for determining said switching frequency, wherein a first input of said first NAND gate is driven by an output of said first comparator, and wherein an output of said first NAND gate turns on/off said osc-discharge switch; and

a second NAND gate, wherein two inputs of said second NAND gate are respectively connected to said output of said first NAND gate and an output of said second comparator, wherein an output of said second NAND gate is connected to a second input of said first NAND gate, and wherein said output of said second NAND gate turns on/off said osc-charge switch.

9. A switching controller having frequency hopping, comprising:

a pattern generator, receiving a clock signal and generating a digital pattern code in response to said clock signal;

an oscillator, for determining a switching frequency of a switching signal, wherein said switching signal is utilized to regulate an output of a power supply; and

a frequency modulating circuit, coupled to said oscillator for modulating said switching frequency in response to said digital pattern code.

10. The switching controller having frequency hopping of claim 9, wherein said switching signal is substantially synchronized with said clock signal.

11. The switching controller having frequency hopping of claim 9, wherein the frequency modulating circuit is a programmable capacitor.

12. The switching controller having frequency hopping of claim 11, wherein said programmable capacitor comprises:

switching-capacitor sets, connected to each other in parallel, wherein said switching-capacitor sets are formed by couples of switches and capacitors connected in series respectively, wherein said switches are turned on/off by said digital pattern code.

13. The switching controller having frequency hopping of claim 9, further comprising:

an attenuator, coupled to a voltage feedback loop for attenuating a feedback signal, wherein said feedback signal is utilized to control the pulse width of said switching signal.

14. The switching controller having frequency hopping of claim 13, wherein the switching controller further comprises:

a programmable resistor, connected to said attenuator for programming an attenuation rate of said attenuator in response to said digital pattern code.