A series pass transistor voltage regulator is described having a main power source and an auxiliary power source. When the main power source voltage falls to a level the regulator can no longer use, the regulator seamlessly draws power from the auxiliary source. A voltage dropping circuit of two series-coupled diodes allows for a single feedback control amplifier to control the regulator's pass transistors in series with the main and auxiliary power sources.

Patent
   7482711
Priority
Sep 30 2004
Filed
Jul 05 2005
Issued
Jan 27 2009
Expiry
May 26 2026
Extension
325 days
Assg.orig
Entity
Large
3
19
EXPIRED
1. A voltage regulator switch mechanism comprising:
a first pass transistor, having a control terminal, and coupled between a first power supply node and an output node;
a second pass transistor, having a control terminal, and coupled between a second power supply node and the output node;
a differential amplifier having an input coupled to the output node and an output coupled to the control terminal of the first pass transistor; and
a voltage dropping circuit connected between the output of the amplifier and the second pass transistor control terminal for switching between the first power supply node and the second supply node when the value of the first power supply drops below the value associated with the voltage dropping circuit such that the voltage dropping circuit turns on the second pass transistor.
2. The voltage regulator switch mechanism of claim 1, wherein the voltage dropping circuit comprises at least one series-coupled diode.
3. The voltage regulator switch mechanism of claim 2, wherein the voltage dropping circuit comprises a pair of series-coupled diodes.
4. The voltage regulator switch mechanism of claim 1, wherein the first and second pass transistors comprise bipolar devices.
5. The voltage regulator switch mechanism of claim 1, wherein the first and second pass transistors comprise MOS devices.
6. The voltage regulator switch mechanism of claim 1, wherein the switch mechanism further comprises a temperature stability arrangement comprising
a “T” network of a pair of steering diodes and a resistive element coupled between the first and second input nodes and the control terminal of the second pass transistor.
7. The voltage regulator switch mechanism of claim 1, wherein the switch mechanism further comprises a protection diode coupled between the second pass transistor and the output node.
8. The voltage regulator switch mechanism of claim 1, wherein the switch mechanism further comprises a protection diode coupled between the first pass transistor and the output node.
9. The voltage regulator switch mechanism of claim 1, wherein the switch mechanism further comprises
a first protection diode coupled between the first pass transistor and the output node; and
a second protection diode coupled between the second pass transistor and the output node.

This application claims the benefit of U.S. Provisional Application No. 60/614,961, filed Sep. 30, 2004.

The present invention relates to power supplies generally and, more particularly, to voltage regulators.

Industry standards have been widely relied upon in the design and manufacture of a number of computer system components and functions. One particular example is computer bus architectures. Generally speaking, computer bus architectures are concerned with the interface and communication between processing, memory and input/output computer system components. One commonly-used bus interface is defined as “Peripheral Component Interconnect” (PCI). At the time it was developed, PCI was a very advanced, high-performance parallel bus standard. More recently, a newer bus standard has been developed to more fully utilize new communication technologies (e.g., packet-based, point-to-point communication). This standard is referred to as “PCI Express”.

This newer PCI Express standard defines the auxiliary power (Vaux) to be at the same voltage level as the primary power supply. That is, the auxiliary power is defined as 3.3 Vaux, with the primary supply being +3.3V. The use of the same voltage levels makes it significantly more difficult to design a seamless Vaux switch mechanism for the PCI Express standard. In the prior PCI standard (PCI 2.2 in particular), the primary supply was maintained at a voltage level of 5.0 volts, with Vaux at 3.3 volts. There exists a variety of commercially-available products capable of providing relatively seamless switching between these two different power supplies. The ability to “seamlessly” switch (i.e., abruptly switching sources without any interruption in supplied voltage) to and from Vaux is an important capability for PCI Express add-in cards.

Prior art arrangements that are intended for the older PCI 2.2 standard typically add more circuitry, complexity and cost to the power supply by performing the primary/Vaux power supply switching as a stand-alone function on the power input lines. Moreover, existing prior art devices do not allow a voltage offset for the switch between the primary and Vaux power supplies while operating both rails at 3.3 volts. Such an offset is highly desirable in the PCI Express environment to ensure that the plug-in card operates on the correct supply at all times, even if the supplies are at the far limits of their respective tolerance ranges.

The need remaining in the prior art is addressed by the present invention, which relates to power supplies generally and, more particularly, to voltage regulators.

In accordance with the present invention, a voltage regulator is constructed to include a first pass transistor coupled between a first power supply node and the output, and a second pass transistor coupled between a second power supply node and the output. A differential amplifier is coupled between the output node and a control terminal of the first pass transistor, with a voltage dropping circuit connected between the output of the differential amplifier and a control terminal of the second pass transistor.

In one embodiment of the present invention, a closed-loop linear series voltage regulator coupled between the primary supply and the regulated output line is supplemented by a second series drop element disposed between the Vaux power supply and the same regulated output. One or more diodes are coupled between the primary control line and the Vaux control line to provide the desired voltage offset. In a particular arrangement, switching transistors are utilized as the series drop elements.

Various embodiments of the present invention may be formed in either bipolar or MOS technology, with additional components used to insure proper operation under a variety of different circumstances.

Other and further aspects and embodiments of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.

Referring now to the drawings, where like numerals represent like elements in different embodiments,

FIG. 1 illustrates a first embodiment of the present invention, utilizing a pair of diodes between the primary control line and the Vaux control line;

FIG. 2 is an alternative embodiment of the arrangement of FIG. 1 with additional elements utilized to provide temperature stability;

FIG. 3 illustrates yet a further variation of the present invention, incorporating a steering diode to prevent reverse current flow; and

FIG. 4 contains an alternative embodiment of the present invention, formed using MOS devices.

FIG. 1 illustrates a first embodiment of a switchable voltage regulator for PCI Express applications, formed in accordance with the present invention. As shown, a differential amplifier 10 and a first transistor 12 are coupled together to form a conventional closed-loop linear series voltage regulator to provide a substantially constant voltage output Vout along output voltage rail 14. In one particular embodiment, the Vout level may be approximately 1 volt. As shown, a reference voltage source, denoted Vref is applied as a first input to differential amplifier 10, with the remaining input being coupled to Vout. The output voltage from amplifier 10 is coupled to the base of first transistor 12 and used, as discussed below, as the control signal for the switching function of the present invention.

As shown, the emitter of first transistor 12 is coupled to primary voltage supply rail 16, where in the case of PCI-Express, the primary voltage is maintained at +3.3 volts. To complete the circuit, the collector of first transistor 12 is coupled to output voltage rail 14, supplying a voltage level of, for example, of 1 volt.

In accordance with the present invention, a second linear drop element, shown as transistor 18 and a pair of diodes 20, 22 are added to the voltage regulator to provide the desired Vaux switching function. As shown, second transistor 18 is connected between a Vaux voltage input supply rail 24 and Vout regulated voltage output rail 14. Diodes 20 and 22 are connected in series between the base of second transistor 18 and the base of first transistor 12. The voltage drop vd across each of these diodes (on the order of, for example, 0. 5 volts) is therefore sufficient to provide a voltage drop exceeding the 0.6 volt tolerance difference desired between the primary +3.3 volt source and the 3.3 Vaux source, with sufficient headroom remaining to control the power devices. It is to be understood that the use of a pair of such diodes is exemplary only, with more or less diodes or other voltage-dropping elements used (as necessary) to provide the desired amount of offset for the switching function.

As required by the PCI Express standard, if 3.3 Vaux is not present, the arrangement of FIG. 1 simply runs from primary rail 16, supplying the +3.3 voltage through first transistor 12 and into the Vout regulated output supply rail 14. In this mode, without Vaux present, second transistor 18 will be “off”. In accordance with the teachings of the present invention, If/when the voltage along rail 16 drops below the level from which first transistor 12 can be regulated (i.e., “Vref”), the control signal output from amplifier 10 will abruptly drop by the voltage level associated with diodes 20 and 22, second transistor 18 will turn “on”, and the regulation will begin through second transistor 18 from Vaux supply rail 24. The provision of the supply voltage from Vaux supply rail 24 still maintains the minimum dropout voltage provided by second transistor 18.

Once the +3.3 voltage level is regained along primary supply rail 16, the control signal output from amplifier 10 will increase, following the increase along primary supply rail 16 and regulation will seamlessly be resumed again through first transistor 12, with second transistor 18 simultaneously turning “off”. Thus, in accordance with the teachings of the present invention, the utilization of the switching transistors and diode drops, in combination with the closed-loop voltage regulator, allows for seamless transition between the primary voltage supply and the Vaux power supply.

FIG. 2 illustrates an alternative embodiment of the present invention, with a second pair of diodes 26, 28 and resistor 30 added to provide for wide temperature stability, while also assuring that the leakage current through second transistor 18 will remain sufficiently low. It is to be understood that the addition of these components is not required in every application of the voltage regulation arrangement of the present invention. FIG. 3 contains a schematic of yet a further variation of the present invention, in this case adding a steering diode 32 to limit (prevent) reverse current flow from regulated output rail 14 and input rail 16. In the arrangement as illustrated in FIG. 3, diode 32 is coupled between the collector of first transistor 12 and output supply rail 14. Although diode 32 needs to carry the full current of the primary supply voltage, the drop across this element is not critical since it is compensated for by the normal function of the regulator arrangement. In some applications, if the system voltage levels are such that second transistor 18 may inadvertently be turned “on”, a second diode 34 may be disposed between the collector of second transistor 18 and supply rail 14 to prevent reverse flow through 3.3 Vaux input supply rail 24.

As mentioned above, the voltage regulator of the present invention may be formed of MOS devices in place of bipolar devices. FIG. 4 illustrates an exemplary embodiment of the present invention formed using MOS devices 40 and 42 as first and second transistors, respectively. To mitigate the potential current flow from the regulated output through the MOSFET substrate (reverse) diode, both steering diodes 32 and 34 should be used. Remaining elements 20, 22, 26, 28 and 30 function in a similar manner as discussed above in association with FIGS. 1-3. Inasmuch as the threshold voltages associated with MOS devices may be different than those for bipolar devices, the particular diodes selected for use in this embodiment (in terms of voltage drop) may be different than those preferred for use with the bipolar embodiment of FIGS. 1-3.

It is to be understood that various modifications may be made to the present invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specification embodiments disclosed in the specification and claims. Rather, the scope of the present invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Blaha, Matthew

Patent Priority Assignee Title
11043488, Jan 24 2019 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
11581305, Jan 24 2019 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
7734953, Jun 12 2006 American Megatrends, Inc. Redundant power solution for computer system expansion cards
Patent Priority Assignee Title
5412716, May 03 1993 AT&T IPM Corp System for efficiently powering repeaters in small diameter cables
5559423, Mar 31 1994 Nortel Networks Limited Voltage regulator including a linear transconductance amplifier
5752046, Jan 14 1993 Apple Inc Power management system for computer device interconnection bus
5864225, Jun 04 1997 Fairchild Semiconductor Corporation Dual adjustable voltage regulators
5898844, Sep 13 1996 International Business Machines Corporation Data processing system including a hot-plug circuit for receiving high-power adaptor cards
6462926, Dec 15 1999 CIENA LUXEMBOURG S A R L ; Ciena Corporation Low loss diode-oring circuit
6513128, Nov 30 1999 HEWLETT-PACKARD DEVELOPMENT COMPANY, L P Network interface card accessible during low power consumption mode
6560713, Dec 31 1998 Intel Corporation Computer power management system using auxiliary power supply during sleep state to provide power to all devices if sufficient and reducing load if not sufficient
6580710, Nov 19 1999 AT&T Corp. Method and apparatus for facilitating intra-premises voice and data distribution using existing in-place POTS telephone lines
6681335, Jun 26 2000 Intel Corporation System for controlling power plane of a printed circuit board by using a single voltage regulator to control switches during first and second power modes
6780018, Jul 14 2003 Hon Hai Precision Ind. Co., Ltd. Electrical connector with power module
6800962, Jan 16 2002 Adtran, Inc. Method and apparatus for forced current sharing in diode-connected redundant power supplies
7221106, Oct 19 1999 X-L Synergy Cordset based appliance controller
20020141492,
20040217653,
20050022035,
20050022036,
20050034045,
20050060587,
///////////
Executed onAssignorAssigneeConveyanceFrameReelDoc
Jun 27 2005BLAHA, MATTHEWAGERE Systems IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0167340322 pdf
Jul 05 2005Agere Systems Inc.(assignment on the face of the patent)
May 06 2014LSI CorporationDEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTPATENT SECURITY AGREEMENT0328560031 pdf
May 06 2014Agere Systems LLCDEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTPATENT SECURITY AGREEMENT0328560031 pdf
Aug 04 2014Agere Systems LLCAVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0353650634 pdf
Feb 01 2016DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTAgere Systems LLCTERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS RELEASES RF 032856-0031 0376840039 pdf
Feb 01 2016DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTLSI CorporationTERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS RELEASES RF 032856-0031 0376840039 pdf
Feb 01 2016AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD BANK OF AMERICA, N A , AS COLLATERAL AGENTPATENT SECURITY AGREEMENT0378080001 pdf
Jan 19 2017BANK OF AMERICA, N A , AS COLLATERAL AGENTAVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS0417100001 pdf
May 09 2018AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITEDMERGER SEE DOCUMENT FOR DETAILS 0471950827 pdf
Sep 05 2018AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITEDCORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827 ASSIGNOR S HEREBY CONFIRMS THE MERGER 0479240571 pdf
Date Maintenance Fee Events
Jul 07 2009ASPN: Payor Number Assigned.
Jun 27 2012M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Jun 24 2016M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Sep 14 2020REM: Maintenance Fee Reminder Mailed.
Mar 01 2021EXP: Patent Expired for Failure to Pay Maintenance Fees.


Date Maintenance Schedule
Jan 27 20124 years fee payment window open
Jul 27 20126 months grace period start (w surcharge)
Jan 27 2013patent expiry (for year 4)
Jan 27 20152 years to revive unintentionally abandoned end. (for year 4)
Jan 27 20168 years fee payment window open
Jul 27 20166 months grace period start (w surcharge)
Jan 27 2017patent expiry (for year 8)
Jan 27 20192 years to revive unintentionally abandoned end. (for year 8)
Jan 27 202012 years fee payment window open
Jul 27 20206 months grace period start (w surcharge)
Jan 27 2021patent expiry (for year 12)
Jan 27 20232 years to revive unintentionally abandoned end. (for year 12)