Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field effect transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word. A similar method for a PFET EEPROM is also disclosed.
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4. A single nonvolatile memory cell, comprising:
a field effect transistor having a drain, a source, a floating gate and a control gate;
a resistor with a first end and a second end, said first end being coupled to said drain and said second end being capable of being coupled to a source of a low voltage; and
a source of multiple voltage levels capable of being coupled to said control gate for providing a selected voltage representable by multiple-bits to be stored in said nonvolatile memory cell.
1. A structure for storing in a single nonvolatile memory cell any one of the values capable of being represented by a given number of bits, comprising:
a nonvolatile memory cell having an FET with a control gate, a source region, and a drain region, and having a resistor one end of which is coupled to said drain region and the other end of which is capable of being coupled to a source of a high voltage; and
said control gate being capable of being coupled to a source of multiple values of voltages, each of said voltages representing a value of multi-bits to be stored in said nonvolatile memory cell.
7. A method for storing information capable of being represented by a multiple bit binary word in a single nonvolatile memory cell, comprising:
programming a nonvolatile memory cell to the highest threshold voltage to which said nonvolatile memory cell can be programmed by applying a high voltage to both a control gate and to a drain electrode of said nonvolatile memory cell; and
erasing down from said highest threshold voltage to a specific threshold voltage by applying a voltage selected from a plurality of different voltages to said control gate by selecting a resistor having an appropriate value of resistance to couple between said drain electrode and a source of said high-voltage.
10. A method for storing any one of a plurality of voltages, each voltage capable of being represented by a multiple bit binary word, in a single nonvolatile memory cell having a substrate, a source, a drain, and a control gate, comprising:
programming said nonvolatile memory cell to a most negative threshold voltage by applying a high voltage both to said source and to said substrate; and
erasing up from said most negative threshold voltage to a specific negative threshold voltage level by applying a voltage selected form a plurality of different voltages to said control gate by selecting a resistor having an appropriate value of resistance to couple between said drain electrode and said source of high voltage.
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1. Field of the Invention
The invention relates to an Electrically Erasable Programmable Read-Only Memory (EEPROM), and more specifically, to structures and methods for enabling multiple threshold voltage operation in single EEPROM cell.
2. Description of the Prior Art
Semiconductor non-volatile memory (NVM), and particularly electrically erasable, programmable read-only memory (EEPROM), is used in a range of electronic equipment from computers, to telecommunications hardware, to consumer appliances, and to subscriber identity modules (SIMs) for mobile phones. In general, EEPROMs serve a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and yet can be altered as needed. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis.
As is well known to those skilled in the art and as shown in
The single-poly NVM cell architecture shown in
The structure of a split-gate NVM shown in
Data is stored in an EEPROM cell by modulating the threshold voltage, Vth, of the FET through the injection of charge carriers into the charge-storage layer from the channel of the FET. For example, with respect to an N channel FET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the FET to exhibit a relatively high positive Vth. When the FET control gate is biased to the voltage required to read stored data, the FET, with a fixed drain voltage, will respond with different source-to-drain currents according to its Vth level. The different source-to-drain current responses can be recognized and converted to the original bit information stored on the charge storage layer of the FET.
The number of bits stored in an EEPROM cell is determined by the number of different current responses, given by number-of-bits=log2 (number of current responses). The more different current responses that can be sensed and resolved, the more bits that can be stored in a single device cell. In modem sense amplifier (SA) design, the current can be measured with very high accuracy and speed. Usually reference cells are used to compare the current response and determines the bit-level information. However, the major challenge to achieving multi-bit storage in a single device cell is to accurately program or erase the charge-storage layer so as to achieve a designated threshold voltage level which results in a consistent device current response under the read operation.
In the conventional write and erase schemes, Drain-Avalanche-Hot Carrier Injection (DAHCI) and Fowler-Nordheim Tunneling (FNT) have been used for programming and erasing, respectively. The amount of charge injected into/out of the floating gate is controlled by the DAHCI/FNT currents generated by applying voltage pulses to the device gate and electrodes (source, drain, and substrate). Since there is no self-convergent mechanism for DAHCI programming and FNT erasing, the amount of charge in the floating gate which controls and determines the device threshold voltage shift is controlled by the durations of the voltage pulses applied to the gate and to the electrodes. Due to non-uniformity of distributed voltage supply across an integrated circuit memory and the RC time constant delay for a given voltage to reach individual devices in a memory array, the threshold voltage shifts associated with the devices in a memory array after conventional programming and erasing, are usually widely spread out. This hinders multiple-level recognition in a large number of cells in an array memory. To reduce such threshold voltage shift variations, an extra convergent circuit is usually supplied to fine-tune the desired threshold voltage level for each individual device cell in an EEPROM memory array. However, such an approach not only requires a complicated convergence circuit with more silicon area but also requires lengthy and time-consuming convergent procedures during programming.
In view of the aforementioned, the present invention provides an innovative scheme to achieve multiple-bit storage in electrically erasable programmable read-only memories (EEPROMs) to overcome the above drawbacks.
One object of the present invention is to enable multiple threshold voltage operation in a single EEPROM cell. Multiple threshold voltage operation leads to multiple-bits storage in a single cell.
Multiple-bits storage in a single cell can reduce the cost per bit for electrically erasable programmable read-only memories (EEPROMs). For instance, storage of two bits in a single cell can reduce by half the silicon memory cell area. In particular, since this invention applies device self-convergent Drain-Avalanche-Hot Hole Injection (DAHHI) for the NFET EEPROM and Drain-Avalanche-Hot Electron Injection (DAHEI) for the PFET EEPROM, respectively, the complicated convergent circuits to overcome the over-erase issues in the conventional scheme are not required. It further reduces the large silicon area required for such complicated convergent circuits.
One aspect of the present invention is to provide self-convergent programming/erasing structures and methods for storing information capable of being represented by an n-bit binary word, where n is a selected integer, in a single nonvolatile memory cell, comprising: a NFET based nonvolatile memory cell having a source electrode capable of being coupled to a low voltage; and a switching circuit capable of being coupled to a drain of the NFET based nonvolatile memory cell for presenting information representable by an n-bit binary word to be stored in the NFET based nonvolatile memory cell.
The switching circuit includes a plurality of resistors connected in parallel, wherein the plurality of resistors have a common node for connection to a high voltage source. The resistances of the resistors are different from each other. The invention further comprises a control gate voltage switch having one end connected to a control gate and another end capable of being switched between a high voltage and an erase voltage. The nonvolatile memory comprises NFET based electrically erasable programmable read-only memory (EEPROM).
A further aspect of the invention is to provide self-convergent programming/erasing structure for multiple-bit storage in a single nonvolatile memory cell, comprising: an NFET based nonvolatile memory cell having a resistor capable of being coupled between a drain and a high voltage source; and a multiple level voltage-provider coupled to a control gate of the nonvolatile memory cell for presenting a selected voltage representing n bits of information to be stored in the NFET based nonvolatile memory cell. The amplitudes of voltages provided by the multiple level voltage-provider differ from each other. The nonvolatile memory comprises an NFET based electrically erasable programmable read-only memory (EEPROM).
One embodiment of the present invention provides storage of information corresponding to any value of an n-bit binary word, where n is a selected integer, in a single nonvolatile memory cell. In this embodiment, a PFET based nonvolatile memory cell has a source electrode capable of being coupled to a high voltage source; and a switching circuit coupled to a drain of the PFET based nonvolatile memory cell for presenting a voltage representing the n-bit word to be stored in the PFET based nonvolatile memory cell.
The switching circuit includes a plurality of resistors connected in parallel, wherein the plurality of resistors have a common node capable of being connected to a low voltage source. The resistances of said resistors are all different. The present invention further comprises a control gate voltage switch having one end connected to a control gate and another end capable of being switched between a low voltage source and an erase voltage source. The nonvolatile memory comprises PFET based Electrically Erasable Programmable Read-Only Memories (EEPROM).
A further purpose of the present invention is to provide structures and methods for storing information capable of being represented by a multiple bit binary word in a single nonvolatile memory cell, comprising: a PFET based nonvolatile memory cell having a resistor capable of being coupled between a drain and a source of a low voltage; and a source of multiple voltages capable of being coupled to a control gate of the nonvolatile memory cell for representing and presenting the information to be stored in the PFET based nonvolatile memory cell. The nonvolatile memory comprises PFET based electrically erasable programmable read-only memory (EEPROM). The voltage amplitudes provided by the source of multiple voltages are different.
The present invention also provides a method for storing information representable by a multiple bit binary word in a single nonvolatile memory cell, comprising: programming a NFET nonvolatile memory to a highest threshold voltage by applying a high voltage both to a control gate and a drain electrode of the nonvolatile memory; and erasing down from the highest threshold voltage to a specific threshold voltage by applying a gate voltage to the control gate and switching the drain electrode to a port of a switching circuit for presenting to the nonvolatile memory a signal representing the information to be stored in the nonvolatile memory cell. The information to be stored is representable by an n-bit binary word, where n is an integer.
One aspect of the present invention is to provide a method for storing information representable by a multiple bit binary word in a single nonvolatile memory cell, comprising: programming a NFET nonvolatile memory to a highest threshold voltage by applying a high voltage to a control gate and a drain electrode of the NFET based nonvolatile memory; and erasing down from the highest threshold voltage to a specific threshold voltage by applying a specific gate voltage to the control gate with a selected resistor coupling between the drain electrode and the high voltage source.
A further aspect of the invention is to provide a method for storing information representable by a multiple bit binary word in a single nonvolatile memory cell, comprising: programming a PFET based nonvolatile memory to a most negative threshold voltage by applying a high voltage to both a source electrode and a substrate of the PFET nonvolatile memory; and erasing up from the most negative threshold voltage to a specific negative threshold voltage by applying a gate voltage to the control gate and switching the drain electrode to a port of a switching circuit for presenting to the drain a voltage representing the multiple bit binary word to be stored in the PFET nonvolatile memory cell.
Further, the present invention discloses a method for storing information representable by a multiple bit binary word in a single nonvolatile memory cell, comprising: programming a PFET nonvolatile memory to a most negative threshold voltage by applying a high voltage to both a source electrode and to a substrate of the PFET nonvolatile memory; and erasing up from the most negative threshold voltage to a specific negative threshold voltage by applying a specific gate voltage to the control gate with a resistor of a selected value coupling between the drain electrode and a low voltage source.
An embodiment of the invention also provides a method for reading information representable as a multiple bit binary word stored as an electric charge in a single nonvolatile memory cell, comprising: applying a read voltage to a control gate of the nonvolatile memory; and connecting a drain electrode of the nonvolatile memory to a high voltage source through a current load; wherein the driving current of the nonvolatile memory in response to different threshold voltage levels generates different output voltages.
The output voltage in response to the actual threshold voltage can be compared and converted to the original bit representation. To achieve this, the nonvolatile memory comprises an NFET based electrically erasable programmable read-only memory (EEPROM).
Another embodiment of the invention provides a method for reading information representable by a multiple bit binary word stored in a single nonvolatile memory cell, comprising: applying a read voltage to a control gate of the nonvolatile memory; and connecting a drain electrode of said nonvolatile memory to ground through a current sink; wherein the driving current of the nonvolatile memory passing through the current sink generates an output voltage representative of the actual threshold voltage which in turn reflects the value of the information stored in said cell.
The output voltage can be compared and converted to the original bit representation. The nonvolatile memory comprises a PFET based electrically erasable programmable read-only memory (EEPROM).
For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiments of the present invention, in which:
The present invention includes methods and structures to store any one of N voltage values in a single EEPROM cell, where each of the N voltage values can be represented by an n-bit binary word, where n=log2N and N in an integer, such as 8, 16 or 32, representable by a power of 2. Thus if N is 16, n is 4 and a four bit binary code word is sufficient to represent any one of sixteen (16) possible voltage values which can be stored in the EEPROM cell. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, and the scope of the present invention is expressly not limited except as specified in the accompanying claims. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details. In order to avoid obscuring aspects of the invention, well known structures, materials, or operations are often not shown or described.
Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein (both methods and schematics) are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to persons skilled in the art in view of this disclosure.
This invention relates to structures and methods to enable multiple threshold voltage operation in a single EEPROM cell.
Multiple threshold voltage level operation makes possible the storage in a single cell of information representable by any one combination of n bits. Hereinafter, storage of such information in a single cell will sometimes be called “multiple-bit storage”. Multiple-bit storage in a single cell can reduce the cost per bit for Electrically Erasable Programmable Read-Only Memories (EEPROM). For instance, two bits in a single cell can cut in half the silicon memory cell area. In particular, since this invention applies device self-convergent Drain-Avalanche-Hot Hole Injection (DAHHI) for an NFET based EEPROM and Drain-Avalanche-Hot Electron Injection (DAHEI) for a PFET based EEPROM, respectively, the complicated convergent circuits to overcome the over-erase or over-programming issues in conventional prior art structures are not required. This invention further reduces the large silicon area required for such complicated convergent circuits.
This invention applies innovative program/erase methods and structures to achieve precise EEPROM threshold voltages for multiple-bit storage in a single cell.
Similarly, under the conditions of Vg−Vs<Vth0, where Vth0 is the device original threshold voltage, and Vd−Vs<<Vdsat, where Vdsat is the saturation voltage, PFET based EEPROM cells are initially programmed to the most negative threshold voltage Vthmax by Drain-Avalanche-Hot Hole Injection (DAHHI) (
The schematic shown in
The resistor switch shown in
In accordance with this invention, EEPROM devices are initially programmed to the highest state, namely, the highest threshold voltage of the EEPROM devices. The multiple threshold voltages levels possible to be associated with each EEPROM device are divided between the lowest threshold voltage and the highest threshold voltage. Each threshold voltage level corresponds to a unique set of multi-bits. The bits stored in the EEPROM device are given by log2 (number of multiple threshold voltage levels). For example, sixteen threshold voltage levels require four (4) bits. Due to Drain-Induced-Barrier-Lowering (DIBL) from the high voltage Vddh, a moderate control gate voltage, Vge, is sufficient to turn on the NFET EEPROM device, while this moderate control gate voltage is not enough to cause significant tunneling from the floating gate to the control gate which, if it occurred would change the threshold voltage.
The Drain-Avalanche-Hot Carriers (DAHC) are generated in the depleted region near the drain electrode. Since a highly positive voltage much greater than the saturation voltage is supplied to the drain electrode of an NFET, channel electrons are injected and accelerated in the drain depletion region. Electrons in the drain depletion region lose their energies from the impact ionization process. With positive drain potential, electrons flow toward the drain electrode, while most holes move toward the substrate. However, some hot holes gaining greater energies than the oxide energy barrier (3.7 ev) are able to reach and annihilate electrons in the floating gate, shown in
To enable the erase-down process, the voltage amplitudes applied to control gate 7n are all large enough to turn on the NFET device. The horizontal potential difference between the pinch-off point of the NFET device and the drain voltage is Vd−Vsat and the vertical potential difference is Vd−Vf (see
A simple schematic for the “READ” operation is shown in
The schematic shown in
To illustrate the write-up process, the drain electrode of the PFET cell is brought by switch 130 into contact with resistor R2 connected to low voltage Vss, as shown in
The Drain-Avalanche-Hot Carriers (DAHC) are generated in the depleted region near the drain electrode. Since the drain electrode is supplied with a highly negative voltage more negative than the saturation voltage relative to the source, channel holes are injected and accelerated in the drain depletion region. Holes in the drain depletion region lose their energies from the impact ionization process. With the negative drain potential, holes flow toward the drain electrode, while most electrons move toward the substrate. However, some hot electrons gaining greater energy than the oxide energy barrier (3.1 ev) are able to reach and annihilate holes in the floating gate 5p, shown in
To enable the erase-up process, the amplitudes of the voltages applied to control gate 7p are all low enough to turn on the device. The potential difference between the pinch-off point of the PFET and the drain voltage is Vd−Vsat and the vertical potential difference is Vd−Vf. The hot electrons injected into the floating gate 5p from the depletion region have energy given by the absolute value of e(Vs−Vsat), and the absolute value of e(Vd−Vf) where e is the electron charge. When the drain voltage Vd is raised to some point such that hot electrons in the depletion region do not have enough energy to flow over the oxide barrier 4p (3.1 volts), the number of holes in the floating gate 5p remains a constant leading to a specific less negative threshold voltage for the PFET EEPROM device. The drain voltage Vd is given by Vss+IdR (
A simple schematic for “READ” operation is shown in
In conclusion, structures and methods are disclosed to achieve multi-bit storage in a single EEPROM cell both for NFET-based and PFET-based nonvolatile memories. The disclosed structures are simple and do not need complicated convergent circuits. With the advantages of larger bit capacity for a single cell and no convergent circuit, the disclosed structures will dramatically reduce the cost per bit for EEPROM capable of storing multi-bit values.
As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative rather than limiting. Having described the invention in connection with preferred embodiments, modifications will now suggest themselves to those skilled in the art. Thus, the invention is not to be limited to the embodiments described but rather includes various modifications and similar arrangements within the spirit and scope of the appended claims. The scope of the claims should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. While the preferred embodiments of the invention have been illustrated and described, various changes can be made therein without departing from the spirit and scope of the invention.
Patent | Priority | Assignee | Title |
7656704, | Jul 20 2006 | Winbond Electronics Corp. | Multi-level operation in nitride storage memory cell |
7778081, | Nov 26 2007 | Macronix International Co., Ltd. | Method for performing operations by applying periodic voltage pulses to control gate of an ono memory cell |
9779814, | Aug 09 2011 | SYNERGER INC | Non-volatile static random access memory devices and methods of operations |
Patent | Priority | Assignee | Title |
6212100, | Jul 23 1996 | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | Nonvolatile memory cell and method for programming and/or verifying the same |
6982903, | Jun 09 2003 | NANTERO, INC | Field effect devices having a source controlled via a nanotube switching element |
7099192, | Jun 07 2004 | Yield Microelectronics Corp. | Nonvolatile flash memory and method of operating the same |
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