A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of jfet regions separated by portions of the drift region. Each of the jfet regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each jfet region is lined with an oxide layer. In one group of embodiments the jfet regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each jfet region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the jfet regions and in the drift region that separates the jfet regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the jfet regions from diffusing into the drift region and allowing the jfet regions to be accurately located in the drift region.
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17. A diode formed in a semiconductor chip comprising:
a first portion of a p-type anode region at a first surface of the chip, the first portion of the anode region being in electrical contact with an anode contact;
an N-type cathode region at the first surface of the chip;
an N-type drift region located between the first portion of the anode region and the cathode region, the drift region having an N-type doping concentration less than a doping concentration of the cathode region; and
a plurality of jfet regions, each of said jfet regions being formed in a trench, each trench extending downward from the first surface of the chip and being bounded by lateral walls and a floor, the lateral walls of each trench being lined with a dielectric layer, each of the trenches containing a second portion of the anode region electrically contacted by the anode contact, along with a single-crystal p-type semiconductor material, the trenches being laterally spaced apart from each other such that portions of the drift region lie between the trenches.
1. A lateral field-effect device formed in a semiconductor chip comprising:
a first portion of a source region of a first conductivity type in the semiconductor chip adjacent a first surface of the chip, the first portion of the source region being in electrical contact with a source contact;
a drain region of the first conductivity type adjacent the first surface of the chip;
a gate overlying the first surface of the semiconductor chip and separated from the first surface of the semiconductor chip by a gate dielectric layer;
a channel region of a second conductivity type opposite to the first conductivity type in the semiconductor chip, the channel region underlying the gate dielectric layer;
a drift region of the first conductivity type in the semiconductor chip, the drift region adjoining the drain region and being located between the drain region and the channel region; and
a plurality of jfet regions, each of said jfet regions being formed in a trench extending downward from the first surface of the semiconductor chip, each trench being bounded by lateral walls and a floor, the lateral walls of each trench being lined with a dielectric layer, each trench containing a second portion of the source region electrically contacted by the source contact, along with a single-crystal semiconductor material of the first conductivity type, the trenches being laterally spaced apart from each other such that portions of the drift region lie between the trenches.
10. A mosfet formed in a semiconductor chip comprising:
a semiconductor substrate of a first conductivity type;
an epitaxial layer of a second conductivity type opposite to the first conductivity type formed on the substrate;
a drain region of the second conductivity type located at a first surface of the epitaxial layer;
a drift region of the second conductivity type located at the first a surface of the epitaxial layer, the drift region abutting a boundary of the drain region, the doping concentration of the drift region being less than the doping concentration of the drain region;
a channel region of the first conductivity type located at the first surface of the epitaxial layer, the channel region abutting the drift region;
a first portion of a source region of the second conductivity type located at the first surface of the epitaxial layer, the first portion of the source region abutting the channel region and being in electrical contact with a source contact;
a gate positioned over the channel region, the gate being separated from the epitaxial layer by a dielectric layer; and
a plurality of jfet regions, each jfet region being formed in a trench, each of the trenches abutting an edge of the drain region and extending outward from the drain region, each trench being bounded by lateral walls and a floor and extending from the first surface of the epitaxial layer to an interface between the epitaxial layer and the substrate, the lateral walls of each trench being lined with an oxide layer, each trench containing a second portion of the source region electrically contacted by the source contact, along with an epitaxial layer of the first conductivity type, the trenches being separated from each other at least in Dart by a portion of the drift region.
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11. The mosfet of
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This invention relates to high voltage devices and in particular to a high-voltage field-effect transistor such as a metal-oxide-silicon field-effect transistor or an insulated gate bipolar transistor.
In the field of field-effect transistors there is a continual quest for devices that approximate an ideal switch, that is, devices that have a very low-resistance when they are turned on and a high voltage-blocking capability when they are turned off. Another objective is a size that occupies minimal “real estate” on today's miniaturized semiconductor chips.
In accordance with the Reduced Surface Field (RESURF) principle, it is known to provide an extended “drift” region in a field-effect transistor, which in a MOSFET is an extension of the drain region. The charge in the drain extension must be carefully controlled to obtain a high Vbd. The RESURF principle was advanced in an article titled “High Voltage Thin Layer Devices (RESURF Devices),” by Appels and Vaes, IEDM Tech. Digest, pp. 238-241 (1979). The drift region permits a more gradual voltage drop across the terminals and reduces the possibility of avalanche breakdown in this area of the device.
As shown in the cross-sectional view of
To increase the voltage-blocking capability of MOSFET 10, an extended drain or drift region 117 is interposed laterally between channel region 116 and N+ drain region 110. Drift region 117 is generally lightly-doped. When MOSFET is turned off, the voltage drop between N+ source region 111 and N+ drain region 110 is partially absorbed in drift region 117, increasing the ability of MOSFET 10 to withstand a large voltage.
This increased voltage-blocking capability comes at a price, however. When MOSFET 10 is turned on, the channel region 116 is inverted and current flows between N+ source region 111 and N+ drain region 110. The presence of the lightly-doped drift region 117 in the current path between N+ source region 111 and N+ drain region 110 increases the on-resistance of MOSFET 10.
U.S. Pat. No. 6,800,903 proposed an alternative solution, which is illustrated in
When MOSFET 20 is in the off state, P buried layers 120 and 121 and the portions of N drift region 117 above and below and between P buried layers 120 and 121 are mutually depleted of free carriers. The portions of N drift region 117 that are above and below and between P buried layers 120 and 121 act as parallel JFET channels, and the current is effectively pinched off in these JFET channels when MOSFET 20 is turned off. This feature provides MOSFET 20 with a greater current-blocking capability that it would have if P buried layers 120 and 121 were not present. For this reason, the doping concentration of N drift region 117 can be higher than it would have to be in order to block current if P buried layers 120 and 121 were not present. For example, the '903 patent suggests that the combined charge in the portions of N drift region 117 above and below and between P buried layers 120 and 121 can be as high as 3×1012 cm−2, which reduces the on-resistance of the device to about one-third of what it would ordinarily be. To keep the strength of the electric field at a level below the critical level at which avalanche breakdown occurs, the charge in each of P buried layers 120 and 121 and the portions of N drift region 117 that are above and below and between them is balanced.
P buried layers 120 and 121 are formed by high-energy implants of a P-type dopant such as boron. The dose and energy of the implants are chosen to provide buried layers of the desired depth and charge concentration. Despite efforts to restrict the dopant to the desired location within the substrate, however, in practice the charge in the buried layers tends to diffuse outwards in three dimensions (both laterally and vertically), particularly if the device is subjected to any thermal processing after the buried layers are implanted. This outdiffusion of dopant makes the device difficult to manufacture.
In addition, a structure that includes alternating shallow P-type pillars in the N-drift region has been reported to improve the trade-off between on-resistance and breakdown voltage in lateral high voltage MOSFET's. See II-Yong Park and C. A. T. Salama, “CMOS Compatible Super Junction LDMOST with N-buffer,” Proc. Of 17th ISPSD conference, May 23-26, 2005, Santa Barbara, Calif.
The foregoing article and other ISPSD proceedings in the period 2000-2005 reference many other lateral super junction or charge control techniques for junction and SOI type lateral MOSFET's and IGBT's.
Nonetheless, all of these known charge control methods encounter problems with the dimensional control of PN junctions, especially junctions of the P-type dopant boron, during the subsequent process steps.
Thus it would be desirable to provide a field-effect device which has the current-blocking advantages of spaced regions of opposite conductivity in the drift region but in which the charge within the regions of opposite conductivity is better controlled. In particular, it would be desirable to limit the tendency of the charge to diffuse in at least two dimensions.
A field-effect transistor according to this invention includes a source region of the first conductivity and a drain region of the first conductivity formed at the surface of a semiconductor die. The die may include a substrate and a layer (e.g., an epitaxial layer) grown on top of the substrate. A gate is formed over the surface of the die, separated from the surface by a gate dielectric layer, typically an oxide layer. The gate overlies a channel region of the transistor, which is of a second conductivity type opposite to the first conductivity type. Adjoining the drain region is a drift region of the first conductivity type, which is positioned generally between the drain region and the channel region. Located at least partially within the drift region are a plurality of JFET regions of the second conductivity type, which are separated by portions of the drift region. In accordance with this invention, the JFET regions are bounded laterally and/or vertically by a dielectric layer, typically an oxide layer, which prevents the second conductivity type dopant of the JFET regions from diffusing into the drift region.
In one group of embodiments, the die includes a substrate of the second conductivity type and each of the JFET regions extends from the surface of the die to the substrate. The JFET regions are separated laterally by portions of the drift region, and the lateral sides of the JFET regions are bounded by dielectric layers which prevent the second conductivity type dopant in each of the JFET regions from diffusing laterally into the drift region. The JFET regions may be arrayed radially around the drain region, linearly between the channel region and the drain region, or in some other geometric configuration. The vertical oxide walls confine the charge within the JFET regions and thus help to utilize the area of the chip more efficiently.
In another group of embodiments, the JFET regions are arranged as a vertical stack of buried layers within the drift region, the JFET regions being separated from each other by portions of the drift region. A dielectric layer is located at the upper boundary (ceiling) and lower boundary (floor) of each of the JFET regions and prevents the second conductivity dopant in the JFET regions from diffusing upwards or downwards into the drift region.
The invention also comprising methods of fabricating a field-effect transistor having JFET regions bounded laterally and/or vertically by a dielectric layer as described above.
The use of JFET regions according to this invention provides for a very efficient use of the lateral area of the chip and allows the doping concentration of the drift region to be higher than it would be if the JFET regions were not present.
Referring first to
Referring again to
Each of JFET regions 416 is laterally bounded by an oxide layer 420, which in accordance with the invention prevents the P-type dopant within JFET regions 416 from diffusing outwards into N-drift region 404. In this embodiment, there is no oxide layer at the floor of JFET regions 416.
Next, as shown in
The structure subjected to a second RIE process. Again, this is a highly directional process that when directed vertically downward removes the portion of oxide layer 505 from the floor of trench 503, while leaving the portion of oxide layer 505 on the walls of trench 503. This remaining portion of oxide layer 505 becomes the oxide layer 420 that lines the walls of JFET regions 416. The result is shown in
As shown in
After JFET regions 416 have been formed, as described in
The MOSFET can be formed in a wide variety of geometric shapes. It will be apparent from
In the embodiments described thus far, each JFET region extends downward from the surface of the epitaxial layer to the interface between the epitaxial layer and the substrate. The JFET regions are laterally spaced from each other and are separated by intervening portions of the drift region in an “interdigitated” arrangement.
The broad principles of this invention are not limited to MOSFETs but may be used in a wide variety of semiconductor devices.
In another group of embodiments, the JFET regions are vertically arranged in a stack, with an oxide layer on the ceiling and floor of each JFET region.
The process begins with P-substrate 400, as shown in
As shown in
Next, as shown in
An oxide layer and a nitride layer similar to oxide layer 700 and nitride layer 702 are formed on the top surface of N-wafer 708 and are patterned to have an opening similar to opening 704, shown in
As shown in
A thin P-wafer 718 is introduced and bonded to the top surface of N-wafer 708. P-wafer 718 could have a doping concentration of 2×1016 cm−3 and a thickness of 2 μm, for example. An oxide layer and a nitride layer similar to oxide layer 700 and nitride layer 702 are formed on the top surface of P-wafer 718 and are patterned to have an opening similar to opening 704, shown in
A photoresist layer 722 is deposited on the top surface of P-wafer 718. Photoresist layer 722 is patterned to form openings 724, as shown in
From a comparison of
As shown in
As shown in
A thin P-wafer 736 is bonded to the top surface of N-wafer 726 and then processed in the same manner as P-wafer 718 to form JFET region 602. A thin N-wafer 738 is bonded to the top surface of P-wafer 736 and processed in the same manner as N-wafers 708 and 726. The resulting structure is shown in
Preferably, the charge in the lower half of each of the JFET regions should balance the charge in the upper half of the underlying portion of the N-type drift region (except in the case of the lowest JFET, where the charge in the lower half of that JFET region should balance the charge in the entire underlying portion of the N-type drift region); and the charge in the upper half of each of the JFET regions should balance the charge in the lower half of the overlying portion of the N-type drift region (except in the case of the uppermost JFET region, where the charge in the upper half of that JFET region should balance the charge in the entire overlying portion of the N-type drift region).
A drift region according to this invention can be used in a wide variety of semiconductor devices. Two examples are illustrated in
Although the present invention is illustrated in connection with specific embodiments for instructional purposes, the present invention is not limited thereto. Various adaptations and modifications may be made without departing from the scope of the invention. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.
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