A method of operating a multi-level cell is described, wherein the cell includes a substrate of a first conductivity type, a control gate, a charge-storing layer and two S/D regions of a second conductivity type. The method includes an erasing step that injects charges of a first type into the charge-storing layer and a programming step that includes applying a first voltage to the substrate, a second voltage to both S/D regions and a third voltage to the control gate. The difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes, and the third voltage causes charges of a second type to enter the charge-storing layer. The third voltage can have 2n−1 different values, for programming the cell to a predetermined state among 2n−1 storage states.
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1. A method of operating a multi-level cell (MLC) that comprises a substrate of a first conductivity type, a control gate, a charge-storing layer between the substrate and the control gate and two source/drain (S/D) regions of a second conductivity type, comprising:
an erasing step that injects charges of a first type into the charge-storing layer; and
a programming step that utilizes a double-side bias band-to-band tunneling hot hole (DSB-BTBTHH) effect and comprises:
applying a first voltage to the substrate, a second voltage to both of the S/D regions and a third voltage to the control gate, wherein
a difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes, and the third voltage causes charges of a second type to enter the charge-storing layer and can have 2n−1 (n≧2) different values, for programming the cell to a predetermined state among 2n−1 storage states.
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applying the first voltage to the substrate, the second voltage to both of the S/D regions and a fourth voltage to the control gate, wherein the fourth voltage drives charges of the first type into the charge-storing layer.
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applying the first voltage to the substrate and both of the S/D regions and applying a fourth voltage to the control gate, wherein a difference between the first and the fourth voltages is sufficient to induce FN-tunneling and thereby inject charges of the first type into the charge-storing layer.
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1. Field of the Invention
The present invention relates to an operating method of a semiconductor device. More particularly, the present invention relates to an operating method of a multi-level cell (MLC) of a non-volatile memory, which utilizes a double-side bias band-to-band tunneling hot hole (DSB-BTBTHH) effect in programming.
2. Description of the Related Art
With the rapid growth of information flow in the world, the requirement for the storage capacity of electrically erasable programmable non-volatile memory devices, such as flash memory devices, continuously gets higher in the market.
The most direct way to increase the unit-area storage capacity of a non-volatile memory product is to reduce the lateral area of each memory cell, while this is limited by the lithographic resolution and some dimension-relating electrical properties, etc. Another way is to allow each memory cell to store more than one bit of data, which may be done by making a cell have one of 2n (n≧2) threshold voltages that correspond to 2n storage states. Such a memory cell is called a multi-level cell (MLC).
In conventional MLC operation, the erasing is done by ejecting electrons out of the charge-storing layer of the cell through Fowler-Nordheim (FN) tunneling, and the programming by injecting electrons into the same through FN tunneling. The amount of injected electrons is controlled by the programming time so that a cell has a threshold voltage (Vt) corresponding to the predetermined storage state thereof.
However, because the efficiency of injecting or ejecting electrons through FN tunneling is low, the erasing or programming is slow in the prior art. Moreover, since the erasing step ejects electrons out of the charge-storing layer, the threshold voltage of the cell is lower in the erased state causing more leakage. Further, the programming step that controls the threshold voltage in time mode cannot precisely control the amount of injected electrons, so that the Vt-distribution of each storage state is broad easily causing error in the reading.
In view of the foregoing, this invention provides a method of operating a multi-level cell, which utilizes a double-side bias band-to-band tunneling hot hole (DSB-BTBTHH) effect to solve the problems in the prior art.
The memory cell to which this invention is applicable includes a substrate of a first conductivity type, a control gate, a charge-storing layer between the substrate and the control gate, and two source/drain (S/D) regions of a second conductivity type. The method of operating a multi-level cell of this invention includes an erasing step that injects charges of a first type into the charge-storing layer and a programming step that applies a first voltage to the substrate, a second voltage to both S/D regions and a third voltage to the control gate, wherein the voltage application to both S/D regions is namely a double-side bias (DSB) application. The difference between the first and the second voltages is sufficient to cause band-to-band tunneling hot holes, and the third voltage causes charges of a second type to enter the charge-storing layer. The third voltage can have 2n−1 (n≧2) different values, for programming the cell to a predetermined state among 2n−1 storage states. The difference between the first and second voltages is within the range of 4V to 6V, for example.
In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, charges of the first type are electrons, charges of the second type are electric holes, the second voltage is higher than the first voltage, and the third voltage is lower than or equal to the first voltage. In such embodiments, for example, the first voltage is 0V, the second voltage is within the range of 4V to 6V, and the 2n−1 (n≧2) different values of the third voltage are within the range of −10V to 0V.
In the MLC operating method of this invention, the erasing step may utilize the DSB-BTBTHH effect or an FN-tunneling effect to inject charges of the first type into the charge-storing layer.
When the erasing step utilizes the DSB-BTBTHH effect, it may include applying the first voltage to the substrate, the second voltage to both S/D regions and a fourth voltage to the control gate, wherein the fourth voltage drives charges of the first type into the charge-storing layer. When the first conductivity type is P-type and the second conductivity type is N-type, charges of the first type are electrons, charges of the second type are electric holes, the second voltage is higher than the first voltage, and the fourth voltage is higher than the first voltage. For example, the first voltage is 0V, the second voltage is within the range of 4V to 6V, and the fourth voltage is within the range of 8V to 12V.
When the erasing step utilizes the FN-tunneling effect, it may include applying the first voltage to the substrate and both of the S/D regions and applying a fifth voltage to the control gate, wherein the difference between the first and the fifth voltages is sufficient to induce FN-tunneling and thereby inject charges of the first type into the charge-storing layer. When the first conductivity type is P-type and the second one is N-type, charges of the first type are electrons, charges of the second type are electric holes, and the fifth voltage is higher than the first voltage. For example, the first voltage is 0V, and the fifth voltage is within the range of 10V to 20V.
In addition, the charge-storing layer that may include a floating gate, a charge-trapping layer or a nano-crystal layer, and n is possibly equal to 2 so that the multi-level cell has totally 4 (=22) storage states. Moreover, a verify operation may be performed after the programming step to check whether the multi-level cell has been programmed to the predetermined storage or not.
Since the MLC operating method of this invention conducts programming with the DSB-BTBTHH effect that makes a charge-injection rate higher than that made by the FN-tunneling effect conventionally used to program a multi-level cell, it is more rapid in the programming. Moreover, because the amount of the electric holes injected with the DSB-BTBTHH effect can be precisely controlled by the voltage applied to the control gate as the programming time is fixed, the Vt-distribution of each storage state is narrower lowering the possibility of reading error.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
It is firstly noted that though this embodiment only describes a case where the first conductivity type is P-type, the second conductivity type is N-type, charges of the first type are electrons and charges of the second type are electric holes, one of ordinary skill in the art can understand, based on the following descriptions, that the method of this invention is also applicable to cases where the first conductivity type is N-type, the second conductivity type is P-type, charges of the first type are holes and charges of the second type are electrons.
Moreover, in a memory cell to which this invention can be applied, the charge-storing layer may include a floating gate, a charge-trapping layer or a nano-crystal layer. A floating gate usually includes doped poly-Si, a charge-trapping layer usually includes silicon nitride, and a nano-crystal layer usually includes many separate nano-crystals of a conductor material in a dielectric layer. Although only the cell including a charge-trapping layer is exemplified in this embodiment, one of ordinary skill in the art can understand, based on the following descriptions, that this invention is also applicable to a cell including a floating gate or a nano-crystal layer as a charge-storing layer.
Referring to
As mentioned above, the erasing step in the MLC operating method according to this embodiment of this invention injects electrons into the charge-storing layer, but not ejects electrons out of the same as in the prior art. Since a cell having electrons in its charge-storing layer has a higher threshold voltage, the leakage of the erased cells can be reduced in this embodiment of this invention.
Since the DSB-BTBTHH effect makes a charge-injection rate higher than that made by the FN-tunneling effect that is conventionally utilized to program a multi-level cell, the MLC operating method of this invention is more rapid in the programming.
It is particularly noted that when a multi-level cell is not subjected to the above programming step during the data-storing process of the non-volatile memory apparatus including the cell, the storage state of the cell is the one having the highest threshold voltage, which is abbreviated to the highest-Vt storage state hereinafter. Therefore, the cell has totally 2n storage states including the highest-Vt storage state. Since the threshold voltages of adjacent storage stares cannot be overly close to each other for preventing reading error, n is usually equal to 2 in consideration of the usual Vt-range for non-volatile memory. As n is equal to 2, the cell has totally four storage states, wherein the first to fourth storage states descending in the Vt-level correspond to the data values of 00, 01, 10 and 11, or to the data values of 11, 10, 01 and 00, respectively.
Moreover, a verify step may be conducted after the above programming step to check whether the cell has been programmed to the predetermined state or not. If the cell passes the verify step, subsequent operations are performed. If the cell fails in the verify step, it may be erased with one of the above two erasing steps and is programmed again as above.
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It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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