A semiconductor element structure includes a first mos having a first high-K material and a first metal for use in a first gate, a second mos having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.
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1. A semiconductor element structure, comprising:
a first mos having a first high-K material and a first metal for use in a first gate;
a second mos having a second high-K material and a second metal for use in a second gate; and
a bridge channel, disposed in a recess connecting said first gate and said second gate for electrically connecting said first gate and said second gate, wherein said bridge channel is embedded in at least one of said first metal and said second metal.
2. The semiconductor element structure of
3. The semiconductor element structure of
4. The semiconductor element structure of
5. The semiconductor element structure of
6. The semiconductor element structure of
8. The semiconductor element structure of
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1. Field of the Invention
The present invention relates to a semiconductor element structure and a method for forming the semiconductor element structure. More particularly, the present invention relates to a semiconductor element structure with an inter-gate bridge channel and a method for forming the semiconductor element structure.
2. Description of the Prior Art
The gate electrodes in a PMOS and NMOS of a static random access memory (SRAM) based on the complementary metal-oxide semiconductor (CMOS) structure are usually connected to each other. If such devices are manufactured by a high-K/metal gate replacement procedure, however, the poly-Si and the gate dielectric layer in the gates of the PMOS and the NMOS is removed in different steps to be replaced by the corresponding conductive metal gate and gate dielectric layer. Just after the deposition of the high-K materials and the metal gate materials, the electric connection between the metal gates in the PMOS and the NMOS is lost due to the isolation formed by the high-K materials. Therefore, a technical strategy is needed to restore the electric connection between the metal gates in the PMOS and the NMOS.
An electrical connection plan is provided in U.S. Pat. No. 6,849,511. A dishing phenomenon is available on the surface of the material with higher removal rate by taking advantage of different removal rates between different materials by CMP and this area is taken as the space for the electrical connection material for the metal gates in the PMOS 101 and the NMOS 102, as shown in
Another electrical connection plan is provided in U.S. Pat. No. 6,653,698. Space for the electrical connection is obtained by entirely back-etching the high-K materials and the metal gates in the PMOS 201 and the NMOS 202, as shown in
Still another electrical connection plan is provided in U.S. Pat. No. 7,045,428. The high-K materials are directly converted into metals to realize the electrical connection between the metal gates.
In spite of the provided technical plans, a stable and reliable method is still needed to construct a sufficient electrical connection of the metal gates in the PMOS and the NMOS.
The present invention therefore provides a novel semiconductor element structure and a stable and reliable method to construct a sufficient electrical connection of the metal gates in the PMOS and the NMOS.
The semiconductor element structure of the present invention includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.
The method for forming the semiconductor element structure of the present invention first provides a substrate including a first MOS and a second MOS, the gate electrode of the first MOS being connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate, then partially removes the first gate and the second gate to form a connecting recess, and afterwards fills the connecting recess with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.
Because the bridge channel in the novel semiconductor element structure of the present invention is located in the recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate and is embedded in at least one of the first gate and the second gate, such a bridge channel will not change the height of the elements, and secures a sufficient electrical connection of each and every gate.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The present invention provides a novel inter-gate connecting structure for use in the invertors and SRAMs. The bridge channel therein not only does not change the height of the elements but also secures a sufficient electrical connection of each and every gate.
Please refer to
The first MOS 310 is disposed in the substrate 301 and includes a first high-K material 312 and a first metal 313 for a first gate 311. Similarly, the second MOS 320 is also disposed in the substrate 301 and includes a second high-K material 322 and a second metal 323 for a second gate 321. Preferably, the first gate 311 and the second gate 321 are connected to each other, so that the first high-K material 312 and the second high-K material 322 are sandwiched between the first metal 313 and the second metal 323.
The substrate 301 may be a semiconductor substrate, such as Si. The first high-K material 312 and the second high-K material 322 may be any suitable material with a high dielectric constant, such as HfSixOx, HfSiON, HfOx, LaOx, LaAlxOy, ZrOx, ZrSixoy, Hf ZrxO4, such as a material with a dielectric constant higher than 10. Similarly, the first metal 313 and the second metal 323 may be any single metal or composite metal, such as Al or W, that is suitable for the gate of an MOS, as shown in
The bridge channel 330 is disposed in a recess 331 for connecting the first gate 311 and the second gate 321 so that the bridge channel 330 may electrically connect the first gate 311 and the second gate 321. The minimum region of the connecting recess 331 is limited to the space of the first high-K material 312 and the second high-K material 322 of the first gate 311 and the second gate 321, or the connecting recess 331 may further partially occupies the first gate 311 and the second gate 321, for example, part of the first high-K material 312 and part of the second high-K material 322, and may further partially occupy at least one of the first metal 313 and the second metal 323. Accordingly, the bridge channel 330 in the recess 331 for connecting the first gate 311 and the second gate 321 is embedded in at least one of the first gate 313 and the second gate 323.
The bridge channel 330 may be formed of a metal to construct the electrical connection between the first gate 311 and the second gate 321, i.e. the first MOS 310 and the second MOS 320. The bridge channel 330 may be formed of any suitable metal for electrical connection, such as W, Al, TiAl, Co WP.
Because the bridge channel 330 is located in the recess 331 connecting the first gate 311 and the second gate 321, the size of the recess 331 is not fixed. Therefore, the recess 331 is unlikely to be too shallow to form a sufficient electrical connection. In addition, no back-etching is required to be performed on the first gate 311 and the second gate 321, so that uneven uniformity of the material for electrical connection is avoided. The present invention provides a stable and reliable solution to construct a sufficient electrical connection of the metal gates in the PMOS and the NMOS.
The present invention still provides a novel method for forming an inter-gate electrical connection structure, for example for forming an SRAM structure.
The first MOS 410 may include any conventional elements, such as a source (not shown), a drain (not shown) or a first gate 411. The first MOS 410 includes a first high-K material 41 2 and a first metal 41 3 for use in a first gate 411. Similarly, the second MOS 420 may also include any conventional elements, such as a source (not shown), a drain (not shown) or a second gate 421. The second MOS 420 also includes a second high-K material 422 and a second metal 423 for use in a second gate 421. The first gate 411 and the second gate 421 are adjacent to each other, so that the first high-K material 412 and the second high-K material 422 are sandwiched between the first metal 413 and the second metal 423.
The substrate 401 may be a semiconductor substrate, such as Si or SiGe or GaAs. The first high-K material 41 2 and the second high-K material 422 may be any suitable material with a high dielectric constant, such as HfSixOx, HfSiON, HfOx, LaOx, LaAlxOy, ZrOx, ZrSixoy, Hf ZrxO4, or a material with a dielectric constant higher than 10. Similarly, the first metal 413 and the second metal 423 may be any single metal or composite metal, such as Al or W, that is suitable for the gate of an MOS, as shown in
Then, as shown in
There are many options for the formation and location of the connecting recess 440. For example, a wet etching procedure, which can be selective or non-selective, may be used to form the connecting recess 440. The selective wet etching procedure may only selectively remove the first high-K material 41 2 and the second high-K material 422. On the other hand, the non-selective wet etching procedure may partially remove the first high-K material 412, the second high-K material 422, the first metal 413 and the second metal 423. The wet etching procedure may include multiple stages to partially remove the first high-K material 41 2, the second high-K material 422, the first metal 413 and the second metal 423.
On the other hand, a dry etching procedure, which can be selective or non-selective, may be used to form the connecting recess 440. The selective dry etching procedure may only selectively remove the first high-K material 41 2 and the second high-K material 422. On the other hand, the non-selective dry etching procedure may partially remove the first high-K material 41 2, the second high-K material 422, the first metal 413 and the second metal 423. For example, if the metal to be etched is W, the etching recipe may be Cl2+SF6. If the metal to be etched is Al, the etching recipe may be Cl2+BCl3.
Alternatively, an energy burning procedure, such as a laser, may be employed in the absence of a mask to form the connecting recess 440. The suitable size of the recess 440 is not fixed.
Afterwards, as shown in
Because the size of the bridge channel 430 is optional, the bridge channel 430 is unlikely to be too shallow to form a sufficient electrical connection. In addition, no back-etching is required to be performed on the first gate 411 and the second gate 421, so that uneven uniformity of the material for electrical connection is avoided. The present invention provides a stable and reliable solution to construct a sufficient electrical connection of the metal gates in the PMOS and the NMOS.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Lin, Chien-Ting, Chou, Cheng-Hsien, Yu, Chih-Hao, Cheng, Li-Wei, Hsu, Che-Hua, Chiang, Tian-Fu, Lai, Chien-Ming, Chen, Yi-Wen, Ma, Guang-Hwa
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