High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an ebg (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the ebg layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the ebg layer from each other is disposed between the power layer for analog operation and the ebg layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.
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1. A semiconductor device comprising:
a digital semiconductor element connected with a power connection terminal and a ground connection terminal;
an analog semiconductor element connected with a power connection terminal and a ground connection terminal;
a wiring board mounted with the digital semiconductor element and the analog semiconductor element; and
a plurality of external terminals connected to the wiring board,
wherein the wiring board includes an ebg (Electromagnetic Band Gap) layer formed by arranging a plurality of unit wiring patterns each of which is composed of two wiring patterns having different impedances over a flat plane, a ground layer, a power layer for a digital element connected to one end of the ebg layer, and a power layer for an analog element connected to the other end of the ebg layer,
wherein the ground connection terminal for the digital semiconductor element and the ground connection terminal for the analog semiconductor element are connected to the ground layer of the wiring board,
wherein the power connection terminal for the digital semiconductor element is connected to the power layer for the digital element of the wiring board, and
wherein the power connection terminal for the analog semiconductor element is connected to the power layer for analog element of the wiring board.
6. A semiconductor device comprising:
a digital semiconductor element connected with a power connection terminal and a ground connection terminal;
an analog semiconductor element connected with a power connection terminal and a ground connection terminal;
a wiring board mounted with the digital semiconductor element and the analog semiconductor element; and
a plurality of external terminals connected to the wiring board,
wherein the wiring board includes an ebg (Electromagnetic Band Gap) layer formed by arranging a plurality of unit wiring patterns each of which is composed of two wiring patterns having different area regularly over a flat plane, a ground layer, a power layer for a digital element connected to one end of the ebg layer, and a power layer for a analog element connected to the other end of the ebg layer,
wherein the ground connection terminal for the digital semiconductor element and the ground connection terminal for the analog semiconductor element are connected to the ground layer of the wiring board,
wherein the power connection terminal for the digital semiconductor element is connected to the power layer for the digital element of the wiring board, and
wherein the power connection terminal for the analog semiconductor element is connected to the power layer for the analog element of the wiring board.
2. The semiconductor device according to
wherein the ground layer of the wiring board is disposed in a layer between the power layer for the analog element and the ebg layer, and the analog semiconductor element is disposed nearer to the power layer for the analog element than the ebg layer.
3. The semiconductor device according to
wherein the power layer for the analog element of the wiring board is connected to one of the external terminals via the ebg layer and the power layer for the digital element is connected to another one of the external terminals directly without interposition of the ebg layer.
4. The semiconductor device according to
wherein the power layer for the analog element and the power layer for the digital element of the wiring board are disposed in the same wiring layer, an interval of 1 mm or more is provided between the power layer for the analog element and the power layer for the digital element, and the power layer for the analog element and the ebg layer are connected via viahole connection and lead wire connection.
5. The semiconductor device according to
wherein the analog semiconductor element is connected to the wiring board in a flip-chip manner using the power connection terminal of the analog semiconductor element and the ground connection terminal of the analog semiconductor element, the digital semiconductor element is stacked over the analog semiconductor element, and the power connection terminal and the ground connection terminal of the digital semiconductor element are connected to the power layer for the digital element and the ground layer of the wiring board via bonding wires respectively.
7. The semiconductor device according to
wherein the ground layer of the wiring board is disposed in a layer between the power layer for the analog element and the ebg layer, and the analog semiconductor element is disposed nearer to the power layer for the analog element than the ebg layer.
8. The semiconductor device according to
wherein the wiring board further includes a signal layer for the analog element connecting a signal connection terminal for the analog semiconductor element and an external terminal for an analog signal and the signal layer for the analog element is disposed between the analog semiconductor element and the power layer for the analog element.
9. The semiconductor device according to
wherein the power layer for the analog element and the power layer for the digital element of the wiring board are disposed in the same wiring layer and an interval of 1 mm or more is provided between the power layer for the analog element and the power layer for the digital element.
10. The semiconductor device according to
wherein the power layer for the analog element and the ebg layer of the wiring board are connected via viahole connection and lead wire connection.
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The present application claims priority from Japanese Patent Application No. JP 2006-155136 filed on Jun. 2, 2006, the content of which is hereby incorporated by reference into this application.
Present invention relates to a semiconductor device, and in particular to an effective technique in application to a semiconductor device having an analog semiconductor element and a digital semiconductor element.
In a portable electronic device such as GPS (Global Positioning System) or wireless LAN (Local Area Network), it is required to combine a wireless technique and a high-density mounting technique. And therefore, a demand for mounting an analog semiconductor element and a digital semiconductor element so as to be close to each other or on one package is increasing. A technique for mounting an analog semiconductor element and a digital semiconductor element on the same board to integrate them in one module and a technique adopting an EBG (Electromagnetic Band Gap) layer as a ground plane of the board are described in “M.Swaminathan et al., “PowerDistribution Networks for System-on-Package: Status and Challenges”, IEEE Transactions on Advanced Packaging, Vol. 27, No. 2, May 2004” (Non-Patent Document 1).
And, there is a technique of reducing influence of mismatching of characteristic impedance caused by electromagnetic coupling generated between a signal through conductor and a grounding conductor layer having an opening arranged so as to surround the signal through conductor (for example, see Japanese Patent Application Laid-Open Publication No. 2004-259959 (Patent Document 1)).
Furthermore, there is a technique of relaxing mismatching of characteristic impedance at a connection portion between a signal wiring conductor and a signal through conductor and preventing noise interference between the signal wiring conductors (for example, see Japanese Patent Application Laid-Open Publication No. 2004-241426 (Patent Document 2)).
Since a digital semiconductor element handles “0” and “1”, power source noise generated therefrom expands to a wide band and a frequency thereof extends to an RF (radio frequency) band with speed-up on every generations. However, a noise band required by an analog RF signal is considerably low (for example, −120 dBm in GPS). It is a problem that, because of transmission/reception of the analog RF signal and interference of noise generated from the digital semiconductor element, it is difficult for the analog semiconductor element and the digital semiconductor element to share a power source and mount the analog semiconductor element and the digital semiconductor element so as to be close to each other.
That is, since interference of power source noise from the digital semiconductor element to the analog semiconductor element exists, it is difficult to constitute a power source for the digital semiconductor element and for the analog semiconductor element as a common power source and realize proximity mounting for high-density mounting.
Even if the EBG wiring is adopted for reduction of noise coupling between the analog semiconductor element and the digital semiconductor element, effect of noise cut-off depends on an arrangement of both the elements, a structure around the EGB wiring and the like. Especially, in order to realize high-density mounting as a whole module structure and reduce the noise coupling to an acceptable level, the arrangement of the analog semiconductor element and the digital semiconductor element and the structure around the EGB wiring must be devised.
An object of the present invention is to provide a technique for achieving a common power source for the digital semiconductor element and the analog semiconductor element in the semiconductor device and realizing high-density mounting.
Another object of the present invention is to provide a technique capable of securing quality of signals in the semiconductor device and achieving stabilization of a power source.
The above-described and other objects and novel characteristics of the present invention will become apparent from the description of the specification and the attached drawings.
An outline of typical elements of the invention disclosed in this application is described briefly as follows.
That is, a semiconductor device according to the present invention includes a digital semiconductor element, an analog semiconductor element, a wiring board mounted with the digital semiconductor element and the analog semiconductor element, and an external terminal connected to the wiring board. The wiring board includes an EBG layer in which two wiring patterns having different impedances are defined as a unit wiring pattern and a plurality of the unit wiring patterns is disposed on a flat plane, a ground layer, a power layer for the digital element connected to one end of the EBG layer, and a power layer for the analog element connected to the other end of the EBG layer. Furthermore, a ground connection terminal for the digital semiconductor element and a ground connection terminal for the analog semiconductor element are connected to the ground layer of the wiring board, a power connection terminal for the digital semiconductor element is connected to the power layer for the digital element of the wiring board, and a power connection terminal for the analog semiconductor element is connected to the power layer for the analog element of the wiring board.
And, the semiconductor device according to the present invention includes the digital semiconductor element, the analog semiconductor element, the wiring board mounted with the digital semiconductor element and the analog semiconductor element, and the external terminal connected to the wiring board. The wiring board includes the EBG layer in which a plurality of unit wiring patterns each of which are composed of a combination of two wiring patterns having different areas are arranged regularly on the flat plane, the ground layer, the power layer for the digital element connected to one end of the EBG layer, and the power layer for the analog element connected to the other end of the EBG layer. Furthermore, the ground connection terminal for the digital semiconductor element and the ground connection terminal for the analog semiconductor element are connected to the ground layer of the wiring board, the power connection terminal for the digital semiconductor element is connected to the power layer for the digital element of the wiring board, and the power connection terminal for the analog semiconductor element is connected to the power layer for the analog element of the wiring board.
And, the semiconductor device according to the present invention includes the digital semiconductor element, the analog semiconductor element, the wiring board mounted with the digital semiconductor element and the analog semiconductor element, and the external terminal connected to the wiring board. The wiring board includes two EBG layers in which two wiring patterns having different impedances are defined as a unit wiring pattern and a plurality of the unit wiring patterns is disposed on a flat plane. One EBG layer is for ground and the other is for power source. Furthermore, one end of the EBG layer for ground (the first EBG layer) is connected to a ground layer for the digital element and the other end is connected to a ground layer for the analog element. One end of the EBG layer for power (the second EBG layer) is connected to the power layer for the digital element and the other end is connected to the power layer for the analog element. And, the ground connection terminal for the digital semiconductor element is connected to the ground layer for the digital element of the wiring board, the ground connection terminal for the analog semiconductor element is connected to the ground layer for the analog element of the wiring board, the power connection terminal for the digital semiconductor element is connected to the power layer for the digital element of the wiring board, and the power connection terminal for the analog semiconductor element is connected to the power layer for the analog element of the wiring board.
Effect obtained by the typical elements of the invention disclosed in this application is described briefly as follows.
Since the power layer for the analog element of a printed board is connected to one end of the EBG layer, the power layer for a digital element is connected to the other end, the ground connecting terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for the analog element and the EBG layer from each other is arranged therebetween, high-density mounting can be achieved while reducing interference of power source noise to the analog semiconductor element.
In the following embodiments, in principle, the same or similar portions are not repeatedly explained unless particularly necessary.
And, in the following embodiments, if necessary for convenience, the invention is described with a plurality of sections or embodiments in a divided manner. However, unless explicitly mentioned, these sections or embodiments are not unrelated to one another. One is a modification example, a detail, a supplement, or the like of all or part of the others.
Furthermore, in the following embodiments, when the number of elements and others (including the numbers, numerical values, amounts, ranges, and the like) are referred to, such number is not restricted to a specific number, and can be above or below the specific number, unless explicitly mentioned or the number is apparently restricted to the specific number according to the principle.
The embodiments of the present invention are described in detail below based on the drawings. Note that, in all drawings for explaining the embodiments, members having the same function are provided with the same reference symbols, and repeated explanation of such members is omitted.
The semiconductor device according to the first embodiment is, as shown in
The analog chip 101 mounted over a main face of the package board 51 is, for example, of an RF type and it is connected with an antenna 94 to perform transmission/reception of an electrical wave as shown in
As shown in
And, over a back face of the package board 51 of the SIP 10, as shown in
In the SIP 10 according to the first embodiment, as shown in
That is, the power layer for digital 54D and the power layer for analog 54A are electrically connected via the EBG layer 52. At this time, the power layer for digital 54D is connected to the EBG layer 52 at one end of the EBG layer 52 via an EBG connection viahole (viahole connection) 61, on the other hand, the power layer for analog 54A is similarly connected to the EBG layer 52 at the other end of the EBG layer 52 at the opposite side via the EBG connection viahole 61. That is, the power layer for digital 54D and the power layer for analog 54A are respectively connected in a DC manner by the viahole connection (the EBG connection viahole 61) disposed at both ends of the EBG layer 52, but they are blocked from each other at a specific high frequency band.
And, as shown in
Next,
Furthermore, an interval with a length of T or more is formed between the power layer for digital 54D and the power layer for analog 54A, so that interference of power source noise can be suppressed. T is, for example, 1 mm and if T is less than 1 mm, it is difficult to suppress interference of power source noise caused by electric coupling of both sides.
And, a plurality of EBG connection viaholes 61 is connected to an outer end portion of the power layer for digital 54D, and a plurality of digital power source connection viaholes (viahole connections) 64 is connected to an inner end portion thereof and the vicinity of a central portion thereof. On the other hand, a plurality of EBG connection viaholes 61 is connected to an outer end portion of the power layer for analog 54A.
Next,
Next,
Thus, the power layer for digital 54D and the EBG layer 52 are connected via the EBG connection viaholes 61 at one end of the EBG layer 52, on the other hand, the power layer for analog 54A and the EBG layer 52 are connected via the EBG connection viaholes 61 at the other end of the EBG layer 52. At this time, the EBG connection viaholes 61 connect upper and lower layers of the ground layer 53 through a region of the anti-pads 62 of the ground layer 53.
Furthermore, the power layer for digital 54D and the solder balls 71 corresponding thereto and serving as external terminals shown in
Note that, as shown by a “P” portion in
Ground connection terminals 22D of the digital chip 102 and ground connection terminals 22A of the analog chip 101 are connected to the ground layer 53 that is the same ground layer (G), respectively.
That is, the connection terminals of the digital chip 102 and the ground connection terminals of the analog chip 101 are connected to the common ground layer 53.
Furthermore, power connection terminals 21D of the digital chip 102 are connected to the power layer for digital 54D, on the other hand, power connection terminals 21A of the analog chip 101 are connected to the power layer for analog 54A.
Next, a structure and a characteristic of the EBG layer 52 will be explained.
The EBG layer 52 is, as shown in
Next, a mechanism of occurring the cut-off frequency (band gap) 60 will be explained. The reason why the cutting-off of power at the EBG layer 52 occurs is as follows: Gaps (slits) 52d are formed in the power layer in the EBG pattern, as shown in
For example, in the EBG pattern of the EBG layer 52 shown in
In a modification example shown in
And, in the EBG layer 52 of a modification example shown in
Next, in the SIP 10, as shown in
According to the SIP 10 of the first embodiment, in the semiconductor device in which the analog chip 101 of analog system and the digital chip 102 of digital system are mounded over the package board 51 in a mixing manner, high density mounting can be achieved with reducing interference of power source. That is, in the SIP 10, the power layer for analog 54A is connected to the one end of the EBG layer 52 of the package board 51, the power layer for digital 54D is connected to the other end thereof, and grounding connection terminals for respective element are connected to the ground layer 53 in common. Furthermore, the ground layer 53 separating the power layer for analog 54A and the EBG layer 52 from each other is provided between the power layer for analog 54A and the EBG layer 52, and the power layer for analog 54A is arranged at a position far from the EBG layer 52.
Accordingly, since the ground layer 53 is provided between the power layer for analog 54A and the EBG layer 52 and the power layer for analog 54A is arranged at a position far from the EBG layer 52, electric coupling between the EBG layer and the power layer for analog 54A is suppressed so that leakage of noise can be prevented. Furthermore, since the EBG layer 52 can be used with a maximum length approximately equal to that of the package board 51, the noise cut-off characteristic can be further improved.
As a result, in the SIP (semiconductor device) 10, high density mounting can be realized with reducing interference of power source noise to the analog chip 101.
Furthermore, since the interference of power source to the analog chip 101 can be reduced, stabilization of power source can be achieved with securing quality of signals in the SIP 10.
Since the present embodiment can be realized by only changing wiring pattern including the EBG layer 52 in the package board 51, reduction of interference of power source and high-density mounting can be realized at low cost without requiring excess parts.
Note that, as described above, in the SIP 10 according to the present embodiment, the maximal effect is obtained by interposition of the EGB layer having a length approximating that of the package board. On the other hand, since only interposition of an EBG pattern with a length sufficient to obtain a required noise cut-off effect is required, the effect of the present invention can be obtained even in a structure in which only a partial region of the package board is served as the EBG layer.
In a SIP (semiconductor device) 10 according to the second embodiment, the power layer for digital 54D is arranged on a side near a back face of the package board 51. That is, the power layer for digital 54D is disposed between the EBG layer 52 and the solder balls 71. Thereby, in a layer including a wiring layer of the power layer for digital 54D, wires for digital signal can be formed in a region corresponding to a portion just below the power layer for analog 54A, so that a wire use rate can be improved.
Note that, since the power layer for digital 54D is arranged on a side near the back face of the package board 51, the power layer for digital 54D can be connected to the solder balls 71 with a shortest route by shortening the digital power source connection viaholes 64. Thereby, connection to a printed board 80 (see
And, in a layer including the wiring layer of the power layer for analog 54A, wires for analog signals can be formed in a region corresponding to a portion just above the power layer for digital 54D and a wire use rate can be improved like the above.
Note that, since the power layer for digital 54D is connected to the solder balls 71 with low impedance, the cut-off effect of the EBG layer is not affected. Accordingly, the SIP 10 according to the second embodiment can also obtain the effect similar to that in the SIP 10 according to the first embodiment.
By disposing the signal area for analog 55A adjacent to the power layer for analog 54A or the ground layer 53 in this manner, a return current of an analog signal can be caused to flow in the power layer for analog 54A or the ground layer 53. That is, if the signal area for analog 55A is positioned adjacent to the EBG layer 52, a return current of an analog signal flows in the EBG layer, so that a signal can not be propagated at a specific frequency. In order to avoid such an event, the signal area for analog 55A is positioned adjacent to the power layer for analog 54A or the ground layer 53 without positioning adjacent to the EBG layer 52.
Similarly, A signal area for digital (a signal area for a digital element) 55D is disposed between the digital chip 102 and the power layer for digital 54D along the power layer for digital 54D and connects signal connection terminals for digital 23D that are signal connection terminals for the digital chip 102 and the solder balls 71 for digital signal. Like the case of the analog signal, a return current of a digital signal can be caused to flow in the power layer for digital 54D or the ground layer 53, not in the EBG layer.
Note that, a modification of the SIP 10 shown in
The semiconductor device according to the fourth embodiment has a structure in which the EBG layer 52 is modified.
That is, in the power layer for analog 54A with reduced area, by forming narrow leading wires 56 and connecting the EBG connection viaholes 61 to the leading wires 56, the power layer for analog 54A and the EBG layer 52 are securely connected to each other via the leading wires 56 and the EBG connection viaholes 61. Note that, the leading wire 56 is, for example, a leading wire having a width approximately equal to that of the second wiring pattern 52b having small area of the unit cell 52c of the EBG layer 52.
On the other hand, since the area of the power layer for digital 54D is larger than that in the first embodiment, more digital power connection viaholes 64 are connected to the power layer for digital 54D, and the power connection viaholes 64 are directly connected to solder balls 71 that are external terminals shown in
As mentioned above, since the power layer for digital 54D and the solder balls 71 are connected through more digital power connection viaholes 64 on digital side, noise generated from the digital chip 102 can be reduced.
Thereby, power source noise can be cut off by the EBG layer 52 even in the digital chip 102 with large power consumption and high clock frequency.
As a result, a power supplying impedance of a digital circuit in the digital chip 102 is reduced so that the quality of signals in the SIP (semiconductor device) 10 can be further improved.
Note that, as shown in
The semiconductor device according to the fifth embodiment shown in
As mentioned above, by forming the EBG layer for ground 57 on the ground layer 53, the EBG layer for ground 57 is paired with the EBG layer for power source 58 of the EBG layer so that a noise cut-off effect can be further increased.
In the sixth embodiment, connection of wires at mounting of an SIP 10 to the printed board 80 is explained. The ground layer 53 of the SIP 10 is connected to a ground layer 81 of the printed board 80, and the power layer for digital 54D is connected to a power layer 82 of the printed board 80. Note that, the power layer for analog 54A is not directly connected to solder balls 71 but connected via the EBG layer 52 certainly.
In a structure in which the power layer for analog 54A is connected to the solder balls 71 without interposition of the EBG layer 52, power source noise induced between the power layer for digital 54D and the ground layer 53 is propagated between the power layer 82 and the ground layer 81 of the printed board 80 and propagated from the power layer 82 to the power layer for analog 54A. That is, noise reduction effect obtained by the EBG layer 52 in the SIP 10 is reduced. In order to avoid such an event, the power layer for analog 54A is connected to the solder balls 71 via the EBG layer 52 certainly.
Note that, since an onboard decoupling capacitance 105 is mounted on the printed board 80, noise in the printed board 80 is reduced by the onboard decoupling capacitance 105.
In the SIP 10 including the EBG pattern incorporated into the digital camera 90, image information (data) taken by an imaging device 91 through a lens 90 is processed at the digital chip 102 that is a digital processing unit in the SIP 10 and is displayed on a display unit 93. On the other hand, analog processing for communication with a printer, a personal computer, or a web server in internet via an antenna 94 is processed at the analog chip 101 that is an RF unit. When both the processings are performed, power source noise mainly generated from the digital chip 102 is cut off by a noise cut-off means 95. In the first to seventh embodiments, the noise cut-off means 95 is the EBG layer 52 (including the EBG layer for ground 57 and the EBG layer for power source 58) formed over the package board 51.
In the package board 51, a power layer 54, an EBG layer 52, and a ground layer 53 are disposed from a layer near a face on which solder balls 71 are arranged in a two-dimensional array in this order. Furthermore, at a central region of a layer positioned above the ground layer 53, a power layer for analog 54A is provided. A ground connection terminal of the analog chip 101 is connected to the ground layer 53 via a viahole 65. A power connection terminal of the analog chip 101 is connected to the power layer for analog 54A via a viahole 66. The power layer 54 and solder balls 71 for external connection are connected in a viahole connection. The power layer 54 and the EBG layer 52 are connected through viaholes 61D. The EBG layer 52 and the power layer for analog 54A are connected through viaholes 61A positioned at an opposite side to the position of the viaholes 61D of the EBG layer 52. On the other hand, in a region of an end of a layer positioned at the same depth as that of the EBG layer 52 of the package board 51, a power layer for digital 54D is provided. The power layer for digital 54D is connected to the power area 54 through viaholes 64, and the power layer for digital 54D is connected to the power connection pad 72P through a viahole 67. The ground layer 53 is connected to a ground connection pad 73P through a viahole 69. Another power connection pad 72P′ is connected to a viahole 61D directly connected to the power layer 54. The power connection pads 72P, 72P′ and the ground connection pad 73P are connected to the digital chip 101 through bonding wires 72 and 73 respectively. Though not illustrated, other wires for signals and the like other than the power wires and ground wires described above exist. The analog chip and the digital chips are encapsulated by encapsulating resin (not shown) to be integrated with the package board 51.
In the semiconductor device according to the present embodiment, power supplying to the power layer for analog 54A is performed via the EBG layer 52. And, the ground layer 53 exists between the power layer for analog 54A and the EBG layer 52. The two configurations are similar to those of the first embodiment explained with reference to
Also in the present embodiment, the configuration in which the power layer for analog is arranged to be insulated by the ground layer and the EBG layer lies between the power supplying route to the digital chip and the power layer for analog is employed. And therefore, in terms of preventing the noise leakage between the digital chip and the analog chip via the power supplying route, an effect equivalent to that of the semiconductor device according to the eighth embodiment can be obtained.
As shown in
Solder balls are arranged on a bottom face of the digital chip 102 and are connected with pressure bonding to pads arranged on a top face of the package board. Some of solder balls of the solder balls positioned in a middle region are connection bumps for power feeding to a circuit inside the digital chip 102, and are connected to pads at distal ends of viaholes 67 connected to the power layer for digital 54D of the package board 51 or pads at distal ends of viaholes 69 connected to the ground layer 53.
On the other hand, a plurality of through viaholes are formed on a peripheral area of the digital chip 102 and electric connections between the analog chip 101 and the package board 51 are performed via these through viaholes. Since solder balls 311 are connected to distal ends of viaholes 66 extending from the power area for analog 54A1, through viaholes 301 is connected to a power source VCC. Similarly, since solder balls 313 are connected to distal ends of viaholes extending from the power area for analog 54A2, through viaholes 303 are also connected to the power source VCC. On the other hand, since solder balls 312 are connected to distal ends of viaholes 65 extending from the ground layer 54, through viaholes 302 are connected to a ground VSS. Since solder balls 314 are connected to other viaholes extending from the ground layer 54, through viaholes 304 are also connected to the ground VSS. Pads at the other ends of the through viaholes 301 to 304 and pads of the analog chip 101 are connected through solder balls 351 to 354 respectively, so that power supplying route to the analog chip 101 is formed. Note that, wires except for wires for power supplying are omitted also in
In the present embodiment, noise leakage between the digital chip and the analog chip can be prevented effectively like the tenth embodiment.
A board 51D including a solder ball array for external connection includes a ground layer 53D and a power source layer 54D. The power source layer 54D is connected to solder balls 713 through viaholes 64D, so that a power source voltage VCDD for a digital chip is applied externally. The ground layer 53D is connected to solder balls 714 so that a ground voltage VSSD is applied. The digital chip 102 is connected to the board 51D in a flip-chip manner to be connected to the power source layer 54D and the ground layer 53D, so as to receive power supply. A decoupling capacitor 104 for stabilizing power to be supplied is connected between the power source layer 54D and the ground layer 53D.
The board 51A includes an EBG layer 52, a ground layer 53A, and a power layer for analog 54A in this order from below. The respective layers are formed so as to extend approximately from one end to the other end of the board 51A. The board 51A is fixed to the board 51D by metal pins 321, 322, and 323. The metal pins also constitute a part of a route for supplying power to the analog chip 101. That is, one end portion of the EBG layer 52 of the board 51A is connected to the power layer for digital 54D of the board 51D via the viahole 64A, the metal pin 321, and the viahole 64D. Furthermore, the other end portion of the EBG layer 52 is connected to the power layer for analog 54A through the viahole 61. A ground layer 53A of the board 51A is connected to the ground layer 53D of the board 51D via viaholes 65A, metal pins 322, and viaholes 65D. The analog chip 101 is connected to the board 51A in a flip-chip manner to be connected to the power layer for analog 54A and the ground layer 53A, so as to receive power supply. A decoupling capacitor 103 for power source stabilization is connected between the power layer for analog 54A and the ground layer 53A.
In the power supplying route to the analog chip 101 described above, since the EBG layer 52 lies, cut-off of noise between the analog chip and the digital chip can be achieved like the other embodiments.
The analog integrated circuit is formed on a region 100A which is a part of a semiconductor chip 100. The analog integrated circuit is hereinafter called “analog section”. And, a digital integrated circuit is formed on other portion 100D adjacent to the analog section. The digital integrated circuit is hereinafter called “digital section 100D”. The analog section 100A and the digital section 100D are provided with individual power bumps and ground bumps, respectively, so that they are supplied with power individually.
The structure of the package board 51 is basically equal to that of the package board of the first embodiment explained with reference to
As described above, the EBG layer lies in the power supplying route reaching the analog section 10A, and therefore, even if the digital section 100A and the analog section 100B are connected in a DC manner, they are cut off at a specific high frequency range. Thereby, effect of cut-off of noise between the analog section and the digital section can be achieved.
Although the present invention made by the present inventors has been specifically described with reference to the embodiments, the present invention is not limited to the above embodiments, and may be variously modified without departing from the spirit thereof.
For example, in the first to seventh embodiments, a case of the semiconductor device of BGA type has been explained, but the external terminals of the semiconductor device are not limited to the solder balls 71 and they may be lands or the like. Accordingly, the semiconductor device may be an LGA (Land Grid Array) or the like.
The present invention can be suitably applied to an electronic device including an analog semiconductor element and a digital semiconductor element.
Suzuki, Eiichi, Uematsu, Yutaka, Osaka, Hideki
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
5336915, | Jan 09 1991 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having analog circuit and digital circuit formed on one chip |
5491358, | Jul 09 1993 | Kabushiki Kaisha Toshiba | Semiconductor device having an isolating portion between two circuit regions |
5994741, | Sep 25 1992 | Kabushiki Kaisha Toshiba | Semiconductor device having digital and analog circuits integrated on one chip |
JP2004241426, | |||
JP2004259959, |
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