Methods and apparatus for including mode information in a wireless transmission frame, which is useful for system acquisition. In particular, a first information bit is provided in a preamble of a transmission frame, where the bit is configured to indicate that a wireless communication system is operating according to either a time division duplex (TDD) mode or a frequency division duplex (FDD) mode. The addition of a single bit minimally affects the resources of the preamble. Additionally, another bit resource already present in the preamble for normally communicating whether FDD transmissions are full duplex or half-duplex transmissions, may be further allocated to indicate partitioning information concerning TDD mode transmissions when the first bit indicates TDD mode, thus affording additional information communicated in the frame without increasing preamble resources.
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1. A method implemented in an apparatus for use in a wireless communication system, the method comprising:
providing at least one first information bit configured to indicate that the wireless communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
providing at least one second information bit configured to provide TDD operational information when the at least one first information bit indicates that the system is operating according to the TDD mode and to provide FDD operational information when the at least one first information bit indicates that the system is operating according to the FDD mode; and
providing the at least one first information bit and the at least one second information bit in a portion of a transmission frame.
19. An apparatus operable in a wireless communication system, the apparatus comprising:
means for providing at least one first information bit configured to indicate that the wireless communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
means for providing at least one second information bit configured to provide TDD operational information when the at least one first information bit indicates that the system is operating according to the TDD mode and to provide FDD operational information when the at least one first information bit indicates that the system is operating according to the FDD mode; and
means for providing the at least one first information bit and the at least one second information bit in a portion of a transmission frame.
7. An apparatus operable in a wireless communication system, the apparatus comprising:
at least one processor configured to:
provide at least one first information bit configured to indicate that the wireless communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
provide at least one second information bit configured to provide TDD operational information when the at least one first information bit indicates that the system is operating according to the TDD mode and to provide FDD operational information when the at least one first information bit indicates that the system is operating according to the FDD mode; and
provide the at least one first information bit and the at least one second information bit in a portion of a transmission frame; and
a memory coupled to the at least one processor.
13. A computer program product comprising:
non-transitory computer-readable medium comprising:
code for causing a computer to provide at least one first information bit configured to indicate that a wireless communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
code for causing the computer to provide at least one second information bit configured to provide TDD operational information when the at least one first information bit indicates that the system is operating according to the TDD mode and to provide FDD operational information when the at least one first information bit indicates that the system is operating according to the FDD mode; and
code for causing the computer to provide the at least one first information bit and the at least one second information bit in a portion of a transmission frame to be transmitted in the wireless communication system.
2. The method as defined in
3. The method as defined in
4. The method as defined in
5. The method as defined in
indicate TDD partition information when the at least one first information bit indicates TDD operation of the wireless communication system, and
indicate whether the wireless communication system is operating according to one of half-duplex FDD operation and full-duplex FDD operation when the at least one first information bit indicates FDD operation of the wireless communication system.
6. The method as defined in
8. The apparatus as defined in
9. The apparatus as defined in
10. The apparatus as defined in
11. The apparatus as defined in
indicate TDD partition information when the at least one first information bit indicates TDD operation of the wireless communication system, and
indicate whether the wireless communication system is operating according to one of half-duplex FDD operation and full-duplex FDD operation when the at least one first information bit indicates FDD operation of the wireless communication system.
12. The apparatus as defined in
14. The computer program product as defined in
15. The computer program product as defined in
16. The computer program product as defined in
17. The computer program product as defined in
indicate TDD partition information when the at least one first information bit indicates TDD operation of the wireless communication system, and
indicate whether the wireless communication system is operating according to one of half-duplex FDD operation and full-duplex FDD operation when the at least one first information bit indicates FDD operation of the wireless communication system.
18. The computer program product as defined in
20. The apparatus as defined in
21. The apparatus as defined in
22. The apparatus as defined in
23. The apparatus as defined in
indicate TDD partition information when the at least one first information bit indicates TDD operation of the wireless communication system, and
indicate whether the wireless communication system is operating according to one of half-duplex FDD operation and full-duplex FDD operation when the at least one first information bit indicates FDD operation of the wireless communication system.
24. The apparatus as defined in
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The present Application for Patent claims priority to Provisional Application No. 60/971,201 entitled “METHOD AND APPARATUS FOR INCLUDING TDD/FDD MODE AND TDD PARTITION INFORMATION IN ACQINFO BLOCK FOR SYSTEM ACQUISITION” filed Sep. 10, 2007, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
1. Field
The present disclosure generally relates to methods and apparatus for including mode information in a frame for system acquisition, and more particularly to including mode information in a frame preamble concerning whether a transmission in a TDD or FDD mode.
2. Background
In particular communication systems that support both frequency division duplex (FDD) and time division duplex (TDD) communication modes, acquisition of timing information during system acquisition at a user equipment (UE) is dependent on the particular communication mode. Accordingly, a user device operable in such systems has to determine whether a current transmission mode is FDD or TDD before timing acquisition. Various known communication systems, however, do not actively communicate the particular mode of operation, thus leading to difficulty and inefficiency in acquiring timing information during system acquisition.
Further, in particular types of these systems, such as the Mobile Broadband Wireless Access (MBWA) according to IEEE standard 802.20, it is known to employ inserted acquisition information (e.g., AcqInfo) in a preamble of a transmission frame (e.g., a superframe) to assist in system acquisition. This information, however, does not presently communicate whether current transmission to a user device is according to TDD or FDD modes, leading to difficultly in timing acquisition. It is noted, however that the acquisition information (AcqInfo), according to IEEE 802.20, employs a HalfDuplexEnable bit that communicates whether transmissions during FDD mode are full duplex or half duplex, dependent on the binary state of the bit. In TDD modes, however, various different partitions of time divided resources for forward link transmissions (e.g., transmission from a base station or access point (AP) to a user equipment (UE), access terminal (AT) or mobile device) and reverse link transmissions (e.g., transmission from a UE, AT, or mobile device to a base station or AP) is known. If the particular partition ratio of downlink frames to uplink frames is not known by devices in the system, which is typical in known systems, timing acquisition may be further delayed.
According to an aspect, a method for use in a wireless communication system is disclosed. The method includes providing at least one first information bit configured to indicate that the communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode. Further, the method includes providing the at least one first information bit in a preamble of a transmission frame.
According to another aspect, an apparatus operable in a wireless communication system is disclosed. The apparatus includes at least one processor configured to: provide at least one first information bit configured to indicate that the communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode. The at least one processor is also configured to provide the at least one first information bit in a preamble of a transmission frame. A memory coupled to the at least one processor is also included in the apparatus.
According to still a further aspect, a computer program product comprising computer-readable medium is disclosed. The computer-readable medium includes code for causing a computer to provide at least one first information bit configured to indicate that a wireless communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode. The medium also includes code for causing the computer to provide the at least one first information bit in a preamble of a transmission frame to be transmitted in the wireless communication system.
According to yet one further aspect, an apparatus operable in a wireless communication system is disclosed. The apparatus includes means for providing at least one first information bit configured to indicate that the communication system is operating according to one of a time division duplex (TDD) mode and a frequency division duplex (FDD) mode. Also included is means for providing the at least one first information bit in a preamble of a transmission frame.
The present disclosure features methods and apparatus that provide information in a transmission frame to communicate the mode of the transmission; namely, whether the transmission is an FDD or a TDD transmission. The information may comprise a single binary bit within a preamble of a transmission frame (i.e., a superframe) that communicates either an FDD or a TDD transmission mode to an apparatus receiving the transmission frame. Additionally, in another aspect the present disclosure also includes methods and apparatus that reuse an extant resource, such as a HalfDuplexEnable bit in a IEEE 802.20 system as an example, to not only communicate full or half duplex mode when transmitting according to FDD, but also with an added feature of communicating partition information when transmitting according to TDD.
It is noted that the system of
TDM Pilot 3 channel 210 may be utilized to communicate additional system information to receiving devices. According to an aspect, it is noted that in MBWA systems (i.e., IEEE 802.20 standard) information included in TDM Pilot 3 does not include information concerning whether the present transmission to the receiving device is FDD or TDD transmission. Accordingly, the present methods and apparatus provide at least one additional bit of information in the preamble, such as in TDM 3, that communicates whether the transmission is an FDD or a TDD transmission. As an example, a zero (0) state of the bit could indicate FDD mode and a one (1) state indicate TDD mode.
Also in MBWA systems (i.e., IEEE 802.20 standard), in particular, the TDM 3 channel includes an acquisition information (AcqInfo) block (not shown) transmitted in the preamble for system acquisition. Accordingly, in an aspect, it is contemplated that the additional bit discussed above may be included in the AcqInfo block, but is not limited to such placement and may be included in any portion of a superframe preamble. Regardless whether the bit is added to the AcqInfo block or elsewhere in the preamble, the addition of this single bit adds minimal overhead to the superframe. It is noted that additional bits beyond one bit may be utilized in the preamble to communicate further information, or communicate modes if more than two modes are supported by a communication system, as another example.
It is known that in TDD transmissions particular forward link and reverse link duplexed transmissions are alternated or partitioned over time in particular prescribed ratios. As an illustration,
In certain communication systems, it is known to utilize a bit in the preamble to indicate during an FDD mode whether the FDD transmission is full duplex or half-duplex. For MBWA systems, as a specific example, this existing bit is termed the “HalfDuplexEnable” bit and is located in the AcqInfo block. No indication is presently given in such systems operating in a TDD mode concerning the particular partitioning for the TDD transmission, such as the partitioning illustrated in
It is noted that the one or more of the processes of method 500 may be repeated for each superframe assembled and transmitted in a communication system. Alternatively, one or more of the processes of method 500 may be performed periodically, where only periodic superframes will be provided with the added bit information.
Apparatus 600 may include a number of various components communicatively coupled by a communication bus 602, which may include a power bus, a control signal bus, a status signal bus, a data bus, any combination thereof, or any other suitable communication link. Also included in apparatus 600 is at least one processor 604 that controls operation of the apparatus 600. The processor 604 may also be referred to as a central processing unit (CPU). Apparatus 600 also includes a memory 606, which may include both read-only memory (ROM) and random access memory (RAM) that provides instructions and data to the processor 604. A portion of the memory 606 may also include non-volatile random access memory (NVRAM), as an example. The processor 604 is configured to perform logical and arithmetic operations based on program instructions stored within memory 606. Moreover, the instructions in memory 606 may be executable to implement the methods described herein.
Apparatus 600 may also include a transmitter/receiver circuitry 608 to provide transmission and reception of wireless signals between a wireless device employing apparatus 600 and another wireless device, for example. One or more antennas 610 may be communicatively coupled to the transmitter/receiver circuitry 608 as illustrated in
Apparatus 600 may also include a transmission frame assembly module 612 configured as means to effect the functions and methods described herein, such as the various processes and functions described above in connection with
It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosed examples is provided to enable any person skilled in the art to make or use the presently disclosed methods or apparatus. Various modifications to these examples will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other examples without departing from the spirit or scope of the disclosure. It is also noted that the word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any example described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples. Thus, the present disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Patent | Priority | Assignee | Title |
11013000, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for inter-band pairing of carriers for time division duplex transmit- and receive-switching and its application to multiplexing of different transmission time intervals |
11019620, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for inter-band pairing of carriers for time division duplex transmit- and receive-switching and its application to multiplexing of different transmission time intervals |
11153875, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for inter-band pairing of carriers for time division duplex transmit- and receive-switching and its application to multiplexing of different transmission time intervals |
11357022, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for interference mitigation utilizing thin control |
11382109, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for synchronous multiplexing and multiple access for different latency targets utilizing thin control |
11432305, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for synchronous multiplexing and multiple access for different latency targets utilizing thin control |
11452121, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for synchronous multiplexing and multiple access for different latency targets utilizing thin control |
11503618, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for synchronous multiplexing and multiple access for different latency targets utilizing thin control |
11832230, | May 19 2014 | Qualcomm Incorporated | Apparatus and method for inter-band pairing of carriers for time division duplex transmit- and receive-switching and its application to multiplexing of different transmission time |
8780767, | Sep 10 2007 | Qualcomm Incorporated | Methods and apparatus for including mode information in a frame for system acquisition |
Patent | Priority | Assignee | Title |
5987010, | May 15 1997 | MICROSEMI SEMICONDUCTOR U S INC | System and method for providing FDD and TDD modes of operation for a wireless communications device |
6788253, | Sep 29 2003 | Lucent Technologies Inc. | Method and apparatus for use in improving accuracy in geo-location estimates |
20010043572, | |||
20070054667, | |||
20070097887, | |||
20070097908, | |||
20070161389, | |||
20080165675, | |||
20080165709, | |||
20080166969, | |||
20090052355, | |||
20090262671, | |||
20100020731, | |||
EP1631098, |
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