A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure.
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1. A method for growing crystalline nanostructures onto a substrate, the method comprising:
providing a pattern on a main surface of the substrate, wherein the pattern has at least one opening, the opening extending from a surface of the pattern to the main surface of the substrate, and wherein at least a portion of the main surface of the substrate is exposed;
providing a metal in the opening of the pattern on the exposed main surface;
at least partly filling the opening with an amorphous material, and
annealing the amorphous material and the metal at a temperature of from about 300° C. to about 1000° C., thereby transforming at least a part of the amorphous material into crystalline material by metal mediated crystallization to form a crystalline nanostructure.
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depositing a layer on a main surface of the substrate; and thereafter
forming a pattern having at least one opening into the deposited layer using at least lithographic patterning, wherein the opening has a diameter of from about 2 nm to about 100 nm.
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This application claims the benefit under 35 U.S.C. §119(e) of U.S. provisional application Ser. No. 61/075,141, filed Jun. 24, 2008, the disclosure of which is hereby expressly incorporated by reference in its entirety and is hereby expressly made a portion of this application.
Methods for formation of single crystal nanowires, e.g., having an n-type and/or p-type dopant, are provided, as are methods for formation of segmented nanowires having segments (regions) containing different dopant types or segments (regions) containing different nanowire material.
Nanostructures such as NanoWires (NW) and Carbon Nanotubes (CNT) have been identified as one of the most promising candidates to extend and even replace materials currently used in microelectronic manufacturing processes. For example, metallic CNT have been proposed as nano-electronic interconnects due to their high current carrying capacity, whereas semiconducting NanoWires (NW) have been indicated as nanoscale transistor elements due to the possibility of forming wrap-around gates and exploitation of quantum confinement effects in the narrow wires. These and similar applications cannot be fully accomplished yet since the fabrication of nanostructures still faces a variety of unsolved issues, which vary from one application to another but may, however, be similar in some aspects as discussed below.
Vapor-liquid-solid (VLS) growth is one of the most common methods used to synthesize NW connecting with other components in a semiconductor device. However, the growth temperature for NW in a chemical vapor deposition (CVD) chamber is typically around 600° C.-700° C. which is relatively high. This high temperature can readily damage the underneath device layer. Therefore, to reduce the growth temperature and at the same time to synthesize a crystalline structure is an important issue.
Liu et al. [Japanese Journal of Applied Physics Vol. 46, No. 9B, 2007, pp. 6343-6345] describes a VLS based growth technique making use of an Anodic Anodized Oxide (AAO) template and Au nanoparticles as catalyst to form silicon nanowires inside the AAO template. By using the AAO template the growth temperature could be lowered to 400° C.-550° C. because the alumina in the AAO template acts as an extra catalyst in addition to the Au catalyst particles.
Another issue is the growth of segmented NW, e.g. a NW having a first segment made of a first semiconducting material and a second segment made of a second semiconducting material. A VLS based growth technique is suitable to achieve e.g. segmented III-V nanowires, but as mentioned above this technique requires relative high growth temperatures (e.g. in the range of 600° C.-700° C.).
Still another issue is the controlled doping of the (semiconducting) NW. It is difficult to control the dopant concentration in the NW and to obtain in a NW low dopant concentrations of e.g. lower than 1017 in the nanowire or very high dopant concentrations of e.g. higher than 1018. Using the VLS technique, one can add dopant gasses to the gas mixture for growth but due to the fact that the doping concentrations in the gas mixture are very low, it is very difficult to control the dopant concentration in the gas-phase versus the incorporated dopant concentration in the nanostructure. Moreover it is hard to obtain high concentration this way.
As a conclusion there still exist a problem in the state of the art to provide an easy controllable growth method, preferably at low temperatures, to obtain mono-crystalline nanostructures which method is capable to incorporate specific concentrations of dopant elements and which method is capable of forming easily segmented nanostructures made of at least two segments made of two different semiconducting materials.
Methods for forming single-crystal nanowires are provided.
Novel and easy methods to grow NW at low temperatures, i.e. below 500° C. are provided.
A novel and easy growth method is provided to provide doped single-crystal nanostructures wherein the concentration of the dopant elements within the nanostructure is very well controllable. Using the method of the preferred embodiments it is possible to control the concentration of dopant elements in the nanostructure in the range of 1013/cm3 up to 1021/cm3.
A novel and easy growth method is provided to provide segmented nanostructures or in other words a nanostructure having at least two segments, i.e. a first segment made of a first semiconducting material and a second segment made of a second semiconducting material.
Methods are provided which are scalable and fully compatible with existing semiconductor processing, for example for manufacturing nanodevices. The methods provided herein can be performed on any size of substrate.
Methods are provided which allow the growth of monocrystalline nanostructures with control over the diameter and length of the nanostructures such that predetermined diameter, length and density is obtained.
Methods are provided which allow forming elongated mono-crystalline nanostructures at a predetermined location.
Selected methods of preferred embodiments use a combination of templated electrochemical deposition (ECD) and a novel constrained metal-mediated crystallization (MMC).
In a first aspect, a method is provided for growing mono-crystalline nanostructures onto a substrate.
The method comprises at least the steps of:
According to preferred embodiments, the substrate or at least the top-layer of the substrate is made of a conductive (metallic) or semi conductive (Si, Ge, III-V semiconductor) material when Electro Chemical Deposition (ECD) is used. The substrate or the top-layer of the substrate may be made of an insulating material when vacuum and physical vapor deposition (PVD) techniques are used to provide the metal compound.
According to preferred embodiments, the pattern has openings extending to the top-layer surface of the substrate, and said top-layer surface of the substrate comprises a (copper) Back End Of Line interconnect structure of a semiconductor device. The openings hence extend towards (copper) interconnect structures.
According to preferred embodiments, the pattern may be a porous pattern such as Anodized Aluminum Oxide (AAO), an oriented zeolite or holes formed in a dielectric such as silicon-oxide, a photoresist pattern, etc.
According to preferred embodiments, providing a pattern may comprise:
According to preferred embodiments, the pattern has openings extending to the surface of the substrate in the nanometer range, more preferably in the range of 2 nm up to 100 nm.
According to preferred embodiments, the pattern may be a permanent pattern or alternatively a sacrificial pattern.
According to preferred embodiments, the pattern is a sacrificial pattern which is removed after formation of the nanostructures using wet etching or dry etching techniques. The removal technique must be selective towards the pattern and not harm the nanostructures and/or substrate underneath the pattern. In case the pattern is a silicon-oxide such as SiO2, the pattern can be removed using a wet or vapour HF treatment.
According to preferred embodiments the step of providing a metal into the openings of the pattern is performed using electrochemical deposition (ECD) or alternatively by other state of the art techniques such as Chemical Vapour Deposition (CVD) or Physical Vapor Deposition (PVD). The metal is selected for metal-mediated crystallization (MMC) of the amorphous material. Suitable metals are e.g. Au, Ni, Co, In, Ga. The suitable temperature range for MMC is determined by the choice of metal; e.g. the temperature will be lower for low melting point metals such as In, Ga and higher for high temperature melting point materials such as Ni and Co. Also metal alloys may be considered. The metal can thus be a single metal or a metal compound or a metal alloy.
According to preferred embodiments, the metal may contain dopant elements. These dopant elements are selected to dissolve into the amorphous material during MMC anneal to obtain a doped crystalline nanostructure.
According to preferred embodiments the step of partly filling the opening with amorphous material is performed using electrochemical deposition (ECD). The amorphous material may be amorphous Si (a-Si), amorphous Ge (a-Ge), amorphous InSb (a-InSb), amorphous carbon (a-C). Ge and Si are typically electrodeposited from organic or ionic solutions while InSb is typically electrodeposited from aqueous solutions.
According to preferred embodiments, the amorphous material may contain dopant elements. Preferably incorporation of the dopant element in the amorphous material is performed by co-deposition of the dopant element and the amorphous material. Typically P, As, Sb or Bi are used as dopant elements to form an n-type doped (Si) material and B, Al, Ga and In are used as dopant elements to form a p-type doped (Si) material.
To obtain a variation in dopant concentration in a nanostructure according to preferred embodiments, first the amorphous material, e.g. amorphous Si, containing dopant elements, e.g. containing P, is co-deposited in a predetermined thickness, e.g. 50 nm, followed by the deposition of the amorphous material in a predetermined thickness, e.g. 150 nm, without any dopant elements. A doping “profile” may be achieved during the crystallization step of the preferred embodiments and/or by performing a further (additional) annealing step after the crystallization step to achieve a doping profile.
According to preferred embodiments, annealing the amorphous material and the metal, is performed at temperatures between 300° C. and 1000° C., depending on the metal-amorphous material combination used for MMC. For example, a temperature in the range 300° C.-400° C. may be used for low-melting point metals such as In, a temperature in the range 500° C.-600° C. for metals such as Ni, Fe and Co and a temperature in the range 900° C.-1000° C. for transition metals such as Ti. The annealing is preferably performed for approximately 1 hour in inert atmosphere or in a vacuum atmosphere. Annealing the amorphous material converts the amorphous material into crystalline material, more preferably mono-crystalline material by diffusion of the amorphous material into the metal. Crystallization is happening by segregation and in the crystallization process the metal phase moves through the amorphous phase leaving behind a crystallized phase until the metal finally ends up on top of the formed crystalline nanostructure. The segregating crystalline phase is mono-crystalline due to the confinement of the pore walls or openings, as the typical grain size in bulk MMC is larger than pore diameter or opening diameter. This phenomenon is denoted as constrained metal-mediated crystallization (CMMC).
According to preferred embodiments, the annealing step may be performed by a Rapid Thermal Anneal.
According to preferred embodiments, after the thermal anneal step full crystallization of the amorphous material is obtained and a single crystalline nanostructure (wire) is obtained with the formed metal on top.
According to preferred embodiments, after crystallization of the amorphous material the metal particle may be removed.
In a second aspect, a method is provided for growing segmented crystalline nanostructures onto a substrate.
The method comprises at least the steps of:
According to an alternative method for growing segmented crystalline nanostructures onto a substrate, the method comprises at least the steps of:
According to preferred embodiments, the method for growing segmented crystalline nanostructures onto a substrate is used to manufacture hetero junctions. Hetero-junctions are made of at least two segments, each segment being formed in another semiconducting material, e.g. first segment made of Si and then a second segment made of Ge.
According to preferred embodiments, the metal used to crystallize the first amorphous material into a first mono-crystalline material is removed after the step of annealing the first amorphous material and a second metal is deposited onto the first mono-crystalline material. Onto said second metal a second amorphous material is deposited and the second metal is then used to crystallize the second amorphous material into a second mono-crystalline material.
According to preferred embodiments, the metal can be a metal alloy made of at least two metals wherein the first metal is chosen such that it selected to crystallize the first amorphous material into a first mono-crystalline material and wherein the second metal is selected to crystallize the second amorphous material into a second mono-crystalline material.
According to preferred embodiments, the metal is mixed with dopant elements to achieve doping of the amorphous material. The dopant elements are incorporated into the amorphous material during crystallization. In this case the metal compound is replaced in between the segments.
According to preferred embodiments, the first amorphous material may be a-Si, a-Ge, a-InSb, or a-C mixed with a small percentage of dopant elements such as P, As, Sb, Bi as n-type dopants for Si and Ge, or B, Al, Ga as p-type dopant elements for Si and Ge, preferentially by electrochemical co-deposition. The second amorphous material may be the same amorphous material as the first amorphous material but mixed with a small percentage of the opposite dopant elements, or the same dopant elements but in different concentration, or no dopant elements to make an intrinsic part.
According to preferred embodiments, the first amorphous material may be a-Si, a-Ge, a-InSb, or a-C mixed with a small (e.g. 1-3 wt %) percentage of dopant elements such as P, As, Sb, Bi as n-type dopants for Si and Ge, or B, Al, Ga as p-type dopant elements for Si and Ge, preferentially by electrochemical co-deposition. The second amorphous material may be a different amorphous material, referred to as hetero-junction, as the first amorphous material with or without incorporated dopant elements.
According to preferred embodiments, the co-deposition technique may comprise alloy co-deposition in which both the metal compound and the dopant element, e.g. B, As, P, or the like, may be deposited from dissolved ions in an electrolyte.
According to other preferred embodiments, the co-deposition technique may comprise particle co-deposition in which dopant elements are nanoparticles which are dispersed in a solution and the metal compound “matrix” is deposited from dissolved metal ions in the solution.
According to preferred embodiments, the step of filling the at least one opening with amorphous material may be performed by electrochemical deposition or by electroless deposition.
The preferred embodiments provide in a further aspect, the use of the methods in the manufacturing process of semiconductor devices.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.
Although there has been constant improvement, change and evolution of devices in this field, the present concepts are believed to represent substantial new and novel improvements, including departures from prior practices, resulting in the provision of more efficient, stable and reliable devices of this nature.
The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.
All drawings are intended to illustrate some aspects and preferred embodiments. Not all alternatives and options are shown and therefore the invention is not limited to the content of the attached drawings. Like numerals are used to reference like parts in the different figures. The figures may show preferred embodiments.
In the different figures, the same reference signs refer to the same or analogous elements.
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention. The invention will be described by a detailed description of several preferred embodiments. It is clear that other preferred embodiments can be configured according to the knowledge of persons skilled in the art without departing from the true spirit or technical teaching of the invention, the invention being limited only by the terms of the appended claims.
Moreover, the terms top, bottom and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the preferred embodiments described herein are capable of operation in other orientations than described or illustrated herein.
The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
Similarly it should be appreciated that in the description of exemplary preferred embodiments, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.
In the description provided herein, numerous specific details are set forth. However, it is understood that preferred embodiments may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
With the term nanostructures is meant any two-dimensionally confined piece of solid material in the form of wires (nanowires), tubes (nanotubes), rods (nanorods) and similar elongated substantially cylindrical or polygonal nanostructures having a longitudinal axis. A cross-sectional dimension of the nanostructures preferably lies in the region of 1 to 500 nanometers. According to preferred embodiments, nanostructures, such as e.g. carbon nanotubes (CNT) or inorganic nanostructures, such as e.g. semiconducting nanowires (e.g. silicon nanowires) are included.
The term “co-deposition” means that two or more elements are deposited at a same time, e.g. from a same bath, to respectively form an alloy or a composite. Different aspects and types of “co-deposition” are known in state of the art and described e.g. in “Electrochemical and Materials Science Aspects of Alloy Deposition”, D. Landolt, Electrochimica Acta, Vol. 39, 1075-1090, 1994.
The preferred embodiments relate to a method to provide mono-crystalline nanostructures. The preferred embodiments further relate to doped single-crystal nanostructures wherein the concentration of the dopant elements within the nanostructure is very well controllable. Using the method of the preferred embodiments it is possible to control the concentration of dopant elements in the nanostructure in the range of 1013/cm3 up to 1021/cm3.
The preferred embodiments further relate to a method to provide a novel and easy growth method to provide segmented nanostructures or in other words a nanostructure having at least two segments.
The methods of the preferred embodiments make use of templated electrochemical deposition (ECD) and metal-mediated crystallization (MMC).
In one aspect, a method is provided for mono-crystalline nanostructures onto a substrate.
The method comprises at least the steps of:
The mono-crystalline nanostructures formed by the method according to preferred embodiments may advantageously be used with any size of substrate and are fully compatible with semiconductor processing technology.
As illustrated in
Onto the substrate 1, a pattern 2 is formed wherein the pattern 2 has at least one opening, the opening extending to the main surface of the substrate. The openings extending to the surface of the substrate are preferably in the nanometer range, more preferably in the range of 2 nm up to 100 nm. The pattern may be a permanent pattern 2 or alternatively a sacrificial pattern 2.
The pattern 2 may be a porous pattern such as Anodized Aluminum Oxide (AAO), an oriented zeolite or holes formed in a dielectric layer, e.g. SiO2, a photoresist pattern, etc.
According to preferred embodiments, the step of providing the pattern 2 may be performed by first depositing a layer and subsequently patterning at least one opening in the deposited layer to form the pattern 2 as shown in
According to preferred embodiments, the deposited layer can be a silicon oxide layer, e.g. a SiO2 layer which may, for example, be formed by Chemical Vapour Deposition (CVD). According to other preferred embodiments, the deposited layer may be an organic spin-on material such as, for example, commonly used polymer resist materials for lithography (e.g. PMMA (poly-methyl methacrylate)) or an organic low-k dielectric material such as e.g. SiLk®. The thickness of the deposited layer depends on the application and on the size, more particularly height of the mono-crystalline nanostructure to be formed. The thickness of the deposited layer may, for example, be in the range of between 10 nm and 100 μm and more specifically between 100 nm and 1 μm for CMOS applications.
After forming openings in the deposited layer to achieve the pattern 2, the substrate 1 may be immersed in an electrolytic bath to perform deposition of the metal. This may, for example be done by Electrochemical Deposition (ECD) by electroless means or electrolytic means. During the deposition process, the bottom of the openings in the pattern 2 is covered with the metal 3.
According to preferred embodiments, the metal 3 is such that metal-mediated crystallization of amorphous material is possible. Suitable metals are e.g. Au, Ni, Co, Fe, Al, In, Ga, Ti, or the like. Au particles may be deposited starting from an Au(I) solution (e.g. 0.01M Na3Au(S2O3)2) in an electrolyte, e.g., 0.1M Na2S2O3, 0.1M Na2SO3, 0.3M Na2HPO4.
Alternatively, also metal alloys may be considered. These metal alloys may be deposited into the openings of the pattern 2 using electrochemical co-deposition.
According to preferred embodiments, the metal 3 may contain dopant elements. These dopant elements are chosen to dissolve into the amorphous material 4 during the subsequent Metal Mediated Crystallization (MMC) step thereby achieving a doped crystalline nanostructure 5 after annealing. The metal containing a predetermined amount of dopant elements may be deposited into the openings of the pattern 2 using electrochemical co-deposition. As known by a person skilled in the art, electrochemical co-deposition of the metal 3 and the dopant element, having standard potentials that are far apart can lead to a large difference in deposition rates of the two materials. Details of co-deposition processes are described e.g. in “Electrochemical and Materials Science Aspects of Alloy Deposition”, D. Landolt, Electrochimica Acta, Vol. 39, 1075-1090, 1994.
In a next step of a method according to preferred embodiments, which is illustrated in
InSb may be deposited using electrochemical deposition starting from a solution of 0.025M InCl3, 0.025M SbCl3, 0.2M citric acid and 0.06M sodium citrate at a pH around 2.2. Amorphous InSb deposits (1:1 In:Sb ratio) in hole patterns at deposition potentials between −0.8V and −1.45V versus the Ag/AgCl reference electrode for a deposition charge of −50 mC/cm2 for 330 nm holes.
According to preferred embodiments, the amorphous material 4 may contain dopant elements. Preferably incorporation of the dopant element in the amorphous material 4 is performed by co-deposition of the dopant element and the amorphous material 4. Typically P, As, Sb or Bi are used as dopant elements to achieve an n-type doped (Si) material and B, Al, Ga and In are used as dopant elements to achieve a p-type doped (Si) material.
To achieve a variation in dopant concentration in a nanostructure according to preferred embodiments, first the amorphous material 4 (e.g. amorphous Si) containing dopant elements, e.g. containing P, is co-deposited in a predetermined thickness, e.g. 50 nm, followed by the deposition of the amorphous material 4 in a predetermined thickness, e.g. 150 nm, without any dopant elements. A doping “profile” may be achieved during the crystallization step of the preferred embodiments and/or by performing a further (additional) annealing step after the crystallization step to achieve a doping profile.
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An alternative processing method for growing crystalline segmented nanostructures, e.g., having a first segment made of a first monocrystalline material 5 and a second segment made of a second monocrystalline material 6 is illustrated in
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In case the metal 3 used to achieve MMC within the first amorphous material 4 is also used to achieve MMC within the second amorphous phase, the metal 3 can remain. In case the metal 3 is not used to achieve MMC within the second amorphous material 6, a new metal is deposited on the formed first segment after removal of the first metal from the first segment. Alternatively, the metal is a metal alloy made of at least two different metals wherein the first metal is used to create MMC within the first amorphous material 4 and the second metal is used to create MMC within the second amorphous material 6.
As illustrated in
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It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope of this invention as defined by the appended claims.
All references cited herein are incorporated herein by reference in their entirety. To the extent publications and patents or patent applications incorporated by reference contradict the disclosure contained in the specification, the specification is intended to supersede and/or take precedence over any such contradictory material.
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