A system or circuit for simulating a potentiometer, thermistor, or the like. A pulse stream, having a duty cycle which is varied as a changing pulse width or as a differing number of time slices per time period, may be input to the system. The pulse stream to a transistor or switch-like mechanism may allow a controlled connection of a fixed value resistor to a reference voltage or ground to provide various resultant values of impedance or resistance. A measuring circuit connected to the output of the system may determine a value which is of the fixed value resistor divided by the duty cycle of the pulse train effectively controlling the connection of the resistor to ground. One or more additional circuits may be connected in parallel to achieve greater accuracy.
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17. A digital potentiometer system comprising:
a first resistor having first and second ends;
a second resistor having a first end connected to the second end of the first resistor, and having a second end;
a semiconductor having a first terminal connected to the second end of the second resistor, and having second and third terminals; and
a capacitance connected between the first end of the second resistor and the third terminal of the semiconductor; and
wherein:
the second and third terminals of the semiconductor are for receiving signals having a duty cycle; and
the duty cycle can be modulated to adjust an amount of resistance between the first end of the second resistor and the third terminal of the semiconductor.
13. A method of providing a variable resistance, comprising:
connecting first and second resistances in a series having a first end, a common connection and a second end;
connecting a first terminal of a switch to the second end of the series;
connecting the first end of the series to a first voltage terminal;
connecting a third terminal of the switch to a second voltage terminal, wherein a third resistance is between the common connection and the third terminal of the switch;
connecting a second terminal of the switch to a signal source for controlling a connection between the first and third terminals of the switch; and
connecting a first terminal of a capacitive element to the common connection and a second terminal of the capacitive element to the third terminal of the switch.
1. An adjustable impedance system comprising:
a first impedance having a first end and a second end;
a second impedance having a first end connected to the second end of the first impedance, and having a second end;
a switch having a first terminal connected to the second end of the second impedance, and having second and third terminals; and
a capacitance having a first terminal connected to the first end of the second impedance and a second terminal connected to the third terminal of the switch; and
wherein:
the second terminal of the switch is an input for a signal to control a connection between the first and third terminals of the switch;
to control the connection between the first and third terminals of the switch is to control a third impedance between the first end of the second impedance and the third terminal of the switch, wherein the capacitance is in parallel with the third impedance; and
each of the first and second impedances comprises one or more resistors.
7. An adjustable impedance system comprising:
a first impedance having a first end and a second end;
a second impedance having a first end connected to the second end of the first impedance, and having a second end; and
a switch having a first terminal connected to the second end of the second impedance, and having second and third terminals; and
wherein:
the second terminal of the switch is an input for a signal to control a connection between the first and third terminals of the switch; and
to control the connection between the first and third terminals of the switch is to control a third impedance between the first end of the second impedance and the third terminal of the switch;
each of the first and second impedances comprises one or more resistors;
the switch is a semiconductor;
the signal comprises a duty cycle;
a size of the duty cycle determines a magnitude of the third impedance;
the signal comprises a stream of time slices; and
a number of time slices per period of time effectively determines the size of the duty cycle.
2. The system of
a fourth impedance having a first end connected to the second end of the first impedance, and having a second end; and
a second switch having a first terminal connected to the second end of the fourth impedance, and having second and third terminals; and
wherein:
the second terminal of the second switch is an input for a signal to control a connection between the first and third terminals of the second switch; and
to control the connection between the first and third terminals of the second switch is to control a fifth impedance between the first end of the fourth impedance and the third terminal of the second switch.
3. The system of
the first end of the first impedance is for connection to a first voltage; and
the third terminal of the switch is for connection to a second voltage.
5. The system of
the signal comprises a duty cycle; and
a size of the duty cycle determines a magnitude of the third impedance.
6. The system of
the signal comprises a stream of pulses;
a temporal size of each pulse determines the size of the duty cycle.
8. The system of
9. The system of
10. The system of
the signal is digital;
an output is across the third impedance; and
the output is for providing a digital impedance simulation in accordance with the signal.
11. The system of
12. The system of
the impedance system provides a level of digital adjustment; and
the system further comprises one or more additional impedance systems connected in parallel with the system for more levels of adjustment.
14. The method of
a magnitude of the third resistance is determined by the connection between the first and third terminals of the switch.
15. The method of
providing a signal from the signal generator to the second terminal of the switch; and
wherein:
the signal comprises train of pulses having a duty cycle;
the duty cycle is between equal to or greater than zero percent and equal to or less than one-hundred percent;
the duty cycle is determinative of an amount of connection between the first and third terminals of the switch; and
the amount of connection affects the magnitude of the third resistance.
18. The system of
an output is between the first end of the second resistor and the third terminal of the semiconductor;
the first end of the first resistor is connected to a first voltage terminal; and
the third element of the semiconductor is connected to a second voltage terminal.
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The invention pertains to electronic components and particularly to impedance devices. More particularly, the invention pertains to digital simulation of variable impedance devices.
The invention is a digital potentiometer system for simulating such things as a potentiometer, thermistor, and the like.
The invention is a system 10, as shown in
The pulse stream or train 23 may instead be a series of time slices or pulses as shown in
Specific voltage magnitudes, pulse widths and time slice sizes of the pulse train or stream waveforms may depend on the parameter values, types of the components in the circuit, and performance factors desired from the digital potentiometer circuit or system 10.
The present circuit 10 may permit the making of a virtual potentiometer by dividing the time which resistor 13 is in the circuit into small slices as discussed herein relative to
Pulse stream 23 may allow a controlled connection of fixed resistor 13 to a reference voltage or ground 14. A measuring or sensing circuit 19, which detects the value of the digital potentiometer 10 output between terminals 16 and 14, may see a value of the fixed resistor 13 divided by the duty cycle. For instance, if the duty cycle is 100 percent, then the measuring circuit 19 would see approximately the value of the fixed resistor 13. If the duty cycle is 50 percent, then it would see about two times the value of the fixed resistor 13, and so on. The measuring circuit 19 may include an analog-to-digital converter or other mechanism.
The pulse stream 23 may be fed into device 15 via a resistor 21. Device 15 may be a FET, bipolar transistor, or another semiconductor or mechanism. Device 15 may be a switch-like mechanism. A bipolar transistor may used as an illustrative example in
A capacitance or capacitor 17 may be connected across resistor 13 and transistor 15 (i.e., impedance or resistance 29) between terminal 16 and the emitter of transistor 15 or terminal 14. The capacitor symbol 17 of the
System 10 may be regarded as an adjustable impedance system that provides a level of digitization. Impedance 29 may be digitally prescribed by an input pulse train 23 of PWM pulses, time slices, or some other digital-like signals. Further, as shown in
Nominal components for circuits 10 and 20 may include a 1K ohm resistor 13, a ten microfarad capacitor 17, a 10K ohm resistor 18 and a 10K ohm resistor 21. Noted values of the components are for illustrative purposes. Other values may be implemented. Transistor 15 may be an NPN type such as a model 2N2222 available from various semiconductor vendors. A semiconductor or mechanism 15 of another type and model may be used in the system or circuits 10 and 20.
In the present specification, some of the matter may be of a hypothetical or prophetic nature although stated in another manner or tense.
Although the invention has been described with respect to at least one illustrative example, many variations and modifications will become apparent to those skilled in the art upon reading the present specification. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.
Thomas, Robert J., Underhill, Michael L.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Nov 19 2007 | THOMAS, ROBERT J | Honeywell International Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020171 | /0424 | |
Nov 19 2007 | UNDERHILL, MICHAEL L | Honeywell International Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020171 | /0424 | |
Nov 28 2007 | Honeywell International Inc. | (assignment on the face of the patent) | / |
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