A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.
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1. A method comprising:
forming a high voltage well over a substrate;
forming a reduced surface field region over said high voltage well;
forming a body region adjacent said reduced surface field region;
forming an isolation layer over the substrate including a predetermined area partially overlapped with said reduced surface field region;
forming a low voltage well over the substrate;
forming a gate electrode extending to a predetermined top surface of said isolation layer from a predetermined top surface of said body region; and
forming a drain region over said low voltage well;
forming a source region over said body region having at least a portion under said gate electrode;
forming a first conductivity type first impurity region under said reduced surface field region; and
forming a second conductivity type second impurity region under said first conductivity type first impurity region.
2. The method of
said isolation layer includes an area adjacent said high voltage well; and
at least a portion of at least one of said low voltage well and said drain region are formed over the substrate and below said area of said isolation layer adjacent said high voltage well.
3. The method of
forming a dielectric layer over said high voltage well;
forming a photoresist pattern over said dielectric layer; and
forming said first and second impurity regions by implanting a corresponding impurity ion using said photoresist pattern as ion implantation mask.
4. The method of
5. The method of
6. The method of
7. The method of
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The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0115090 (filed on Nov. 19, 2008) which is hereby incorporated by reference in its entirety.
Embodiments relate to a semiconductor device and a method of manufacturing the same. Some embodiments relate to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same.
A MOS Field Effect Transistor (MOSFET) may have relatively high input impedance compared to a bipolar transistor, providing an electrical benefit and/or a relatively simple gate driving circuit. A MOSFET may be a unipolar device having substantially no-time delay which may result from minority carrier storage and/or recombination while being turned off A MOSFET may be applied, for example, to switching mode power supply devices, lamp ballasts and/or motor driving circuits. A DMOSFET (Double Diffused MOSFET) may use planar diffusion technology.
A LDMOS transistor is described in U.S. Pat. No. 4,300,150 to Colak. A LDMOS device may be applied to a VLSI process due to its relatively simple structure. LDMOS devices may have minimized technical features than, for example, DMOS (VDMOS) devices. However, Reduced Surface Field (RESURF) SLMOS devices may have maximized on-resistance (Rsp).
Referring to
Electric currents may flow along a surface of a LDMOS device, which may minimize electric current driving efficiency. As shown in
Accordingly, there is a need for a LDMOS device and a method of manufacturing a LDMOS device that may minimize on-resistance and/or may acquire a relatively high breakdown voltage.
Embodiments relate to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. According to embodiments, a LDMOS device and a method of manufacturing the same may minimize on-resistance and/or may acquire a relatively high breakdown voltage.
According to embodiments, a lateral double diffused metal oxide semiconductor (LDMOS) device may include a high voltage well (HVWELL) formed on and/or over a substrate. In embodiments, a LDMOS device may include a reduced surface field (RESURF) region formed on and/or over a HVWELL. In embodiments, a LDMOS device may include a body region formed adjacent to a RESURF region. In embodiments, a LDMOS device may include an isolation layer having a predetermined area formed on and/or over a RESURF region. In embodiments, a isolation layer may partially overlap with a top surface of a substrate.
According to embodiments, a low voltage well (LVWELL) may be formed on and/or over a predetermined area of a substrate, which may be under an area of an isolation layer. In embodiments, a LDMOS device may include a gate electrode which may extend from a predetermined top surface area of a body region to a predetermined top surface of a isolation layer. In embodiments, a LDMOS device may include a drain region formed on and/or over a LVWELL, which may be under an area of an isolation layer. In embodiments, a LDMOS device may include a source region formed on and/or over a body region, which may have at least a portion under a gate electrode.
Embodiments relate to a method of manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device. According to embodiments, a method of manufacturing a LDMOS device may include forming a high voltage well (HVWELL) on and/or over a substrate. In embodiments, a method of manufacturing a LDMOS device may include forming a RESURF region on and/or over a HVWELL. In embodiments, a method of manufacturing a LDMOS device may include forming a body region adjacent to a predetermined area of a RESURF region. In embodiments, a method of manufacturing a LDMOS device may include forming an isolation layer on and/or over a substrate. In embodiments, an isolation layer may include a predetermined area which may be partially overlapped with an area of a RESURF region.
According to embodiments, a method of manufacturing a LDMOS device may include forming a low voltage well (LVWELL) on and/or over a substrate, which may be under an area of an isolation layer. In embodiments, a method of manufacturing a LDMOS device may include forming a gate electrode which may extend from a predetermined top surface of a isolation layer to a predetermined top surface of a body region. In embodiments, a method of manufacturing a LDMOS device may include forming a drain region on and/or over a LVWELL, which may be under an area of an isolation layer. In embodiments, a method of manufacturing a LDMOS device may include forming a source region on and/or over a body region, which may include at least a portion under a gate electrode.
Example
Example
Example
Embodiments relate to a LDOMS device. According to embodiments, a first conductivity type may be a p-type and a second conductivity type may be an n-type. However, a first conductivity type may be an n-type and a second conductivity type may be a p-type in accordance with embodiments. Referring to example
According to embodiments, p-type epilayer 100 may be formed on and/or over a p-type substrate. In embodiments, n-type high voltage well (HVWELL) 110 may be formed on and/or over p-type epilayer 100. In embodiments, n-type reduced surface field (RESURF) region 120 may be formed on and/or over HVWELL 110. In embodiments, n-type RESURF region 120 may be disposed under isolation layer 140 and/or gate dielectric layer 160. In embodiments, n-type RESURF region 120 may be disposed on and/or over a side of p-type body 130. In embodiments, a depth of n-type RESUF region 120 may be between approximately 1 μl and 1.2 μm.
According to embodiments, a LDMOS device may include p-type first impurity region 122 and/or n-type second impurity region 124. In embodiments, HVWELL 110 and/or p-type first impurity region 122 may be formed under n-type RESURF region 120. In embodiments, n-type second impurity region 124 may be formed under p-type first impurity region 122. In embodiments, unlike a LDMOS device shown in
According to embodiments, p-type body region 130 may be formed on and/or over a predetermined area between n-type RESURF region 120 and p-type first impurity region 122. In embodiments, isolation layer 140 may include a predetermined area formed on and/or over n-type RESURF region 120, and/or an area formed on and/or over n-type HVWELL 110. In embodiments, isolation layer 140 may include a field oxide layer, for example, silicon oxide that may thermally grow.
According to embodiments, n-type low voltage well (LVWELL) 150 may be formed on and/or over n-type well 110 of a substrate, which may be formed under an area of isolation layer 140 which may be adjacent a high voltage well. In embodiments, a gate pattern may include gate dielectric layer 160 and/or gate electrode 162. In embodiments, gate electrode 162 may extended to a top surface of isolation layer 140 from a top of p-type body region 130. In embodiments, gate electrode 162 may be poly silicon doped with impurity. In embodiments, gate dielectric layer 160 may be formed on and/or over a predetermined area from a top of p-type body region 130 to isolation layer 140, which may be under gate electrode 162.
According to embodiments, high density n-type drain region 172 may be formed on and/or over LVWELL 150, which may be under an area of isolation layer 140. In embodiments, high density n-type source region 170 may be on and/or over an upper area of p-type body region 130, and/or may be adjacent to gate pattern 160 and/or 162. In embodiments, high density p-type region 174 may be a source contact layer to contact source region 170. In embodiments, p-type region 174 may have a maximized contact with respect to p-type body region 130, which may be doped with a higher density than p-type body region 130.
According to embodiments, a predetermined area of p-type body region 130 between n-type source region 170 and n-type RESURF region 120 may be formed under gate dielectric layer 160 and may correspond to a channel area. In embodiments, a predetermined area between p-type body region 130 and n-type LVWELL 150 may be formed under gate dielectric layer 160 and/or isolation layer 140, and may correspond to a drift region.
According to embodiments, a LDMOS device may include n-type RESURF region 120, p-type first impurity region 122 and/or n-type second impurity region 124. In embodiments, other regions illustrated in
Embodiments relate to a method of manufacturing a LDMOS device. Example
Referring to
Referring to
According to embodiments, using substantially the same photoresist pattern 126 as an ion implantation mask, different ion energies may implanted to form n-type RESURF region 120, p-type first impurity region 122 and/or n-type second impurity region 124. In embodiments, RESURF region 120, first impurity region 122 and/or second impurity region 124 may be formed in various orders. In embodiments, photoresist pattern 126 may be substantially removed, for example in a ashing and/or strip process. In embodiments, ion implantation mask 126 may include a photoresist pattern. In embodiments, other kinds of materials, for example, a hard mask may be used as ion implantation mask.
Referring to
Referring to
According to embodiments, oxide layer 142, for example SiO2, may be formed on and/or over p-type body region 130, n-type RESURF region 120 and/or n-type HVWELL 100. In embodiments, nitride layers 144, for example Si3N4, may accumulate sequentially on and/or over oxide layer 142. In embodiments, oxide layer 142 may thermally grow to form isolation layer 140. In embodiments, nitride layer 144 may be substantially removed, for example using a phosphoric acid solution. In embodiments, isolation layer 140 may be formed in a LOCOS process. In embodiments, isolation layer 140 may be formed in a Shallow Trench Isolation (STI) process.
Referring to
According to embodiments, oxide layer 142 may accumulate sequentially. In embodiments, SiO2 and/or poly silicon may be patterned such that gate dielectric layer 160A and/or gate electrode 162 may be respectively formed, for example as illustrated in
Referring back to
According to embodiments, in a LDMOS device and a method of manufacturing a LDMOS device, an n-type RESURF region, p-type first impurity region and/or n-type second impurity region may be formed, for example sequentially, under an isolation layer and/or a gate pattern. In embodiments, a depletion layer may be distributed substantially uniformly on and/or over a surface of a RESURF region. In embodiments, a concentrated electric field of a surface region may be minimized. In embodiments, a surface breakdown in a gate edge of an isolation layer may be minimized, and/or a relatively high voltage breakdown may be maximized. In embodiments, first and/or second impurity regions, and/or a RESURF region, may be formed using a single mask, such that there may be a relatively simple manufacturing process.
It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.
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