A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second mos transistors. The first mos transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second mos transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first mos transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.
|
1. A sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising:
a first mos transistor supplying a predetermined voltage to the bit line and controlling a connection between the bit line and a sense node in response to a control voltage applied to a gate thereof; and
a second mos transistor having a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first mos transistor,
wherein the sense amplifier circuit has operating modes including a charge transfer mode and a charge distributing mode, and
wherein the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high level data and low level data read out from the memory cell can be obtained in a vicinity of a changing point between the charge transfer mode and the charge distributing mode within a range of a read voltage of the memory cell.
18. A circuit for amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising:
a first mos transistor supplying a predetermined voltage to the bit line and controlling a connection between the bit line and a sense node in response to a control voltage applied to a gate of the first mos transistor;
a second mos transistor including a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first mos transistor, a drain current of the second mos transistor being supplied to an input/output node;
a third mos transistor precharging the sense node and the bit line to a predetermined precharge voltage in response to a precharge signal applied to a gate of the third mos transistor;
a fourth mos transistor switching a connection between a drain of the second mos transistor and the input/output node in response to a first control signal applied to a gate of the fourth mos transistor; and
a fifth mos transistor switching a connection between the sense node and the input/output node in response to a second control signal applied to a gate of the fifth mos transistor,
wherein the sense amplifier circuit has operating modes including a charge transfer mode and a charge distributing mode, and
wherein the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high level data and low level data read out from the memory cell can be obtained in a vicinity of a changing point between the charge transfer mode and the charge distributing mode within a range of a read voltage of the memory cell.
2. The sense amplifier circuit according to
3. The sense amplifier circuit according to
a first sense amplifier including the first mos transistor and the second mos transistor; and
a second sense amplifier connected to an input/output node to which a drain current of the second mos transistor is supplied and including a signal voltage determination circuit determining a signal voltage level at the input/output node.
4. The sense amplifier circuit according to
a local sense amplifier including the first mos transistor and the second mos transistor and amplifying a signal transmitted through a local bit line as the bit line; and
a global sense amplifier connected to a global bit line which is selectively connected to a predetermined number of the local bit lines via the local sense amplifier, and including a signal voltage determination circuit determining a signal voltage level of the global bit line.
5. The sense amplifier circuit according to
6. The sense amplifier circuit according to
7. The sense amplifier circuit according to
8. The sense amplifier circuit according to
9. The sense amplifier circuit according to
a fourth mos transistor switching a connection between a drain of the second mos transistor and the input/output node in response to a first control signal applied to a gate of the fourth mos transistor; and
a fifth mos transistor switching a connection between the sense node and the input/output node in response to a second control signal applied to a gate of the fifth mos transistor.
10. The sense amplifier circuit according to
a fourth mos transistor switching a connection between a drain of the second mos transistor and the global bit line in response to a first control signal applied to a gate of the fourth mos transistor; and
a fifth mos transistor switching a connection between the sense node and the global bit line in response to a second control signal applied to a gate of the fifth mos transistor.
11. The sense amplifier circuit according to
12. The sense amplifier circuit according to
13. The sense amplifier circuit according to
14. The sense amplifier circuit according to
15. The sense amplifier circuit according to
17. The sense amplifier circuit according to
|
1. Field of the Invention
The present invention relates to a single-ended sense amplifier circuit amplifying a signal read out from a memory cell and transmitted through a bit line, and to a semiconductor memory device having the single-ended amplifier circuit.
2. Description of Related Art
As capacity of semiconductor memory devices such as a DRAM has recently become large, it has become difficult to obtain a sufficient capacitance value of a capacitor included in a memory cell for the purpose of miniaturization of the memory cell. A charge transfer type sense amplifier circuit is conventionally known as a sense amplifier circuit suitable for amplifying a minute signal voltage read out from the memory cell. For example, configurations of a variety of charge transfer type sense amplifiers are disclosed in the following Patent References 1 to 4.
In
However, when using the charge transfer type sense amplifier circuit of
The present invention seeks to solve one or more of the above problems and provides a sense amplifier circuit capable of obtaining a sufficient operating margin in a read operation by appropriately controlling amplifying operations in a charge transfer mode and in a charge distributing mode, in case of achieving low voltage operation in a semiconductor memory device employing memory cells each including a capacitor having a small capacitance.
An aspect of the invention is a sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising: a first MOS transistor supplying a predetermined voltage to the bit line and controlling connection between the bit line and a sense node in response to a control voltage applied to a gate thereof; and a second MOS transistor having a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first MOS transistor. In the sense amplifier of the aspect, the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node can be obtained in a vicinity of a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell when reading out high level data and low level data of the memory cell.
According to the sense amplifier circuit of the aspect, in a read operation of the memory cell, the first MOS transistor functions as a charge transfer gate in a state of supplying the predetermined voltage to the bit line in response to the control voltage, and the signal voltage is amplified by the second MOS transistor connected to the sense node based on a charge transfer mode or a charge distributing mode. At this point, when reading out high and low level data in the memory cell, a voltage relation is set so as to obtain a sufficient voltage difference between the high and low level data. Also, since the employment of the single-ended sense amplifier circuit allows the capacitance at the sense node to be reduced, a configuration advantageous for improving operating margin particularly in a low voltage operation can be achieved when memory cells having small capacitance are employed.
Particularly the sense amplifier circuit of the aspect is effectively applied to a hierarchical memory cell array. That is, in a configuration in which a predetermined number of local bit lines are selectively connected to a global bit line via the local sense amplifier, the circuit scale can be smaller by using the single-ended local sense amplifier without employing a differential configuration, and sufficient operating margin of the sense amplifier circuit can be obtained.
Further, particularly the sense amplifier circuit of the aspect is effectively combined with a compensated voltage generating circuit generating a compensated voltage of which fluctuation of a threshold voltage of the first or second MOS transistor is compensated. By supplying such a compensated voltage to the sense amplifier circuit, the above-mentioned operating margin can be further improved.
As described above, according to the invention, when the single-ended sense amplifier is employed in which amplifying operation is controlled based on the charge transfer mode and the charge distributing mode, since the capacitance at the sense node can be small, sufficient operating margin in a low voltage operation of about 1V can be obtained. Particularly, an advantageous configuration can be achieved when using memory cells having a small capacitance of under about 5 fF.
Further, in a semiconductor memory device having a hierarchical bit line structure and a hierarchical sense amplifier circuit, the capacitance at each local bit line can be set to a small value, and therefore excellent operating margin can be obtained in the large capacity semiconductor memory device.
Furthermore, fluctuation of the threshold voltage of the MOS transistor due to manufacturing process and temperature can be appropriately compensated by using the compensated voltage generating circuit. Therefore, the operating margin for sensing can be further improved, thereby improving reliability of the operation of the sense amplifier circuit. Or, since the variation permissible range in the chip can be expanded, when large number of sense amplifier circuits can be implemented in a large capacity DRAM using memory cells having small capacitance, it is possible to improve production yield and to reduce manufacturing cost.
The above featured and advantages of the invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. In the following, three embodiments will be described, in which the invention is applied to a semiconductor memory device having a sense amplifier circuit.
[Basic Principle]
Basic operating principle of a sense amplifier circuit of the embodiments will be described with reference to
The selection transistor Q0 has a source connected to a bit line BL, and a gate connected to a word line WL. Further, the capacitor Cs is connected between the drain of the selection transistor Q0 and a ground potential. The MOS transistor Qg functioning as a charge transfer gate is connected between the bit line BL and a sense node Ns. The MOS transistor Qp for supplying the bit line potential is connected between a power supply voltage VDD and the sense node Ns. A control voltage Vg is applied to the gate of the MOS transistor Qg, and a control signal SET is applied to the gate of the MOS transistor Qp. In
The sense node Ns is set to the power supply voltage VDD by the operation of the MOS transistor Qp for supplying the bit line potential before a read operation of the memory cell MC. At this point, the voltage Vb (the predetermined voltage of the invention) satisfying Vb=Vg−Vt1 based on the control voltage Vg and a threshold voltage Vt1 of the MOS transistor Qg is supplied to the bit line BL via the MOS transistor Qg.
Thereafter, the MOS transistor Qp is turned off, and subsequently the word line WL is driven so that the selection transistor Q0 is turned on. Thereby, the sensing operation of the sense amplifier circuit is started. When a voltage at a charge accumulation node N0 of the memory cell MC is assumed to be Vs, there can be following three operations in accordance with relations between values of Vs, Vb and VDD.
(1) The MOS transistor Qg is maintained off.
(2) Electric charge is transferred via the MOS transistor Qg in the above-mentioned charge transfer mode.
(3) Electric charge is transferred via the MOS transistor Qg in the above-mentioned charge distributing mode.
Here, the voltage Vb corresponding to a boundary (changing point) between the operation (2) and the operation (3) is defined as Vc. By using this voltage Vc, the voltage Va at the sense node Ns after the above operation is completed can be represented as following formulas 1, 2 and 3 respectively corresponding to the operations (1), (2) and (3).
Vb≦Vs:Va=VDD (formula 1)
Vs<Vb≦Vc:Va=VDD+(Cs/Ca)Vs−(Cs/Ca)Vb (formula 2)
Vc<Vb:Va=(CsVs+CaVDD)/(Cs+Cb+Ca)+(Cb/(Cs+Cb+Ca))Vb (formula 3)
Here, the voltage Vc is calculated according to a following equation.
Vc=((Cs+Cb)CaVDD)+(Cs+Cb)CsVs)/(Cs(Cs+Cb+Ca)+CbCa)
For example, the conventional sense amplifier shown in
A first embodiment of the invention will be described below. A feature of the first embodiment is that a single-ended sense amplifier circuit controlled in the charge transfer mode and the charge distributing mode is employed.
The memory cell MC is a 1T1C type DRAM memory cell composed of an N-type MOS selection transistor Q0, and a capacitor Cs storing information as electric charge. The selection transistor Q0 has a source connected to the bit line BL and a gate connected to the word line WL. The capacitor Cs is connected between the drain of the selection transistor Q0 and a cell plate voltage VPLT. Although
The preamplifier 10 includes five N-type MOS transistors Q1, Q2, Q3, Q4 and Q5. The MOS transistor Q1 (the first MOS transistor of the invention) functioning as the charge transfer gate is connected between the bit line BL and the sense node Ns of the side of the preamplifier 10, and the control voltage Vg is applied to its gate. The MOS transistor Q2 (the second MOS transistor of the invention) functioning as an amplifying element has a gate connected to the sense node Ns, and senses and amplifies the signal transmitted from the bit line BL via the MOS transistor Q1 so as to convert the signal into a drain current. The drain current flows from an input/output node N1 of the side of the preamplifier 10 to a ground via the MOS transistors Q4 and Q2.
A precharge signal PC is applied to the gate of the MOS transistor Q3 functioning as a transistor for precharging the bit line BL, and the MOS transistor Q3 precharges the sense node Ns to a ground potential when the precharge signal PC is high. When the sense node Ns is precharged, the bit line BL is precharged to the ground potential via the MOS transistor Q1. The MOS transistor Q4 for read control switches connection between the input/output node N1 and the MOS transistor Q2 in response to a control signal RT applied to the gate of the MOS transistor Q4. The MOS transistor Q5 for write control switches connection between the input/output output node N1 and the sense node Ns in response to a control signal WT applied to the gate of the MOS transistor Q5.
Since the preamplifier 10 has a simple configuration including five MOS transistor as shown in
A signal voltage decision latch 11a includes MOS transistors Q13, Q14, Q15 and Q16, and determines a binary level of a signal transmitted from the preamplifier 10 to the input/output node N1 so as to latch the signal. In the signal voltage decision latch 11a, a pair of MOS transistors Q13 and Q14 having gates connected to the node N2 forms a sensing inverter having relatively large driving force. Similarly, a pair of MOS transistors Q15 and Q16 having gates connected to the node N3 forms a latching inverter having relatively small driving force.
Two MOS transistors Q17 and Q18 are connected in series as a read circuit between the read bus/RDL and the ground, and an output signal SD (node N3) of the signal voltage decision latch 11a is inputted to the gate of the MOS transistor Q17. Two MOS transistors Q19 and Q20 are connected in series as a write circuit between the write bus/WDL and the node N2, and a write enable signal WE is inputted to the gate of the MOS transistor Q19. A sense amplifier selection signal YS is commonly inputted to the gates of the MOS transistors Q18 and Q20.
In a read operation, the latch control signal LTC becomes high and the sense amplifier selection signal YS becomes high, and the output signal SD of the sensing inverter is outputted to the read bus/RDL. At this point, the output signal SD appearing at the node N3 has a voltage obtained by inverting the logic value at the input/output node N1. In a rewrite operation performed for avoiding destruction of data of memory cells MC after the read operation, the latch control signal LTC becomes low, the control signal RES becomes high, and the output signal SD is outputted to the input/output node N1 via the NMOS transistor Q12.
Meanwhile, in a write operation, the sense amplifier selection signal YS becomes high, the write enable signal WE becomes high, and write data is inputted through the write bus/WDL. The write data is inverted by the sensing inverter, and outputted to the input/output node N1 via the MOS transistor Q12.
Next, an amplifying operation of the sense amplifier circuit of the first embodiment will be descried using
In
Each of
Here,
In the conventional sense amplifier circuit, positions of the changing points P and P′ are shifted to right in a case of the power supply voltage VDD=3V/2V, and thus it is understood that the charge transfer mode is dominant. Here, the difference between read signal voltages is decreased in the case of Cs=2 fF in
Next, a second embodiment of the invention will be described. In the second embodiment, a hierarchical memory cell array is formed, and a charge transfer/distributing type single-ended sense amplifier is applied to a DRAM having hierarchical bit lines and hierarchical sense amplifier circuits.
The memory cell MC has the same structure as that in
Further, for example, eight local sense amplifiers 20 are connected to one global bit line GBL. In this case, 512 memory cells MC in total can be selectively connected to one global bit line GBL. A parasitic capacitance Cgb is formed at each global bit line GBL. There are provided a MOS transistor Q7 switching connection to one global bit line GBL and a MOS transistor Q8 switching connection to the other global bit line GBL, on both sides of the global sense amplifier 21. Then, the global sense amplifier 21 can be selectively connected to either of the global bit lines GBL on both sides by using a control signal SHL applied to the gate of the MOS transistor Q7 and a control signal SHR applied to the gate of the MOS transistor Q8.
Each of
Next, a read operation in the DRAM of the second embodiment will be described with reference to
As shown in
In the precharge cancellation term T1, the precharge signal PC is controlled to be low so that the MOS transistor Q3 is turned off, and the local bit line LBL and the sense node Ns are precharged to the ground potential VSS and become floating. Further, the control signals SHR and CTR are both controlled to be low, the non-selected global bit lines GBL is disconnected from the global sense amplifier 21, and the non-selected local bit line LBL is disconnected from the local sense amplifier 20. Here, the control signal CTL is set to a voltage value of the above control voltage Vg. In addition, the non-selected local sense amplifier 20 is maintained in a state where the precharge signal PC and the control signals CTL and CTR are controlled to be high and the control signals RT and WT are controlled to be low.
In a local bit line voltage set term T2, the control signal WT is controlled to be the positive voltage VPP and is maintained in this state for a given period. The MOS transistor Q5 is turned on by the control signal WT controlled to be at the positive voltage VPP, and the sense node Ns in the local sense amplifier 20 is driven to the power supply voltage VDD through the global bit line GBL. As a result, the local bit line LBL is driven to the voltage Vg−Vt1 via the MOS transistor Q1. Thereafter, the inverted precharge signal/PC is controlled to be high, and the global bit line GBL is maintained in a state of being precharged to the power supply voltage VDD.
In a cell selection term T3, the word line WL is driven from the negative voltage VKK to the positive voltage VPP. Thereby, a signal voltage of the memory cell MC maintaining high level is read out to the local bit line LBL. At this point, since the voltage Vb of the local bit line LBL is higher than the voltage Vg−Vt1, the MOS transistor Q1 is maintained off. Thus, the sense node Ns is maintained at the power supply voltage VDD.
In a sense term T4, the control signal RT is controlled to be high and is maintained in this state for a given period. At this point, since the potential of the sense node Ns is higher than the upper limit of the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2, a large drain current flows through the MOS transistor Q2. Accordingly, electric charge which is charged in the parasitic capacitance Cgb at the global bit line GBL is extracted in a short time by the MOS transistor Q2, and thus the global bit line GBL is rapidly discharged so that its potential changes from the power supply voltage VDD to the ground potential VSS. The potential of the global bit line GBL reaches the ground potential VSS at the end of the sense term T4 and is inverted by the signal voltage decision latch 21a of the global sense amplifier 21 so that the output signal SD changes to the power supply voltage VDD. Thereafter, the latch control signal LTC is controlled to be low, and the sense term T4 is finished.
In addition, the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2 is determined depending on a range in which an entire variation distributed, for example, depending on a minute variation in dimension when forming transistors, variation in thickness of a gate insulating film, a random fluctuation in channel impurity distribution, or the temperature.
Subsequently, in a restore term T5, the control signal RES is controlled to be the positive voltage VPP, the output signal SD of the global sense amplifier 21 is outputted to the global bit line GBL via the MOS transistor Q12, and the potential of the global bit line GBL changes to the power supply voltage VDD. Subsequently, the control signal WT is again controlled to be the positive voltage VPP, and the global bit line GBL is connected to the sense node Ns via the MOS transistor Q5. Then, the control signal CTL maintained at the control voltage Vg is controlled to be the positive voltage VPP at the approximately same timing, and the local bit line LBL is connected to the sense node Ns via the MOS transistor Q1. Thereby, high level data is rewritten into the memory cell MC.
In a precharge term T6, the word line WL is returned to the negative voltage VKK. Subsequently, the control signals WT and RES are controlled to be low, and the latch control signal LTC is controlled to be high. Subsequently, the precharge signal PC is controlled to be high, the inverted precharge signal/PC is controlled to be low, the local bit line LBL and the sense node Ns are both precharged to the ground potential VSS, and the global bit line GBL is precharged to the power supply voltage VDD. Thereby, the output signal SD of the signal voltage decision latch 21a changes to low. Finally, the control signals SHR and CTR are controlled to be the positive voltage VPP, and the read operation is completed.
Next, as shown in
In the sense term T4, the control signal RT is controlled to be high and is maintained in this state for a given period. At this point, since the potential of the sense node Ns is lower than the lower limit of the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2, the drain current does not flow through the MOS transistor Q2. Thus, the potential of the global bit line GBL is maintained at the power supply voltage VDD. The potential of the global bit line GBL reaches the power supply voltage VDD at the end of the sense term T4, the potential is inverted by the signal voltage decision latch 21a of the global sense amplifier 21, and the output signal SD is maintained at the ground potential VSS. Thereafter, the latch control signal LTC is controlled to be low, and the sense term T4 is finished.
In the restore term T5, the control signal RES is controlled to be the positive voltage VPP, the output signal SD of the global sense amplifier 21 is outputted to the global bit line GBL via the MOS transistor Q12, and the potential of the global bit line GBL changes to the ground potential VSS. Subsequently, the control signal WT is again controlled to be the positive voltage VPP, and the global bit line GBL is connected to the sense node Ns via the MOS transistor Q5. Then, the control signal CTL maintained at the control voltage Vg is controlled to be the positive voltage VPP at the approximately same timing, and the local bit line LBL is connected to the sense node Ns via the MOS transistor Q1. Thereby, low level data is rewritten into the memory cell MC.
In the precharge term T6, the word line WL, the control signals WT and RES, the latch control signal LTC, the precharge signal PC, and the inverted precharge signal/PC are controlled in the same manner as in
Here, the operation waveforms shown in
Next, a modification of the second embodiment will be described.
Next, a third embodiment of the invention will be described. In a DRAM of the third embodiment, hierarchical bit lines and sense amplifier circuits are configured in the same manner as the second embodiment, part of which differs from the second embodiment. Although the circuit configuration in
In
The control voltage Vg outputted from the control voltage generating circuit of
Next,
The first operational amplifier 48 inverts and amplifies the monitor signal Sm of the threshold voltage monitor part 30, and outputs an inverted monitor signal −Sm. The second operational amplifier 49 receives the inverted monitor signal −Sm at a minus-side input terminal and receives the correction amount Vm smoothed through the low pass filter 47 composed of a resistor and a capacitor at a plus-side input terminal as s shifted voltage. When resistors R1 and R2 are arranged as shown in
As described above, the fluctuation of the threshold voltage Vt2 of the MOS transistor Q2 due to manufacturing process and temperature can be reflected to each power supply based on the operation of the threshold voltage monitor part 30. Thus, respective values of the voltages VSNH and VSNL, the cell plate voltage VPLT and the voltage Vb can be appropriately set so as to compensate the fluctuation of the threshold voltage Vt2 of the MOS transistor Q2. For example, the voltage VSNH used to precharge the sense node Ns in the local sense amplifier 20 can be controlled to be increased following the increase of the threshold voltage Vt2 of the MOS transistor Q2, and reversely decreased following the decrease of the threshold voltage Vt2. Further, the voltage for writing data of high and low in the memory cell MC can be similarly controlled to be increased or decreased following a change in the threshold voltage Vt2 of the MOS transistor Q2. Furthermore, as to the control voltage Vb or as to the control voltage Vg generated by using the voltage Vb as a criterion, it is possible to control the voltage to be similarly increased or decreased following a change in threshold voltage Vt2 of the MOS transistor Q2. As a result, since each voltage in the sensing part changes in the same manner as the change in the threshold voltage Vt2 of the MOS transistor Q2, the actual variation can be reduced relative to the above-mentioned variation permissible range Rvt of the threshold voltage, thereby further improving the operating margin of the sense amplifier circuit.
In the foregoing, although the contents of the invention have been specifically described based on the embodiments, the invention is not limited the above-described embodiments, and can variously be modified without departing the essentials of the invention. For example, the above embodiments have described the preamplifier 10/the local sense amplifier 20 (the sense amplifier circuit) including five MOS transistors. However, the invention can be widely applied to various sense amplifier circuits having a first MOS transistor functioning as the charge transfer gate and a second MOS transistor amplifying the signal voltage via the first MOS transistor without restriction for other components.
Patent | Priority | Assignee | Title |
8310887, | Mar 17 2008 | Longitude Licensing Limited | Semiconductor device having single-ended sensing amplifier |
8588019, | Nov 05 2010 | Longitude Licensing Limited | Semiconductor device having current change memory cell |
8976611, | Mar 15 2013 | Taiwan Semiconductor Manufacturing Company, Ltd | Asymmetric sensing amplifier, memory device and designing method |
8976612, | Sep 16 2009 | Longitude Licensing Limited | Sense amplifier circuit and semiconductor device |
8982652, | Sep 16 2009 | Longitude Licensing Limited | Sense amplifier circuit and semiconductor device |
8988958, | Sep 16 2009 | Longitude Licensing Limited | Sense amplifier circuit and semiconductor device |
9177619, | Dec 20 2011 | Longitude Licensing Limited | Semiconductor device having hierarchical bit line structure |
9269420, | Jun 27 2013 | Samsung Electronics Co., Ltd. | Semiconductor memory device and sense amplifier control method thereof |
Patent | Priority | Assignee | Title |
6154402, | Sep 07 1998 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
6314028, | Jul 07 2000 | Renesas Electronics Corporation | Semiconductor memory device capable of stable sensing operation |
20020060924, | |||
20090175066, | |||
JP1116384, | |||
JP2000195268, | |||
JP2002157885, | |||
JP200773121, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 20 2009 | KAJIGAYA, KAZUHIKO | Elpida Memory, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023174 | /0422 | |
Aug 26 2009 | Elpida Memory, Inc. | (assignment on the face of the patent) | / | |||
Jul 26 2013 | PS4 LUXCO S A R L | ELPIDA MEMORY INC | SECURITY AGREEMENT | 032414 | /0261 | |
Jul 26 2013 | Elpida Memory, Inc | PS4 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032899 | /0588 | |
Aug 29 2013 | PS4 LUXCO S A R L | PS5 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 039818 | /0506 | |
Nov 12 2013 | PS5 LUXCO S A R L | LONGITUDE SEMICONDUCTOR S A R L | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 039793 | /0880 | |
Jul 31 2018 | LONGITUDE SEMICONDUCTOR S A R L | Longitude Licensing Limited | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 046865 | /0667 |
Date | Maintenance Fee Events |
Jul 10 2015 | REM: Maintenance Fee Reminder Mailed. |
Sep 17 2015 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Sep 17 2015 | M1554: Surcharge for Late Payment, Large Entity. |
Oct 22 2015 | ASPN: Payor Number Assigned. |
May 21 2019 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
May 23 2023 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Nov 29 2014 | 4 years fee payment window open |
May 29 2015 | 6 months grace period start (w surcharge) |
Nov 29 2015 | patent expiry (for year 4) |
Nov 29 2017 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 29 2018 | 8 years fee payment window open |
May 29 2019 | 6 months grace period start (w surcharge) |
Nov 29 2019 | patent expiry (for year 8) |
Nov 29 2021 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 29 2022 | 12 years fee payment window open |
May 29 2023 | 6 months grace period start (w surcharge) |
Nov 29 2023 | patent expiry (for year 12) |
Nov 29 2025 | 2 years to revive unintentionally abandoned end. (for year 12) |