A demultiplexer, a light emitting display using the same, and a display panel thereof. The light emitting display includes: an image signal line for supplying a data signal for displaying an image through a plurality of first signal lines; a display area including a plurality of data lines for transmitting the data signal, a plurality of scan lines for transmitting a selection signal, and a plurality of pixels coupled to the data lines and the scan lines; a data driver for sequentially outputting a plurality of first control signals; a scan driver for sequentially applying the selection signal to the scan lines; and a demultiplexer including a plurality of switches for transmitting the data signal to at least two data lines in response to the first control signals. One of the first control signals is transmitted in at least two directions to switches in at least one of the switching units.
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9. A demultiplexer for demultiplexing a data signal which is input through a plurality of first signal lines and for applying the data signal to a plurality of data lines in a display area comprising a plurality of pixel circuits for displaying an image corresponding to the data signal, comprising:
a plurality of second signal lines for transmitting a first control signal which is sequentially input;
a plurality of switching units for transmitting the data signal to the data lines in response to the first control signal; and
at least two fourth signal lines in parallel with and coupled to a corresponding one of the second signal lines,
wherein at least one of the switching units is coupled between the first signal lines and the data lines, and includes a plurality of switching transistors sharing a gate electrode that forms a third signal line, each of the plurality of switching transistors respectively has a source terminal and a drain terminal, and the corresponding one of the second signal lines is coupled to the third signal line so that the switching transistors in terms of their physical arrangements are symmetrically formed with respect to the corresponding one of the second signal lines,
wherein one of the at least two fourth signal lines is formed to extend in an area between two nearest ones of the plurality of switching transistors, and the one of the at least two fourth signal lines is spaced from the two nearest ones of the plurality of switching transistors, and the at least two fourth signal lines are coupled to the third signal line that is commonly connected to all of the plurality of switching transistors and that is formed to extend in a direction perpendicular to the at least two fourth signal lines and crosses the plurality of switching transistors such that all of the respective source terminals of the plurality of switching transistors are formed on one side of the third signal line and all of the respective drain terminals of the plurality of switching transistors are formed on an opposite side of the third signal line from the respective source terminals, and
wherein each of the at least two fourth signal lines has a proximate end and a distal end, the respective proximate ends of the at least two fourth signal lines are coupled to the third signal line, and the respective distal ends of the at least two fourth signal lines are coupled to a fifth signal line that extends in parallel with the third signal line and is coupled to the corresponding one of the second signal lines.
6. A display panel comprising:
a plurality of first signal lines for supplying a data signal to display an image;
a display area comprising a plurality of pixel circuits for displaying the image corresponding to the data signal and a plurality of data lines for transmitting the data signal to the pixel circuits;
a data driver for sequentially outputting a plurality of first control signals;
a plurality of switching units for sequentially transmitting the data signal to the data lines in response to the first control signals, wherein at least one of the switching units comprises a plurality of switching transistors that are respectively coupled between the plurality of first signal lines and at least two data lines among the plurality of data lines, each of the plurality of switching transistors respectively has a source terminal and a drain terminal, and gate electrodes of the switching transistors form a third signal line;
a plurality of second signal lines for transmitting the first control signals to the switching units; and
at least two fourth signal lines formed in parallel with and coupled to a corresponding one of the second signal lines,
wherein the corresponding one of the second signal lines is coupled to the third signal line so that lengths for transmitting the corresponding one of the first control signals to at least two switching transistors among the plurality of switching transistors in terms of their physical arrangements are substantially the same as each other,
wherein one of the at least two fourth signal lines is formed to extend in an area between two nearest ones of the plurality of switching transistors, and the one of the at least two fourth signal lines is spaced from the two nearest ones of the plurality of switching transistors, and the at least two fourth signal lines are coupled to the third signal line that is commonly connected to all of the plurality of switching transistors and that is formed to extend in a direction perpendicular to the at least two fourth signal lines and crosses the plurality of switching transistors such that all of the respective source terminals of the plurality of switching transistors are formed on one side of the third signal line and all of the respective drain terminals of the plurality of switching transistors are formed on an opposite side of the third signal line from the respective source terminals, and
wherein each of the at least two fourth signal lines has a proximate end and a distal end, the respective proximate ends of the at least two fourth signal lines are coupled to the third signal line, and the respective distal ends of the at least two fourth signal lines are coupled to a fifth signal line that extends in parallel with the third signal line and is coupled to the corresponding one of the second signal lines.
1. A light emitting display comprising:
a plurality of first signal lines for supplying a data signal to display an image;
a display area comprising a plurality of data lines for transmitting the data signal, a plurality of scan lines for transmitting a selection signal, and a plurality of pixels coupled to the data lines and the scan lines;
a data driver for sequentially outputting a plurality of first control signals;
a scan driver for sequentially applying the selection signal to the scan lines;
a demultiplexer comprising a plurality of switching units for respectively transmitting the data signal to at least two data lines among the plurality of data lines in response to the first control signals;
the demultiplexer further comprising:
a plurality of second signal lines for applying the first control signals from the data driver to the switching units; and
at least two third signal lines formed in parallel with and coupled to a corresponding one of the second signal lines,
wherein at least one of the switching units comprises a plurality of switches for transmitting the data signal to the at least two data lines in response to a corresponding one of the first control signals, each of the plurality of switches respectively has a source terminal and a drain terminal, and the plurality of switches are respectively coupled between the plurality of first signal lines and the at least two data lines,
wherein the corresponding one of the first control signals is applied to the at least one of the switching units at a predetermined point, such that the corresponding one of the first control signals is transmitted to the switches in at least two directions with respect to the predetermined point,
wherein the plurality of switches in the at least one of the switching units in terms of their physical arrangements are symmetrically arranged with respect to the corresponding one of the second signal lines,
wherein one of the at least two third signal lines is formed to extend in an area between two nearest ones of the plurality of switches, and the one of the at least two third signal lines is spaced from the two nearest ones of the plurality of switches, and the at least two third signal lines are coupled to the plurality of switches via a fourth signal line that is commonly connected to all of the plurality of switches and that is formed to extend in a direction perpendicular to the at least two third signal lines and crosses the plurality of switches such that all of the respective source terminals of the plurality of switches are formed on one side of the fourth signal line and all of the respective drain terminals of the plurality of switches are formed on an opposite side of the fourth signal line from the respective source terminals, and
wherein each of the at least two third signal lines has a proximate end and a distal end, the respective proximate ends of the at least two third signal lines are coupled to the fourth signal line, and the respective distal ends of the at least two third signal lines are coupled to a fifth signal line that extends in parallel with the fourth signal line and is coupled to the corresponding one of the second signal lines.
2. The light emitting display of
3. The light emitting display of
4. The light emitting display of
5. The light emitting display of
a driving transistor comprising first, second and third electrodes, the driving transistor for outputting a current corresponding to a voltage applied between the first and second electrodes at the third electrode;
a capacitor coupled between the first and second electrodes of the driving transistor; and
a switching transistor for transmitting the data signal to the capacitor in response to the selection signal.
7. The display panel of
8. The display panel of
10. The demultiplexer of
11. The light emitting display of
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This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0050608 filed on Jun. 30, 2004 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a demultiplexer, and a light emitting display using the demultiplexer and a display panel thereof. More specifically, the present invention relates to an organic light emitting diode (OLED) display.
2. Discussion of the Related Art
Generally, OLED displays emit light by electrically exciting an organic compound. Such an OLED display includes N×M organic light emitting cells arranged in the form of a matrix, and displays an image by driving the organic light emitting cells, using voltage or current. Such organic light emitting cells are also called “OLEDs” because they have diode characteristics. As shown in
For driving methods for such an OLED display panel, there are a passive matrix type driving method and an active matrix type driving method using thin film transistors (TFTs). In accordance with the passive matrix type driving method, anodes and cathodes are arranged to be orthogonal to each other so that a desired line to be driven is selected. In accordance with the active matrix type driving method, thin film transistors are coupled to respective indium tin oxide (ITO) pixel electrodes in an OLED display panel so that the OLED display panel is driven by a voltage maintained by the capacitance of a capacitor coupled to the gate of each thin film transistor.
As shown in
The scan driver 20 sequentially transmits a selection signal to a plurality of scan lines S1 to Sn, and the data driver 30 sequentially outputs control signals X1 to Xm for turning on the switches SW1 to SWm.
The switches SW1 to SWm form a demultiplexer for demultiplexing an image signal transmitted from an image signal line and for transmitting the image signal to data lines D1 to Dm, and sequentially transmit the image signal to the data lines D1 to Dm in response to the control signals X1 to Xm.
In the conventional OLED display, the data driver 30 is required to have output terminals corresponding to the data lines, and to sequentially apply the image signal to the respective data lines D1 to Dm for a horizontal period. Therefore, it is limited to programming the image signal to one data line at a time.
To provide more time for programming each data line, multiple data lines should be driven at the same time by dividing and transmitting the image signal to a plurality of signal lines, and turning on the plurality of switches at the same time when a signal (e.g., signal X1) is applied by a data driver.
However, when one signal output from the data driver 30 is transmitted to a plurality of switches, a time for a control signal X being transmitted to the plurality of switches has a variation. Accordingly, an image signal is not correctly transmitted to the data lines D1 to Dm.
In one exemplary embodiment of the present invention, a method for reducing a variation in transmission time of a control signal of a data driver, and accurately applying an image signal to a data line, is provided.
Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description.
In an exemplary embodiment according to the present invention, a light emitting display is disclosed. The light emitting display includes: an image signal line for supplying a data signal for displaying an image through a plurality of first signal lines; a display area including a plurality of data lines for transmitting the data signal, a plurality of scan lines for transmitting a selection signal, and a plurality of pixels coupled to the data lines and the scan lines; a data driver for sequentially outputting a plurality of first control signals; a scan driver for applying the selection signal to the scan lines; and a demultiplexer including a plurality of switching units for respectively transmitting the data signal to at least two data lines among the plurality of data lines in response to the first control signals. At least one of the switching units includes a plurality of switches for transmitting the data signal to the at least two data lines in response to a corresponding one of the first control signals. The plurality of switches are respectively coupled between the plurality of first signal lines and the at least two data lines. The corresponding one of the first control signals is applied to the at least one of the switching units at a predetermined point, such that the corresponding one of the first control signals is transmitted to the switches in at least two directions with respect to the predetermined point.
In another exemplary embodiment according to the present invention, a display panel is provided. The display panel includes: an image signal line for supplying a data signal for displaying an image through a plurality of first signal lines; a display area including a plurality of pixel circuits for displaying the image corresponding to the data signal and a plurality of data lines for transmitting the data signal to the pixel circuits; a data driver for sequentially outputting a plurality of first control signals; a plurality of switching units for sequentially transmitting the data signal to the data lines in response to the first control signals; and a plurality of second signal lines for transmitting the first control signals to the switching units. At least one of the switching units includes a plurality of switching transistors that are respectively coupled between the plurality of first signal lines and at least two data lines among the plurality of data lines, and sharing a gate electrode that forms a third signal line. A corresponding one of the second signal lines is coupled to the third signal line so that lengths for transmitting the corresponding one of the first control signals to at least two switching transistors among the plurality of switching transistors are substantially the same as each other.
In yet another exemplary embodiment according to the present invention, a demultiplexer for demultiplexing a data signal which is input through a plurality of first signal lines and for applying the data signal to a plurality of data lines, is provided. The demultiplexer includes a plurality of second signal lines for transmitting a first control signal which is sequentially input, and a plurality of switching units for transmitting the data signal to the data lines in response to the first control signal. At least one of the switching units is coupled between the first signal lines and the data lines, and includes a plurality of switching transistors sharing a gate electrode that forms a third signal line. A corresponding one of the second signal lines is coupled to the third signal line so that the switching transistors are symmetrically formed with respect to the corresponding one of the second signal lines.
The accompanying drawings, together with the specification, illustrate certain exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.
In the following detailed description, exemplary embodiments of the present invention are shown and described by way of illustration. As those skilled in the art would recognize, the described exemplary embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, rather than restrictive.
There may be parts shown in the drawings, or parts not shown in the drawings, that are not discussed in the specification as they are not essential to a complete understanding of the invention. Like reference numerals designate like elements.
Exemplary embodiments of the present invention will now be described in detail with reference to the drawings.
As shown in
The display panel 100 includes a plurality of data lines D1 to Dm, a plurality of scan line S1 to Sn, and a plurality of pixel circuits 102 coupled to the data lines and the scan lines. The plurality of data lines D1 to Dm are arranged in a column direction, and each data line is used to transmit a data current for displaying an image to corresponding pixel circuits 102. The plurality of scan lines S1 to Sn are arranged in a row direction, and each scan line is used to transmit a selection signal to corresponding pixel circuits 102. Each pixel is formed in an area defined by a neighboring data line and two neighboring scan lines.
The scan driver 200 sequentially applies the selection signal to the selection scan lines S1 to Sn, and the data driver 300 sequentially outputs the control signals X1 to Xi. The demultiplexer 400 applies an image signal (red, green, and blue data) to the plurality of data lines D1 to Dm in response to the control signals X1 to Xi from the data driver 300.
In the exemplary embodiment of the present invention, the image signal includes red, green, blue data, namely, R DATA, G DATA, and B DATA. The respective data is input through six respective channels (e.g., parallel data bus lines) in
The demultiplexer 400 transmits red, green, and blue data input through the six respective channels to eighteen data lines in response to one control signal (i.e., one of the control signals X1 to Xi).
The scan driver 200, the data driver 300, and/or the multiplexer 400 may be coupled to the display panel 100, or formed, in the form of a chip, on a tape carried package (TCP). They may also be formed, in the form of a chip, on a flexible printed circuit (FPC) and a film which are coupled to the display panel. Otherwise, the scan driver 200, the data driver 300, and/or the multiplexer 400 may be directly formed on the glass substrate of the display panel 100 so that the selection/emission driver 200 and/or the data driver 300 may be substituted for driving circuits respectively formed on the same layers as those of the selection signal lines, data lines, and transistors.
The pixel circuit includes a driving transistor M1, a switching transistor M2, a capacitor Cst, and an OLED.
The driving transistor M1 is coupled between a power source having a voltage of VDD and the OLED, and transmits a current corresponding to a voltage applied to its gate and source to the OLED. By way of example, when a metal-oxide-semiconductor (MOS) transistor having a p-type channel is provided as the driving transistor M1, a source of the driving transistor M1 is coupled to the power source of the voltage VDD, and a drain of the driving transistor M1 is coupled to an anode of the OLED. According to the exemplary embodiment of the present invention, a cathode of the OLED is coupled to a power source of the voltage VSS, and the voltage VSS is lower than the voltage VDD (e.g., the voltage VSS may be a negative voltage or a ground voltage).
The capacitor Cst is coupled between the gate and the source of the driving transistor M1, and the switching transistor M2 is coupled between the data line Dm and the gate of the driving transistor M1.
An operation of the pixel shown in
where VTH denotes a threshold voltage of the transistor M1, and β denotes a constant.
As shown in Equation 1, the current of IOLED corresponding to the data voltage VDATA is supplied to the OLED in the pixel circuit shown in
While the exemplary embodiment of the present invention has been described above in reference to a pixel circuit formed on the display panel 100, pixel circuits according to various voltage programming methods or current programming methods may be formed on the display panel 100 according to exemplary embodiments.
As shown in
The demultiplexer 400 includes a plurality of switching units 410 for transmitting the image signals to the data lines in response to the output signals X1 to Xi, respectively, of the buffers BUF1 to BUFi.
When the image signals include the red, green, and blue data, and each data is input through the six channels, a first switching unit 410 receives eighteen image signals and transmits them to the data lines D1 to D18 in response to the output signal X1 of the buffer BUFi.
In the like manner, a second switching unit transmits the eighteen image signals to the data lines D19 to D36 in response to the output signal X2 of the buffer BUF2, and an ith switching unit transmits the eighteen image signals to the data lines D(m-17) to Dm in response to the output signal Xi of the buffer BUFi.
A demultiplexer according to the first exemplary embodiment of the present invention will now be described with reference to
As shown in
Eighteen signal lines are formed in a column direction and spaced apart from each other in a row direction in order to transmit the image signals, and switches SW1 to SW18 are coupled between the respective signal lines and data lines D1 to D18.
The eighteen switches SW1 to SW18 included in the first switching unit 410 are concurrently turned on by the output signal X1 of the buffer BUF1, and transmit data from the respective signal lines to the data lines D1 to D18. In other words, image data signals R001, G001, B001 through R006, G006, B006 are respectively applied to the data lines D1 to D18 through the switches SW1 to SW18.
According to the first exemplary embodiment of the present invention, as shown in
That is, when one control signal X1 is applied to the plurality of switches SW1 to SW18, a resistance-capacitance RC delay is generated by parasitic resistance and capacitance in the signal line for transmitting the control signal X1, and the time to apply the signal X1 to the respective switches SW1 to SW18 has a variation.
Accordingly, when the signal X1 is transmitted from one side of the switches SW1 to SW18 in a direction, a time for applying the control signal X1 to a switch which is arranged far from the output terminal of the buffer BUF is delayed, a variation is generated between a switch which is near the output terminal of the buffer and a switch which is far from the output terminal, and therefore an error of the image signal applied to the data line is increased.
Accordingly, the output terminal of the buffer BUF1 is to be provided at a center of the switching unit 410, and therefore the variation in time to apply the output signal X1 of the buffer BUF1 to the switches SW1 to SW18 may be reduced.
As show in
The respectively control signals X1 to Xi output from the buffer BUF1 to BUFi are bi-directionally transmitted from the center of the respective switching units, and the switches transmit the image signals to the data lines D1 to Dm in response to the control signals X1 to Xi. As shown in
Accordingly, the variation in time to apply the respective output signals X1 to Xi of the buffer BUF1 to BUFi to the switches SW1 to SW18 in the switching units may be reduced, and the more exact image signals can be transmitted to the data lines. While the switches are depicted as PMOS transistors in
The switching unit 410′ according to the second exemplary embodiment of the present invention is substantially the same as the switching unit 410 according to the first exemplary embodiment of the present invention except that the output signal X1 of the buffer BUF1 transmitted through a signal line 42 is transmitted to a gate electrode line 44 of the switches through three signal lines 43a to 43c.
Each of the eighteen switches in the switching unit is formed as a p-channel transistor. The gate electrodes of the eighteen transistors are formed by the gate electrode line 44, and a signal line 43b is coupled to a center of the gate electrode line 44. Signal lines 43a and 43c are symmetrically formed with respect to the signal line 43b.
A source electrode 45 of the transistor is coupled to a signal line 41 for transmitting the image data through a signal line 47, and a drain 46 of the transistor is coupled to the data line through an electrode 46 and a signal line 48.
Accordingly, the control signal X1 is applied to the signal line 42, and transmitted to the signal line 44 that forms the gate electrode of the switching transistors through the signal lines 43a to 43c. The transistor transmits the image data provided through the signal line 41 to the data line.
As described, when the control signal X1 is transmitted using the three signal lines 43a to 43c, the variation in time to apply the output signal to the plurality of switches may be reduced, and the more accurate image signal is transmitted to the data line.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention that come within the scope of the claims and their equivalents.
While it has been described that the switches are formed as MOS transistors having a p-type channel, the present invention covers the modifications and variations of the switches provided that active elements perform a switching operation of two terminals in response to the applied control signal according to the exemplary embodiments.
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