Resistor random access memory cell device

Abstract

A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

Description

REFERENCE TO RELATED APPLICATION

This application is a Divisional of copending U.S. application Ser. No. 11/617,542, titled “Resistor Random Access Memory Cell Device”, by Erh-Kun Lai, ChiaHua Ho, and Kuang Yeu Hsieh filed 28 Dec. 2006. The foregoing application is incorporated by reference herein for all purposes.

BACKGROUND

1. Field of the Invention

This invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and by reducing the size of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure.

SUMMARY

Generally, the invention features a memory cell device of the type that includes a memory material switchable between electrical property states by application of energy. The memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

In one general aspect the invention features a memory cell device including a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim in contact with the top electrode and having an opening in the bottom in contact with the memory material.

In another general aspect the invention features a method for making a memory cell device, by: providing a substrate having an intermetal dielectric at a surface, forming a first electrode layer over the intermetal dielectric, forming an electrically insulative layer over the first electrode layer, forming a stop layer over the electrically insulative layer, and patterning the layers to form bottom electrode islands each including an electrically insulative element and a stop element; depositing a fill material over the intermetal dielectric and the islands; removing the fill material to the stop element; removing the stop element, forming a hole defined by a wall of the separation layer and an exposed surface of the electrically insulative element; depositing an electrically conductive material to form an electrically conductive film over the fill material, the wall of the separation layer and the exposed surface of the electrically insulative element; depositing an electrically insulative liner material over the electrically conductive film; performing an anisotropic etch to remove the insulative liner material and the conductive film from the surface of the separation layer and to form an opening through the insulative liner material and through the conductive film; depositing a phase change memory material into the opening; forming an oxide cap over the phase change memory material; and forming a top electrode over the oxide cap and surface of the separation layer.

The method according to the invention is a straightforward self-aligned process, and is readily scalable.

In the resulting memory cell construct the memory material is in electrical contact with a bottom electrode. A conductive member includes a sidewall having a rim and a bottom having an opening. The memory material contacts the bottom electrode and contacts the conductive member at the opening; and the rim of the cup-shaped member contacts the top electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sketch in a sectional view showing a memory cell device according to an embodiment of the invention.

FIGS. 2A and 2B are diagrammatic sketches in plan and a sectional views, respectively, showing a patterned bottom electrode stack, including bottom electrode, oxide, and silicon nitride layers, on a surface of an intermetal dielectric.

FIGS. 3A and 3B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of depositing and polishing a fill around a stack as in FIGS. 2A, 2B.

FIGS. 4A and 4B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of removing the silicon nitride layer from the stack.

FIGS. 5A and 5B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of depositing a layer of titanium nitride over the structure of FIGS. 4A, 4B, and forming a liner layer of silicon dioxide over the titanium nitride layer.

FIGS. 6A and 6B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of anisotropically etching through the silicon dioxide and the titanium nitride to expose an area of the bottom electrode.

FIGS. 7A and 7B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of depositing a GST layer over the structure of FIGS. 6A, 6B, and etching back to form a GST plug.

FIGS. 8A and 8B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of depositing a cap oxide over the structure of FIGS. 7A, 7B, and planarizing.

FIGS. 9A and 9B are diagrammatic sketches in plan and a sectional views, respectively, showing the result of forming a top electrode over the structure of FIGS. 8A, 8B, and marked to illustrate dimensions of some features of the completed memory cell.

FIG. 9C is a diagrammatic sketch in a plan view as in FIG. 9A showing an alternative form of top electrode.

FIG. 10 is a schematic diagram for a memory array comprising phase change memory elements.

DETAILED DESCRIPTION

The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGS. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGS.

Turning now to FIG. 1, there is shown generally at 10 a memory cell structure according to an embodiment of the invention. Memory cell structure 10 includes a bottom electrode 12 and a top electrode 14. An electrically insulative layer 16 overlies the bottom electrode 12. An electrically conductive cup-shaped liner 18 includes a bottom part 27 formed over the insulative layer 16 and a side wall part 29 having a rim 13 which contacts the top electrode 14. An electrically insulative liner 17 is formed over the bottom part 27 and within the side wall part 29 of the conductive cup-shaped liner 18. A plug 20 of a phase change memory material is formed within an opening through the insulative liner 17, the bottom part 27 of the conductive cup-shaped liner 18, and the insulative layer 16. The plug 20 of phase change memory material contacts a portion 23 of the surface 21 of the bottom electrode 12, and contacts the conductive cap-shaped liner 18 at the opening 28 through the bottom part 27. An electrically insulative cap 26 fills the volume within the insulative liner 17 and between the top electrode 14 and the plug 20 of phase change material. The bottom electrode 12, the insulative layer 16 and the conductive cup-shaped liner 18, together with plug 20 of phase change material and the remainder of the features contained within the cup-shaped liner, are enclosed by a fill layer or separation layer 11. The fill layer 11 and the bottom electrode 12 rest upon an intermetal dielectric; and the top electrode 14 rests upon the fill layer 11, and contacts the rim 13 of the conductive cup-shaped liner 18. Thus, the top electrode is electrically connected to the cup-shaped liner at the rim of the side wall of the cup-shaped liner; the plug of phase change material is electrically connected to the bottom electrode at a portion of the surface of the bottom electrode; and the cup-shaped liner is electrically connected to the plug of phase change material at the opening of the bottom of the cup-shaped liner. The conductive path, illustrated roughly by arrows 19, passes from the top electrode 14 through the conductive cup-shaped liner 18, through the plug 20 of phase change material to the bottom electrode 12.

This memory cell structure according to the invention provides several advantageous features, as FIG. 1 shows. The plug of phase change material has a small area of contact with the bottom electrode. The current flow from the top electrode (by way of the cup-shaped liner) to the plug of phase change material is confined to a small area where the opening through the bottom part of the cup-shaped liner contacts the phase change material.

FIG. 10 is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration of FIG. 10, a common source line 128, a word line 123 and a word line 124 are arranged generally parallel in the Y-direction. Bit lines 141 and 142 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block 145 are coupled to the word lines 123, 124. An X-decoder and a set of sense amplifiers in block 146 are coupled to the bit lines 141 and 142. The common source line 128 is coupled to the source terminals of access transistors 150, 151, 152 and 153. The gate of access transistor 150 is coupled to the word line 123. The gate of access transistor 151 is coupled to the word line 124. The gate of access transistor 152 is coupled to the word line 123. The gate of access transistor 153 is coupled to the word line 124. The drain of access transistor 150 is coupled to the bottom electrode member 132 for memory cell 135, which has top electrode member 134. The top electrode member 134 is coupled to the bit line 141. Likewise, the drain of access transistor 151 is coupled to the bottom electrode member 133 for memory cell 136, which has top electrode member 137. The top electrode member 137 is coupled to the bit line 141. Access transistors 152 and 153 are coupled to corresponding memory cells as well on bit line 142. It can be seen that in this illustrative configuration the common source line 128 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data.

Embodiments of memory cell device 10 include phase change based memory materials, including chalcogenide based materials and other materials, for memory material 20. Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In the disclosure herein, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory device described herein is Ge2Sb2Te5.

With reference again to FIG. 1, access circuitry, such as described with reference to FIG. 10, can be implemented to contact the first electrode 12 and the second electrode 14 in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the phase change material 20 in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state. For example, application of an electrical pulse having a suitable shorter, high amplitude profile, for example, results in changing the phase change material 20 locally to a generally amorphous state, as indicated at 22 in FIG. 1.

Manufacture of a memory cell device 10 will be described with reference to FIGS. 2A-9C, in which various stages in an exemplary process are shown in plan view (2A, 3A, etc.; an array of four memory cells is shown) and in sectional view (2B, 3B, etc.; one memory cell is shown). Access circuitry is provided in a substrate having a surface intermetallic dielectric layer 221. An electrically conductive layer of a conductive material suitable for a bottom electrode, such as a metal or metal-based or non-metal material, such as, e.g.: copper; aluminum; titanium (Ti) and titanium-based materials such as titanium nitride (TiN), titanium ox nitride (Ton); tantalum (Ta) and tantalum-based materials such as tantalum nitride (Tan); polysilicon, tungsten-based materials such as tungsten silicide (WSix); and, for a low thermal conductivity electrode, materials such as LNO (LaNiO3) and LSMO (LaSrMnO3), is deposited on the surface of the intermetallic dielectric layer 221; an electrically insulative layer, such as an oxide (e.g., silicon dioxide) is deposited over the bottom electrode layer; and an etch stop layer, of a material such as silicon oxynitride or silicon nitride, is deposited over the insulative layer.

The bottom electrode layer may have a thickness, for example, in a range about 200 Å to about 3000 Å, usually about 500 Å. An oxide insulative layer, for example, may have a thickness in a range about 50 Å to about 2000 Å, such as about 200 Å for a silicon dioxide layer. A silicon nitride etch stop layer, for example, may have a thickness in a range about 200 Å to about 3000 Å, usually about 1000 Å. The layers are then patterned and etched to form bottom electrode stacks or islands 210, each including a bottom electrode 212, an insulative layer (oxide, such as silicon dioxide) 216, and an etch stop layer 230, as shown for example in FIGS. 2A, 2B. Layer 230 is a sacrificial layer, of a material selected according to the materials of the insulative layer 216 and the fill layer 311 (see below); generally a suitable material for the layer 230 has a higher etch selectivity to insulative layer 216 and a higher CMP selectivity to layer 311. Accordingly, polysilicon or tungsten materials are suitable for most insulative layer materials and conductive layers. In plan view (FIG. 2A) the bottom electrode stack is shown here as having been patterned to be a cylindrical island; other shapes may be formed by patterns having different configurations. Alternatively, a cross-point configuration (bit-line/word line) could be employed, as illustrated diagrammatically in FIG. 10.

Then a fill material is deposited over the structure of FIGS. 2A and 2B, and the material is removed back to the surface of the etch stop layer 230, to form a fill layer (or separation layer) 311. Suitable fill materials include, for example, oxides (e.g., silicon dioxide BPSG, FSG lower K, or other material having higher etch selectivity to layer 230), and nitrides (e.g., silicon nitride, silicon oxynitride polysilicon, tungsten, or some other material having higher etch selectivity to layer 216 and a higher CMP rate to layer 311). The fill material surrounds the bottom electrode stacks, and preferably provides a relatively good insulator for heat as well as for electricity, providing thermal and electrical isolation for the memory cells. The fill material may be planarized by chemical mechanical polishing, or by etch back, for example, and exposure of the surface of the etch stop layer 230 may be detected to terminate the polish or etch. The fill material may be deposited by high density plasma chemical vapor deposition, for example, and, in this process the etch stop is protective. Suitable etch stop materials include for example, silicon oxynitride (SiON), tungsten (W), polysilicon, or other material having a higher etch selectivity to insulative layer 216 and a higher CMP rate to layer 311; and the etch stop layer has a thickness, for example, in a range about 200Å to about 3000 Å, usually about 1000Å.

Then the etch stop layer is removed, for example by a selective ion etch or by a wet etch (“dip”). This results in the structure shown in FIGS. 4A and 4B. The separation layer 311 encloses the bottom electrode 212 and the insulative (oxide) layer 216 generally as in the previous FIGS. Now, however, a surface 421 of the insulative (oxide) layer 216 is exposed at the bottom of a hole 422 defined by the surrounding wall 421 of the separation layer.

Then an electrically conductive material is deposited over the structure shown in FIGS. 4A, 4B, forming an electrically conductive film 518 on the top surface of the separation layer, the surface 427 of the insulative (oxide) layer 216, and the surface of the wall 421. Then an electrically insulative material is deposited over the structure, to form a liner layer 517 over the surface of the electrically conductive film 518. The result of these procedures is shown in FIGS. 5A and 5B. The thickness of the liner layer is limited so that it does not entirely fill the volume in the hole, leaving a void 522. Suitable materials for the electrically conductive film include, for example, titanium nitride, TI, W, Cu, polysilicon; titanium nitride may be preferred as a liner material because thinner layers of TiN can be effective. Suitable materials for the insulative (oxide) liner layer include, for example, silicon oxynitride (SiON) and silicon nitride (SiN).

Then an anisotropic etch is preformed, to remove the insulative liner material and the conductive film material from the surface of the separation layer, and to etch through the insulative (oxide) liner material and through the conductive film at the bottom of the hole. As shown in FIGS. 6A, 6B, this results in formation of the electrically conductive film 518 as a cup-shaped conductive liner 18, and it also results in formation of an opening 622 passing to the bottom electrode 12 and exposing several features, including: the surface 512 of the separation layer 311, the rim 13 of the cup-shaped liner 18, a small area 23 of the surface 21 of the bottom electrode 12, and the opening 28 through the bottom part 27 of the cup-shaped liner 18. A portion of the insulative liner material remains, over the bottom part 27 and within the side wall part 29 of the cup-shaped liner 18.

A suitable anisotropic etch may include several steps, and an example employing three steps follows. In this example the insulative liner 517 (17) is SiN, the electrically conductive film 518 (18) is a metal such as copper, and the insulative layer 216 (16) is silicon oxide. In the first step, for SiN, a reactive ion etch (RIE) is performed, using a higher bottom power of, for example, 80-200 W and chemistries such as CH3F or CHF3 or a mixture of CH3F and CHF3, optionally with one of, or a mixture of two or all of, argon, nitrogen, and oxygen. In the second step, for the metal, a chlorine-based etch is performed, such as a RIE using chemistries of BC13or C12 or a mixture of BC13 and C12, optionally with argon or nitrogen or a mixture of argon and nitrogen. As in the first step, in the second step the bottom power is high enough to perform anisotropic etch, for example higher than 100 W for an 8″ wafer process. The second step etch can be stopped by time control or by end point detection; for end point detection C-N signal degradation can be employed to detect the TiN etching process. In the third step, for SiO2, a RIE is performed, using fluorine-based chemistries such as C4F8 or CF4 or CHF3 or C4F6 or a mixture of one or more of C4F8, CF4, CHF3, and C4F6, optionally with oxygen or argon or a mixture of oxygen and argon. The selectivity of the third layer, (here SiO2) to the first layer (here SiN) is high to prevent damage to the SiN layer during the third etch step; the etch selectivity may be higher than about 10, for example. Parameters of the etch steps may be adjusted or tuned as a matter of routine to obtain optimum performance and to optimize the physical profile of the resulting etch. An O2 plasma strip may be performed between the second and third steps, to remove polymer residue within the hole. Optionally an additional dry strip can be performed following each of the three steps and following the conventional O2 plasma strip.

Then the phase change memory material is deposited over the structure shown in FIGS. 6A, 6B, and the upper portion of the deposited material is removed, for example by etch back, to leave a plug 20 of the phase change material in the lower part of the opening 622 as shown in FIGS. 7A and 7B. The phase change memory material may be a chalcogenide of the formula GexSbyTez (a “GST”), where x=0−5; y=0−5; and z=0−10, such as, for example, a GST where x:y:z=2:2:5. Or the phase change material may be a GST, such as for example, a N-doped GST or a Si-doped GST, or a Ti-doped GST; or another element may be employed as a dopant.

The chalcogenide phase change memory material is deposited by PVD sputtering or by magnetron-sputtering, using argon, nitrogen, helium or the like or mixtures of such gases as reactive gases, at pressure in the range about 1 mtorr to about 100 mtorr, and usually at room temperature. Fill-in performance can be improved by using a collimator with an aspect ratio of about 1 to about 5, or by employing a DC bias in the range about 10 V to about 1000 V (such as several tens of volts to several hundred volts), or by a concurrent use of both a collimator and a DC bias. Following deposition the chalcogenide material may be annealed to improve the crystalline state. The post deposition anneal can be done, for example, under vacuum or nitrogen ambient, at temperatures in the range about 100° C. to about 400° C. for a time less than 30 minutes.

The thickness of the chalcogenide plug depends upon the design of the cell structure. Generally a chalcogenide plug having a thickness greater than about 8 nm can show a phase change characteristic with bistable resistance. The deposited chalcogenide material can be etched back using a conventional metal-dry-etch recipe, that is, a RIE using chemistries such as CI2 or CF4 or a mixture of CI2 and CF4, optionally with argon or oxygen or a mixture of argon and oxygen. In order to remove GST outside the hole, an anisotropic GST etch is needed. The RIE should have additional bottom power, such as for example 40-100 W, to form the structure shown in FIG. 7B. End point detection can be used to stop the GST etch.

Where the memory materials is deposited by sputtering, the conditions may include, for example, nitrogen or argon gas (or a mixture of argon and nitrogen); the target may be GeSbTe if only argon gas is used, or, if Ar/N2 gas is used, the target may be N2-GeSbTe.

The etch back is controlled so that the contact of the phase change memory material with the cup-shaped liner at the opening 28 is maintained. The plug of phase change memory material contacts the bottom electrode at the small area 23, and it contacts the cup-shaped conductive film 18 at the opening 28. The plug is confined by the lower part of the opening 622, and the shape and dimensions of the plug—including the area 23 of contact of the plug with the bottom electrode—are defined by the shape and dimensions of the lower part of the opening 622 and by the height of the plug as remains following the etch back.

Then an oxide material (such as silicon dioxide) is deposited over the structure of FIGS. 7A, 7B, filling the volume within portion of the opening 622 remaining over the plug 20, and the oxide material is planarized to form a cap oxide 26.

Then an electrically conductive material suitable for a top electrode, such as a metal or metal-based or non-metal material, such as, e.g.: copper; aluminum; titanium (Ti) and titanium-based materials such as titanium nitride (TiN), titanium oxynitride (TiON); tantalum (Ta) and tantalum-based materials such as tantalum nitride (TaN); polysilicon, tungsten-based materials such as tungsten silicide (WSix); and, for a low thermal conductivity electrode, materials such as LNO (LaNiO3) and LSMO (LaSrMnO3), is deposited over the structure of FIGS. 8A, 8B, and is patterned to form top electrodes over the memory cell components, as shown in FIGS. 9A, 9B, and 9C. The top electrode may be patterned as islands, as shown for example in FIG. 9A, or as lines (straplines or bitline), as shown for example in FIG. 9C. The top electrode may have a thickness, for example, in a range about 200 Å to about 5000 Å, usually about 2000 Å.

The resulting memory cell device is shown at FIG. 9B, marked to indicate dimensions of some features. Generally the cross-sectional shape of the features in the memory cell made according to the invention are defined by the shape of the hole in the separation layer, which in turn may be defined by the shape of the memory stack or island. Similarly, the shape and dimensions of the plug of phase change material are defined by the shape and dimensions of the opening formed by the anisotropic etch, and by the extent of etchback of the phase change material. In the illustrated embodiments various of the features of the memory cell are shown as having a circular cross-section (in the plane of the surface of the intermetallic dielectric), but as will be understood other cross-sectional shapes may be used. Certain of the dimensions shown by way of example with reference to FIG. 9B may be termed “widths”, with the understanding that where the feature is circular, a diameter is meant.

The width 92 of the hole through the separation layer may be in a range about 50 nm to about 400 nm, usually about 100 nm. The thickness 94 of the side wall portions of the cup-shaped conductive film may be in a range about 25 Å to about 200 Å, usually about 50 Å, and the thickness 95 of the bottom portion of the cup-shaped conductive film may be in a range about 25 Å to about 200 Å, usually about 50 Å. The width 98 of the area of contact of the plug with the bottom electrode may be in a range about 20 nm to about 260 nm, usually about 70 nm providing a contact area in a range about 20 nm to about 260 nm, usually about 70 nm. The height 99 of the plug depends among other factors upon the thickness 95 of the bottom portion of the cup-shaped conductive film and the thickness of the insulative oxide between the contact area at the bottom electrode; the height 99 may be in a range about 20 nm to about 100 nm, usually about 30 nm.

Embodiments of memory cell device 10 include phase change based memory materials, including chalcogenide based materials and other materials, for memory material 20. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IV of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, columns 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7. (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.

The invention has been described with reference to phase change materials. However, other memory materials, also sometimes referred to as programmable materials, can also be used. As used in this application, memory materials are those materials having electrical properties, such as resistance, that can be changed by the application of energy; the change can be a stepwise change or a continuous change or a combination thereof. Other programmable resistive memory materials may be used in other embodiments of the invention, including N2 doped GST, GexSby, or other material that uses different crystal phase changes to determine resistance; PrxCayMnO3, PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene 6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse. Further examples of programmable resistive memory materials include GeSbTe, GeSb, NiO, Nb—SrTiO3, Ag—GeTe, PrCaMnO, ZnO, Nb2O5, Cr—SrTiO3.

For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067, filed 17 June 2005, titled Thin Film Fuse Phase Change Ram And Manufacturing Method, Attorney Docket No. MXIC 1621-1.

Other embodiments are within the scope of the invention.

Claims

1. A method for making a memory cell device, comprising:

providing a substrate having an intermetal dielectric at a surface, forming a first electrode layer over the intermetal dielectric, forming an electrically insulative layer over the first electrode layer, forming a stop layer over the electrically insulative layer, and patterning the first electrode layer, the electrically insulative layer, and the stop layer to form bottom electrode islands;

depositing a fill material over the intermetal dielectric and the islands;

removing the fill material to the stop layer, the remaining fill material comprising a separation layer;

removing the stop layer, forming a hole defined by a wall of the separation layer and an exposed surface of the electrically insulative layer;

depositing an electrically conductive material to form an electrically conductive film over the wall of the separation layer and the exposed surface of the electrically insulative layer;

depositing an electrically insulative liner material over the electrically conductive film;

performing an anisotropic etch to remove the insulative liner material and the conductive film from a top surface of the separation layer and to form an opening through the insulative liner material and through the conductive film, wherein the remaining electrically conductive film having a cup-shape, and having a rim and a bottom, and the opening extends through the bottom of the remaining electrically conductive film;

depositing a phase change memory material into the opening;

forming an oxide cap over the phase change memory material;

and forming a top electrode over the oxide cap and surface of the separation layer.

2. The method of claim 1 wherein depositing the separation layer comprises depositing a material having a higher etch selectivity than that of the stop layer.

3. The method of claim 1 wherein depositing the stop layer comprises depositing a material having a higher CMP rate than of the separation layer.

4. The method of claim 1 wherein depositing the separation layer comprises high density plasma chemical vapor deposition.

5. The method of claim 1 wherein depositing the stop material comprises depositing a material having a higher etch selectivity than that of the insulative layer.

6. The method of claim 1 wherein depositing the stop material comprises depositing a material having a higher CMP rate than that of the separation layer.

7. The method of claim 1 wherein performing the anisotropic etch comprises performing a reactive ion etch to remove the insulative liner material, performing a chemical etch using a chlorine-based chemistry to form the opening through the conductive film, and performing a reactive ion etch using a fluorine-based chemistry to form the opening through the electrically insulative layer.

8. A method of making a memory device, comprising:

providing a bottom electrode;

forming a first insulating element over the bottom electrode;

forming a conductive member over the first insulating element;

forming an opening in the first insulating element and the conductive member;

forming a memory element in the opening, wherein the memory element directly and physically contacts the bottom electrode and is electrically coupled to the conductive member;

forming a second insulating element over the memory element; and

forming a top electrode over the second insulating element, wherein the memory element is electrically coupled to the top electrode through the conductive member.

9. A method of making a memory device, comprising:

providing a bottom electrode having an upper surface with a surface area;

forming a first insulating element over the bottom electrode;

forming a conductive member over the first insulating element;

forming an opening in the first insulating element and the conductive member, exposing a portion of the upper surface of the bottom electrode;

forming a memory element in the opening, wherein the memory element is directly and physically contacts the upper surface of the bottom electrode and is electrically coupled to the conductive member, wherein the memory element has an area in contact with the bottom electrode, the area is smaller than the surface area of the upper surface of the bottom electrode;

forming a second insulating element over the memory element; and

forming a top electrode over the second insulating element, wherein the memory element is electrically coupled to the top electrode through the conductive member.

10. The method of claim 9, wherein the bottom electrode comprises a plug within a via through a dielectric layer.