A transponder and method for operating a transponder, which has a capacitor (Cbuf) for storing power transmitted via an air interface and an arithmetic logic unit (10) that can be supplied with the stored power,
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9. One or more non-transitory computer-readable storage media embodying logic that is operable when executed to:
receive a comparison of a capacitor voltage of a capacitor with a threshold voltage, the capacitor storing power transmitted via an air interface;
determine, at a first time and in response to determining that the capacitor voltage of the capacitor exceeds the threshold, to operate in a first operating mode, the first operating mode comprising performing a number of routines having different associated priorities;
update a status register of the arithmetic logic unit with an indicator of the determined first operating mode;
determine, at a second time and in response to determining that the capacitor voltage of the capacitor is below the threshold, to operate in a second operating mode, the second operating mode comprising suspending at least one routine at a place within a run of the at least one routine;
update a status register of the arithmetic logic unit with an indicator of the second operating mode; and
resume, in response to determining at a third time that the capacitor voltage of the capacitor exceeds the threshold, the at least one previously suspended routine from the place within the run at which the at least one previously-suspended routine was suspended.
1. A method comprising:
comparing a capacitor voltage of a capacitor of a transponder, the capacitor for storing power transmitted via an air interface, with a threshold voltage, the transponder having an arithmetic logic unit configured to be supplied with the at least a portion of the stored power;
determining, at a first time and in response to determining that the capacitor voltage of the capacitor exceeds the threshold, to operate in a first operating mode, the first operating mode comprising performing a number of routines having different associated priorities;
updating a status register of the arithmetic logic unit with an indicator of the determined first operating mode;
determining, at a second time and in response to determining that the capacitor voltage of the capacitor is below the threshold, to operate in a second operating mode, the second operating mode comprising suspending at least one routine at a place within a run of the at least one routine;
updating a status register of the arithmetic logic unit with an indicator of the second operating mode; and
resuming, in response to determining at a third time that the capacitor voltage of the capacitor exceeds the threshold, the at least one previously-suspended routine from the place within the run at which the at least one previously-suspended routine was suspended.
5. A transponder comprising:
a capacitor configured to store power transmitted via an air interface;
a comparator configured to:
compare a capacitor voltage of the capacitor with a threshold voltage;
and
an arithmetic logic unit supplied with the stored power from the capacitor, the arithmetic logic unit configured to:
determine, at a first time and in response to determining that the capacitor voltage of the capacitor exceeds the threshold, to operate in a first operating mode, the first operating mode comprising performing a number of routines having different associated priorities;
update a status register of the arithmetic logic unit with an indicator of the determined first operating mode;
determine, at a second time and in response to determining that the capacitor voltage of the capacitor is below the threshold, to operate in a second operating mode, the second operating mode comprising suspending at least one routine at a place within a run of the at least one routine;
update a status register of the arithmetic logic unit with an indicator of the second operating mode; and
resume, in response to determining at a third time that the capacitor voltage of the capacitor exceeds the threshold, the at least one previously-suspended routine from the place within the run at which the at least one previously-suspended routine was suspended.
2. The method of
3. The method of
4. The method of
6. The transponder of
7. The transponder of
8. The transponder of
10. The media of
11. The media of
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This nonprovisional application claims priority to German Patent Application No. DE 102007027610, which was filed in Germany on Jun. 12, 2007, and to U.S. Provisional Application No. 60/944,081, which was filed on Jun. 14, 2007, and which are both herein incorporated by reference.
The present invention relates to a transponder and a method for operating a transponder, as well as to a use for a transponder.
German patent publication DE 698 31 711 T2 shows a transponder communication device, which is configured for contactless communication with a transponder present within a reception range of the transponder communication device. Furthermore, German patent publication DE 698 31 711 T2 shows a transponder, which is configured for contactless communication with at least one transponder communication device and which is activated in an active state to communicate with a transponder communication device.
This type of transponder communication device with a transponder is also disclosed in U.S. Pat. No. 5,339,073. U.S. Pat. No. 5,339,073 discloses an access control equipment, which contains an interrogation unit, which emits an interrogation signal, as well as a plurality of transponders, whereby each transponder has a stored identity code different from that of the other transponders. This identity code contains a plurality of fields, each of which holds a selected information bit. The interrogation signal is controlled so that the fields of all transponders within range are interrogated simultaneously in a serial manner. A group reply signal is sent back to the interrogation unit by any transponder which has, in the interrogated field, a bit matching required by the interrogation signal. The interrogation unit is arranged to determine, from the series of received reply signals, the identity of each and every valid transponder within range.
Another exemplary document is U.S. Pat. No. 5,345,231, whereby for the case when there are several transponders in the reception range of a known transponder communication device, the problem arises of the individual selection of each and every known transponder. This individual selection can be performed with use of selection means of a transponder communication device.
U.S. Pat. No. 5,621,412 discloses a system and a method in which energy is conserved during transponder operation. In this case, the transponder is activated or awakened in multiple stages. A threshold detector measures the power level of the received RF energy. If the RF energy exceeds a predetermined threshold, the transponder employs the modulation detector to ascertain whether it was awakened by a valid signal or by a random sudden change in amplitude (burst). If a predetermined modulation has been detected, the transponder is fully activated to its normal operational state.
A method for transmitting data between a base station and a passive transponder is known from European Patent Application EP 473 569 B1. In this case, digital data are exchanged between a base station and a passive transponder by means of an amplitude modulated carrier wave.
The object of the invention is to provide a method which improves the power supply to a transponder as much as possible.
This object is achieved by a method with the features of independent claim 1. Advantageous refinements are the subject of dependent claims.
Accordingly, a method for operating a transponder is provided. The transponder has a capacitor for storing power transmitted via an air interface and an arithmetic logic unit that can be supplied with the stored power. If the transponder is supplied with power transmitted via an air interface, this type of transponder is also called a passive transponder. In addition, the transponder can have its own power supply, such as, for example, a chargeable or nonchargeable battery.
In the method, a capacitor voltage of the capacitor is compared with a first threshold. A comparator can be used, for example, for the comparison. For this purpose, for example, the voltage of the capacitor is sampled and analog-to-digital converted. Alternatively, an analog comparator may also be employed which enables a continuous comparison. Furthermore, the capacitor voltage is compared with the second threshold, whereby the first threshold and the second threshold are different. A comparator, for example, can be employed for the comparison of the capacitor voltage with the second threshold. The comparison with the first threshold and with the second threshold can occur disjunctive in time but preferably simultaneously.
Preferably, the arithmetic logic unit in a first operating mode performs a number of routines with a different priority. The first operating mode is thereby defined when the capacitor voltage is above the first threshold. In this case, capacitor voltage is taken to mean the absolute value, so that it is immaterial whether the capacitor voltage is regarded as a positive or negative voltage. The operating mode is preferably established by the arithmetic logic unit by setting, for example, certain values or parameters.
The operating mode preferably depends on the capacitor voltage detected advantageously by a comparator. Preferably, a coded signal or a signal assigned for detection is transmitted to the arithmetic logic unit. The signal is, for example, a detection status flag or an interrupt signal (IRQ, interrupt request). Advantageously, a status register, programmed within the arithmetic logic unit, is updated according to the detection within a software program. In this way, tracking of the operating mode and control of functionalities of the arithmetic logic unit or the transponder are advantageously made possible.
Preferably, in a second operating mode a number of routines with a low priority are stopped and a number of routines with a high priority are continued. This occurs under the condition that the capacitor voltage is between the first threshold and the second threshold. Preferably, the routines, for example, interrupt routines (IRQ), assigned to the second threshold, have a higher priority than routines assigned to the first threshold. Higher-priority routines can preallocate, for example, interruptions of the program run, which are otherwise assigned to lower-priority routines.
According to an advantageous refinement, suspension of the routines of the arithmetic logic unit occurs in a third operating mode. The suspension occurs under the condition that the capacitor voltage is below the second threshold. In this case, register values of routines are stored, for example, in a nonvolatile memory (EEPROM, FRAM, etc.) and the values can be reloaded into the register after the suspension.
A preferred refinement provides that at least the previously suspended routines are continued, when the capacitor voltage is again above the first threshold or even above the second threshold. If the arithmetic logic unit is reset, first an initialization is started and then the routines are run from their beginning. In contrast, the suspended routines can be continued at any place within their run. Preferably, at least one of the suspended routines is continued at a place within its run at which it was previously suspended. Alternatively, returns within the run of the specific routine are also possible. To continue the routine, said routine therefore is not restarted or initialized.
It is provided in another refinement that falling below and/or exceeding the first threshold by the capacitor voltage triggers a first interrupt signal (interrupt request) to interrupt the program run in the arithmetic logic unit. For this purpose, the interrupt signal reaches an interrupt-capable input of the arithmetic logic unit. The interrupt signal is generated, for example, as a rising edge of a digital signal. It is provided in yet another refinement that falling below and/or exceeding the second threshold by the capacitor voltage triggers a second interrupt signal to interrupt the program run in the arithmetic logic unit.
The object of the invention is furthermore to provide a use for a transponder whose power supply is improved as much as possible.
This object is achieved by a use with the features of independent claim 6. The use can be refined advantageously by the features of the method or the transponder.
Accordingly, a use of a first threshold and a second threshold, different from the first threshold, is provided to monitor a capacitor voltage of a capacitor of a transponder. In addition to the capacitor, the transponder has an arithmetic logic unit, which can be supplied with power stored in the capacitor. Preferably, the arithmetic logic unit is configured to reduce the current uptake, when the capacitor voltage is between the first threshold and the second threshold.
Preferably, the arithmetic logic unit operates in a first operating mode, when the capacitor voltage is above the first threshold. The first operating mode can also be called the normal mode (normal level). In the first operating mode, the functionality of the arithmetic logic unit and/or the transponder is not limited.
Preferably, the arithmetic logic unit operates in a second operating mode, when the capacitor voltage is below the first threshold and above a second threshold. The second operating mode can also be called the warning mode (warning level). Advantageously, at least a limitation of a current drain from the capacitor is activated in the second operating mode. Advantageously, at least a functionality of the transponder is deactivated in the second operating mode to reduce the current drain from the capacitor. Preferably, a firmware periodically reads a status register which is programmed within the arithmetic logic unit and contains the operating mode. Advantageously, depending on a value of the status register, peripheral circuits in the transponder are activated or deactivated and a clock frequency of the arithmetic logic unit is changed.
Preferably, the arithmetic logic unit operates in a third operating mode, when the capacitor voltage is below the second threshold. The third operating mode can also be called the emergency operating mode (stop level). Advantageously, in the third operating mode the predominant part of the functionality of the transponder is deactivated. Only a low charge remains in the capacitor. The arithmetic logic unit advantageously switches to a sleep state. For this purpose, the routines of the arithmetic logic unit are preferably suspended. The suspended routines are continued by a return at any place within its run, for example, at the suspended place or another place, when the capacitor voltage is at least above the second threshold.
A third threshold is preferably provided in addition below the second threshold. Preferably, the arithmetic logic unit is reset, when the capacitor voltage falls below the third threshold (reset level). For example, in the third operating mode despite the deactivation of the predominant part of the transponder's functionality, the capacitor voltage can decline further due to a very low current drain from the capacitor and fall below the third threshold. Advantageously, a resetting of the arithmetic logic unit then occurs to avoid undefined states. If the capacitor voltage rises again after the resetting, the arithmetic logic unit is first initialized and then all routines are begun again.
The object of the invention furthermore is to provide a transponder whose power supply is improved as much as possible.
This object is achieved by a transponder with the features of independent claim 7. Advantageous refinements are the subject of dependent claims.
Accordingly, a transponder with a transmit-receive circuit, with a capacitor, with an arithmetic logic unit, and with a comparator circuit is provided. The capacitor is connected to the transmit-receive circuit for charging. The arithmetic logic unit is connected to the capacitor for the power supply. Preferably, the arithmetic logic unit is connected directly or indirectly to the transmit-receive circuit for data transmission.
The comparator circuit is connected to the capacitor. Furthermore, the arithmetic logic unit is connected to the comparator circuit. The comparator circuit is set up to compare a capacitor voltage of the capacitor with a first threshold and with a second threshold different from the first threshold. The capacitor voltage can be applied preferably as an input variable at an input of the comparator circuit.
In an advantageous refinement, the first threshold and/or the second threshold has a hysteresis. Preferably, the comparator circuit has a first window comparator or Schmitt trigger for the first threshold and/or a second window comparator or Schmitt trigger for the second threshold. The hysteresis has a voltage window in regard to the capacitor voltage in which the operating mode is not changed. If, for example, the lower hysteresis for the first threshold is underrun, the arithmetic logic unit changes, for example, from the first operating mode to the second operating mode. If the capacitor voltage increases slightly afterwards, for example, whereby the top hysteresis level of the first threshold is not yet exceeded, the arithmetic logic unit remains in the second operating mode. Only when the top hysteresis level is exceeded by the capacitor voltage does the comparator circuit generate a signal that interrupts, for example, the program run of the arithmetic logic unit, so that the arithmetic logic unit can change back to the first operating mode.
The arithmetic logic unit is preferably set up to perform a number of routines with a different priority within its program run.
According to a preferred refinement, the arithmetic logic unit is set up, depending on an output signal of the comparator circuit, to stop a number of low-priority routines and to continue a number of high-priority routines. Alternatively or in combination, to stop the low-priority routines, in another advantageous refinement, the arithmetic logic unit is set up to disconnect peripheral circuits from the current supply from the capacitor, depending on the output signal of the comparator circuit, or to reduce the frequency of the arithmetic logic unit clock signal.
In an advantageous refinement, the transponder has in addition a battery and a switch. The switch is connected to the battery and to the capacitor to switch the power supply between the battery and capacitor. The battery is chargeable, for example.
Preferably, the arithmetic logic unit is set up to control the switching of the power supply depending on a comparator circuit output signal. Alternatively, another subcircuit of the transponder can also be provided to control the switching.
According to an especially preferred refinement, the first threshold and/or the second threshold of the comparator circuit can be adjusted. The adjustment can be made in this case by a signal over the transmit-receive circuit or by control of the arithmetic logic unit. Preferably, the adjustment of the first and/or second threshold occurs dynamically, for example, as a function of the boundary condition of the transponder. Advantageously, a self-learning adjustment, for example, by means of evaluation by the arithmetic logic unit is also possible.
It is provided in another refinement that the arithmetic logic unit is configured to adjust the first threshold and/or the second threshold and is connected to a control input of the comparator circuit.
Preferably, the comparator circuit has a multiplexer. A first input of the multiplexer is connected to the capacitor and a second input of the multiplexer to a battery, particularly to measure the battery voltage.
The previously described refinement variants are especially advantageous both individually and in combination. In this regard, all refinement variants can be combined with one another also under different claim categories. Some possible combinations are explained in the description of the exemplary embodiments shown in the figures. These possible combinations of the refinement variants, depicted there, are not definitive, however.
In the following text, the invention will be described in greater detail by exemplary embodiments using the graphic drawings.
Here,
Discharge current ID is used to supply an arithmetic logic unit 10 and other subcircuits 12, 20, 30, 31, 40, 41, 50 with electric power. For this purpose, a voltage regulator 30 connected to capacitor Cbuf is provided, which provides a supply voltage Vdd at its output. To supply arithmetic logic unit 10 as the main current consumer, voltage regulator 30 is connected via a switch 31 to the supply voltage terminal of arithmetic logic unit 10. Arithmetic logic unit 10 is, for example, a computation core of a microcontroller.
If the charging current IC exceeds the discharge current ID, the capacitor Cbuf is charged, so that the capacitor voltage VC increases. If, in contrast, the discharge current ID exceeds the charging current IC, the capacitor Cbuf is discharged, so that the capacitor voltage VC declines. The capacitor voltage VC thereby depends on the difference between charging current IC and discharge current ID. If the capacitor voltage VC is too low, arithmetic logic unit 10 can no longer process the program routines of a program run reliably. The error frequency increases with declining capacitor voltage VC and can lead to the interruption of the program run and to the resetting of arithmetic logic unit 10. Arithmetic logic unit 10 register values that are not stored are lost upon resetting.
To increase the availability of the arithmetic logic unit in
Several operating modes are defined for the arithmetic logic unit 10 of the exemplary embodiment of
In the exemplary embodiment of
Output signal B is inverted or not inverted by switchable inverter 12 depending on the control signal D. The switched output signals A′ or B′ are applied at the inputs of arithmetic logic unit 10. In the exemplary embodiment of
Furthermore, comparator circuit 40 is connected to at least one output of arithmetic logic unit 10. Comparator circuit 40 is formed with adjustable thresholds, so that at least one threshold can be adjusted by arithmetic logic unit 10 and can be changed particularly during transponder operation.
Comparator circuit 40 can have furthermore a multiplexer 41 to switch several voltages to be monitored to the input Vin. In the exemplary embodiment of
Switch 31 of the exemplary embodiment in
Another input of control circuit 50 is connected to transmit-receive circuit 20. This makes it possible that transmit-receive circuit 20 switches switch 31, when the transmission is active and the received power is sufficient for running programs in arithmetic logic unit 10. The connection of control circuit 50 to arithmetic logic unit 10 makes it possible that the software of arithmetic logic unit 10 directly controls switch 31 when the operating mode is identified.
Furthermore, control circuit 50 is connected to comparator circuit 40 in such a way that comparator circuit 40 is switched directly between capacitor voltage VC and battery voltage Vbat by means of a signal. This function is activated only when battery voltage Vbat is available.
Reset logic 60 is connected via an OR gate 61 to a reset input RST of arithmetic logic unit 10. If the voltage supply Vdd of arithmetic logic unit 10 is too low, so that undefined states can occur, arithmetic logic unit 10 is set back in that reset logic 60 applies a reset signal to the reset input RST of arithmetic logic unit 10 via OR gate 61. Thereafter, arithmetic logic unit 10 is re-initialized and all routines are restarted. The data transmission with base station 100 must also be started over. OR gate 61 is also connected to control circuit 50, so that resetting of arithmetic logic unit 10 can be initiated via an input signal to control circuit 50 by arithmetic logic unit 10 itself and/or by comparator circuit 40 and/or by transmit-receive circuit 20.
The invention is thereby not limited to the shown embodiment of the transponder in
The functionality of the transponder circuit according to
A diagram with a functionality of voltage monitoring for a transponder by means of several signal curves is shown schematically in
In the upper part of the diagram, the course of the input voltage Vin, to be compared, is shown in regard to a first threshold V1 and a second threshold V2. The time t is plotted on the abscissa in regard to all signals.
From the start of the plot to time t11, the voltage Vin is above the first threshold V1. Arithmetic logic unit 10 in the associated first operating mode M1 processes a number of routines during the program run, whereby the routines have a different priority.
At time t11, the voltage Vin falls below the first threshold V1. The signal A′ changes from the low value to the high value. The positive edge of the signal A′ triggers an interruption of the program run in arithmetic logic unit 10. Because of this interruption, arithmetic logic unit 10 changes to a second operating mode M2. The second operating mode M2 can also be called the low-power mode. In this second operating mode M2; a number of low-priority routines are stopped and a number of high-priority routines are continued. At least one low-priority routine is therefore stopped and at least one high-priority routine is continued.
High-priority routines are, for example, routines whose register values must be confirmed. These register values are needed to again load the stored register values in the register and to continue the program run after a voltage dip, when the capacitor voltage Vin is again sufficient to continue the routines. This has the surprising effect that after a connection abort as well, a communication need not be totally performed anew, but continuation of the communication according to the state before the connection abort is enabled.
In contrast to high-priority routines, lower-priority routines are stopped. This has the surprising effect that the time interval in which reliable processing of program routines of the program run is possible is extended. This is achieved in that the capacitor voltage VC decreases more slowly also without a charging current IC, i.e., without an alternating magnetic field. The error frequency is reduced. By prioritizing routines and stopping of lower-priority routines, the current drain from capacitor Cbuf by arithmetic logic unit 10 is surprisingly considerably reduced. In this way, the time interval between the two times t11 and t12 and therefore the duration of the operating mode M2 become longer.
At time t12, the voltage Vin falls below the second threshold V2, so that the signal B′ changes from a low value to a high value. The positive edge of signal B′ again leads to an interruption of the program run. Arithmetic logic unit 10 switches to a third operating mode M3. This third operating mode M3 can also be called the sleep mode. The input voltage Vin in the third operating mode M3 can decline so far that any operation can no longer be performed in arithmetic logic unit 10 or undefined states can arise in arithmetic logic unit 10. In this case, a reset can occur, so that all register values in arithmetic logic unit 10 are cleared. To be able to detect an increase in the input voltage Vin also by positive edges, at time t3 switchable inverter 12 is switched with signal D, so that signal A′ is now inverted to signal A and so that signal B′ is now inverted to signal B. Alternatively to the exemplary embodiment of
If in the exemplary embodiment of
At time t21, the input voltage Vin again rises above the first threshold V1. Arithmetic logic unit 10 in operating mode M1 can then again start all high- and low-priority routines. The signal D in the first operating mode M1 is again set to a low value (not shown).
If, in contrast, the second threshold is underrun, a second interrupt signal 74 is generated and the fixed or dynamic address of the interrupt routine is loaded. In program part 77, arithmetic logic unit 10 is placed in a third operating mode, a sleep mode. In the third operating mode, after the last commands are processed, all routines can be suspended to continue these when the voltage supply is restored.
By means of interrupt signal 79, which is assigned to overwriting of the first threshold, or by interrupt signal 80, which is assigned to overwriting of the second threshold, the program flow again reaches program part 72, with the execution of higher-priority routines and lower-priority routines.
The invention is thereby not limited to the exemplary embodiment of a process course according to
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jun 12 2008 | Atmel Corporation | (assignment on the face of the patent) | / |
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