A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
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1. A method of manufacturing an integrated circuit, comprising:
forming first trench isolation structures in a transistor region of a semiconductor substrate;
forming second trench isolation structures in a dynamic random memory (DRAM) region of the semiconductor substrate;
forming an etch mask over the transistor region and the DRAM region;
patterning the etch mask over the second trench isolation structures to expose a portion of each of the second trench isolation structures with the transistor region remaining protected by the etch mask;
removing a portion of the exposed portions to form a gate trench in each of the second trench isolation structures, wherein each of the gate trenches include a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure;
removing the etch mask from the DRAM region;
rounding at least the first corner of each of the gate trenches;
forming an oxide layer over a sidewall, the first rounded corner, and the semiconductor substrate adjacent each of the gate trenches;
forming a gate oxide over the semiconductor substrate in the transistor region;
filling each of the gate trenches with a gate material, the gate material extending over at least the first rounded corner and onto the semiconductor substrate adjacent each of the gate trenches;
forming the gate material over the transistor region;
patterning the gate material in the DRAM region and the transistor region to form gates; and
forming source/drains adjacent the gates.
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This application claims priority of International Application No. PCT/US2007/083176, entitled “METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE”, filed on Oct. 31, 2007. The above-listed application is commonly assigned with the present invention and is incorporated herein by reference as if reproduced herein in its entirety.
The invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a Random Access Memory (RAM) device that has reduced leakage and method of manufacture therefore.
Memory capacity and the demand for that memory for electronic devices of all types have grown explosively as performance requirements for electronic devices as increased. One way in which memory capacity has been increased is through the use of dynamic random access memory (DRAM). Typical DRAM storage cells are created comprising one single Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) and a single capacitor, this DRAM storage cell is commonly referred to as a 1 T-RAM device. The 1 T-RAM device stores one bit of data on the capacitor as an electrical charge.
Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. The continued miniaturization of semiconductor devices, such as DRAM, presents ongoing challenges to semiconductor manufacturers in maintaining or improving that optimization. As performance requirements have continued to increase, leakage concerns within DRAM areas of semiconductor devices has become a point of focus for the industry.
One embodiment of the invention provides a method of manufacturing a semiconductor device. This method includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a semiconductor substrate and patterning an etch mask over the trench isolation structure to expose a portion of the trench isolation structure. A portion of the exposed trench isolation structure is removed to form a gate trench therein, wherein the gate trench includes a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure. The etch mask is removed from the DRAM region and at least the first corner of the gate trench is rounded. An oxide layer is formed over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench, and the trench is filled with a gate material.
Another embodiment includes a method of manufacturing an integrated circuit. This embodiment includes forming first trench isolation structures in a transistor region of a semiconductor substrate, forming second trench isolation structures in a dynamic random memory (DRAM) region of the semiconductor substrate, forming an etch mask over the transistor region and the DRAM region, and patterning the etch mask over the second trench isolation structures to expose a portion of each of the second trench isolation structures with the transistor region remaining protected by the etch mask. A portion of the exposed portions is removed to form a gate trench in each of the second trench isolation structures, wherein each of the gate trenches include a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure. This embodiment further includes removing the etch mask from the DRAM region, rounding at least the first corner of each of the gate trenches, forming an oxide layer over a sidewall, the first rounded corner, and the semiconductor substrate adjacent each of the gate trenches, forming a gate oxide over the semiconductor substrate in the transistor region. Additional steps include filling each of the gate trenches with a gate material, the gate material extending over at least the first rounded corner and onto the semiconductor substrate adjacent each of the gate trenches, forming the gate material over the transistor region, patterning the gate material in the DRAM region and the transistor region to form gates, and forming source/drains adjacent the gates.
Yet another embodiment includes an integrated circuit device that includes transistors located in a transistor region of a semiconductor substrate and dynamic random access memory (DRAM) transistors located in a DRAM region of the semiconductor device, wherein each DRAM transistor includes an isolation trench wherein a portion of the isolation trench is a gate trench having a conductive gate material located therein, the gate trench having a first outside rounded corner formed by the semiconductor substrate. This device further includes an oxide layer located over a sidewall of the gate trench, the first outside rounded corner, and the semiconductor substrate adjacent the gate trench, the oxide layer having a thickness that ranges from about 2 nm to about 3 nm and has a thickness uniformity that varies by less than about 0.2 nm. Dielectric layers are located over the transistor regions and the DRAM regions, and interconnects are located over and within the dielectric layers that interconnect the transistors and the DRAM transistors.
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The semiconductor device 100 further includes a DRAM region 110. In this embodiment, the DRAM region 110 includes an embedded capacitor 112 that that has a capacitor electrode 114 comprised of a conductive material, such as a doped polysilicon. The electrode 114 is located within a gate trench 116 formed in an isolation region 118, which may have a thickness of about 40 nm. The gate trench 116, in the illustrated embodiment has first and second rounded corners 120 and 122, although in other embodiments, only the first rounded corner 120 may be present. The first rounded corner 120 is formed by the substrate 109 and the second rounded corner is formed by the isolation region 118. An oxide layer 124 is located over a sidewall of the trench 116 adjacent and on an upper surface of the substrate 109. Due to the presence of the rounded corner 120, the oxide layer 124 has improved uniformity and reduced leakage as compared to conventionally formed devices. Further, in those embodiments that include the second rounder corner 122, less stress is present in the capacitor electrode 114 at the point where the capacitor electrode 114 overlaps the isolation region 118 due to the presence of the second rounded corner 122. The DRAM region 110 further includes a doped source or drain region 126 located within a well 128 and a gate structure 130, all of which may be conventionally formed.
Following the etch process 310, the mask 210, the oxide layer 212, and the nitride layer 214 may be conventionally removed from at least the DRAM region 110, as seen in
In the embodiment where only the first rounded corner 412 is formed, the invention provides a device with reduced leakage because the rounded corner 412 allows for a more uniform growth of oxide over the rounded corner 412. In an alternative embodiment, further improvements are provided by the invention because the processes of the invention can provide good corner rounding for both the first corner 312 and second corner 314. This dual rounding provides not only a uniform oxide layer over the first corner 312 that reduces leakage, but rounding on the second corner 314 reduces stress on the gate electrode, which can reduce leakage and cracking or voiding of the gate material that covers the second corner 314. Thus, various embodiments of the invention provide improvements over conventional processes used to form buried capacitors in a DRAM device.
The oxide layer thickness in the transistor region 105 may vary, depending on whether the transistors are functioning as a high voltage device or as a core or low voltage device. Thus, the oxide layer in the transistor region 105 may have a different thickness than the oxide layer 510 in the DRAM region 110. In such instances, conventional processes may be used to form the appropriate thickness within the transistor region 105.
In
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Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
Singh, Ranbir, Rossi, Nace M., Yuan, Xiaojun
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