A passive frequency translator with positive conversion voltage gain including at least one input node for receiving an input signal, at least one output node for providing an output signal, and a network coupled to the at least one input node and to the at least one output node, in which the network includes multiple capacitors and switches operatively coupled thereto. The switches are controlled by corresponding clock signals to capture charge of the input signal onto the capacitors and to develop the output signal by performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal. The output signal has a net voltage gain relative to the input signal in which energy of the output signal is predominantly derived from energy of the input signal.
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8. A method of performing passive frequency translation, comprising:
receiving an input signal;
providing a plurality of switches operatively coupled to a plurality of capacitors;
controlling the plurality of switches to combine voltage samples to develop the output signal with a net voltage gain relative to the input signal and in which energy of the output signal is predominantly derived from energy of the input signal; and
wherein said controlling the plurality of switches includes performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal.
15. A method of downconverting an input signal having a first frequency to an output signal having a lower second frequency, the method comprising:
periodically charging a plurality of capacitors with respective charges derived from the input signal;
periodically updating the respective charge held by each of the plurality of capacitors by combining with the respective charge held by at least one other one of the plurality of capacitors;
periodically combining the updated charges held by one or more of the plurality of capacitors to provide an output signal having a net voltage gain relative to the input signal and having an energy which is derived predominantly from energy of the input signal; and
wherein said periodically charging, updating and combining comprises performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal.
1. A passive frequency translator with positive conversion voltage gain, comprising:
at least one input node for receiving an input signal and at least one output node for providing an output signal;
a network coupled to said at least one input node and to said at least one output node, wherein said network comprises a plurality of capacitors and a plurality of switches operatively coupled to said plurality of capacitors;
wherein said plurality of switches are controlled by a corresponding plurality of clock signals to capture charge of said input signal onto said plurality of capacitors and to develop said output signal by performing frequency translation of said input signal by a mixing frequency in such a manner that DC energy of said input signal is substantially blocked from said output signal; and
wherein said output signal has a net voltage gain relative to said input signal in which energy of said output signal is predominantly derived from energy of said input signal.
22. An electronic device, comprising:
a radio system, comprising:
an input circuit configured to receive a radio signal and to convert said radio signal into an input signal;
a passive frequency translator with positive conversion voltage gain, comprising:
at least one input node for receiving said input signal and at least one output node for providing an output signal;
a network coupled to said at least one input node and to said at least one output node, wherein said network comprises a plurality of capacitors and a plurality of switches operatively coupled to said plurality of capacitors;
a plurality of switches controlled by a corresponding plurality of clock signals to capture charge of said input signal onto said plurality of capacitors and to develop said output signal by performing frequency translation of said input signal by a mixing frequency in such a manner that DC energy of said input signal is substantially blocked from said output signal; and
wherein said output signal has a net voltage gain relative to said input signal in which energy of said output signal is predominantly derived from energy of said input signal; and
an output circuit for converting said output signal into a data signal; and
a host system coupled to said radio system for receiving and processing said data signal.
2. The passive frequency translator of
3. The passive frequency translator of
4. The passive frequency translator of
5. The passive frequency translator of
6. The passive frequency translator of
7. The passive frequency translator of
9. The method of
10. The method of
11. The method of
12. The method of
said receiving an input signal comprises receiving an input signal having a first frequency; and
wherein said controlling the plurality of switches comprises:
receiving a plurality of non-overlapping switching signals each having a predetermined duty cycle a respective frequency related to a predetermined base frequency; and
using the non-overlapping switching signals to control at least one switch to periodically charge at least two capacitors via the input signal, combine a respective charge held by each of the at least two capacitors with respective charges held by other ones of the at least two capacitors, and combine respective charges held by at least two of the at least two capacitors to construct the output signal having a second frequency.
13. The method of
generating at least one local oscillator signal having the base frequency; and
generating the plurality of non-overlapping switching signals from the at least one local oscillator signal.
14. The method of
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
21. The method of
periodically combining the updated charges held by one or more of the plurality of capacitors coupled in series; and
periodically combining the updated charges held by one or more of the plurality of capacitors coupled in anti-series.
23. The electronic device of
25. The electronic device of
26. The electronic device of
27. The electronic device of
28. The electronic device of
29. The electronic device of
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This application claims the benefit of U.S. Provisional Application Ser. No. 61/332,447, filed on May 7, 2010 which is hereby incorporated by reference in it entirety for all intents and purposes.
1. Field of the Invention
The present invention relates generally to circuit design, and, more particularly, to the design of passive mixer circuits having a positive voltage gain and a balanced DC mixing function.
2. Description of the Related Art
Typical radio frequency (RF) communications systems utilize mixers to shift, or translate, the frequency of an input signal (fIN) by mixing it with a Local Oscillator (LO) signal of a known frequency (fm). The frequency of the resulting output signal (fOUT) is either the sum or difference of fIN and fm (e.g. fOUT=|fIN+fm| or fOUT=|fIN−fm|), depending on whether the mixer is used for downconversion or upconversion. Mixers are typically used in both receivers and transmitters, oftentimes to perform downward frequency translation, which is commonly referred to as downconversion. Downconversion is useful in a receiver because it reduces the frequency of received signals, enabling any subsequent signal processing to be carried out at baseband or at an intermediate frequency (IF) where it is more tractable. Mixers are also used to perform upward frequency translation, commonly referred to as upconversion. Upconversion is useful in a transmitter because it enables shifting the modulated low-frequency data to higher frequencies where wireless transmission is more tractable.
Mixers can be passive and/or active mixer circuits, both types of mixer circuits being fairly common in current RF transceivers. Active type and passive type mixer circuits both come with their own advantages and disadvantages. Active mixer circuits consume DC bias current, while passive mixer circuits do not. One important advantage of active mixers, such as a Gilbert Cell, for example, is the relatively large conversion gain they typically provide, easing noise requirements and reducing the power consumption of subsequent stages. Active mixers, however, typically require substantial bias current and operating voltage headroom, and the active circuitry is also prone to generating (1/f) noise, which can be problematic in Low-IF and direct conversion receiver topologies. Furthermore, the downward scaling of voltage supplies and feature-sizes in the IC fabrication processes can exacerbate the voltage headroom and noise issues present in active mixers. Passive switching mixers, which typically use transistors configured to function as switches, can be used as an alternative to active mixers. Passive switching mixers offer inherently low power consumption because they do not consume DC bias current. Furthermore, they typically do not require voltage headroom to operate, generate significantly lower (1/f) noise than active mixers, and derive the output signal energy predominantly from the energy of the input signal. It should be noted, however, that in practice, energy from other undesired sources may also appear at the output, for example feed through from the LO signal and thermal noise. However, such undesired energy will affect most all implementations, including those featuring active mixers, thus the benefit of low power consumption when using passive mixers therefore remain substantial.
Overall, passive (switching) mixers can achieve linearity and noise performance levels comparable with those of active mixers, while consuming less power. Furthermore, the performance and power consumption of passive FET switching mixers can also improve with the scaling of field effect transistor (FET) technology (e.g. metal oxide semiconductor—MOS) fabrication processes (e.g., implemented with MOSFET devices). However, one notable disadvantage of passive mixers is their lack of conversion gain. As a matter of fact, an inherent property of passive frequency translation is actually signal power attenuation. Passive mixers can exhibit a conversion loss of 2 dB to 6 dB, which can offset the power consumption advantage of the passive mixer, as subsequent stages of a receiver (i.e. stages following the mixer) must achieve lower noise levels to maintain a given signal-to-noise ratio (SNR) with an attenuated signal level. Hence, subsequent stages typically need to consume more power to achieve a given system noise figure. It would therefore be advantageous to design mixers having the power saving advantages of passive mixers as well as the ability to achieve voltage conversion gain.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.
A passive frequency translator with positive conversion voltage gain according to one embodiment includes at least one input node for receiving an input signal, at least one output node for providing an output signal, and a network coupled to the at least one input node and to the at least one output node, in which the network includes multiple capacitors and switches operatively coupled thereto. The switches are controlled by corresponding clock signals to capture charge of the input signal onto the capacitors and to develop the output signal by performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal. The output signal has a net voltage gain relative to the input signal in which energy of the output signal is predominantly derived from energy of the input signal.
A method of performing passive frequency translation according to one embodiment includes receiving an input signal, providing switches operatively coupled to capacitors, controlling the switches to combine voltage samples to develop the output signal with a net voltage gain relative to the input signal and in which energy of the output signal is predominantly derived from energy of the input signal, and performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal.
A method of downconverting an input signal having a first frequency to an output signal having a lower second frequency according to one embodiment includes periodically charging capacitors with respective charges derived from the input signal, periodically updating the respective charge held by each of the capacitors by combining with the respective charge held by at least one other one of the capacitors, periodically combining the updated charges held by one or more of the capacitors to provide an output signal having a net voltage gain relative to the input signal and having an energy which is derived predominantly from energy of the input signal, and performing frequency translation of the input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal.
An electronic device according to one embodiment includes a radio system and a host system. The radio system includes an input circuit, an output circuit and a passive frequency translator with positive conversion voltage gain as described herein. The passive frequency translator performs frequency translation of an input signal by a mixing frequency in such a manner that DC energy of the input signal is substantially blocked from the output signal.
The foregoing, as well as other objects, features, and advantages of this invention may be more completely understood by reference to the following detailed description when read together with the accompanying drawings in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. Note, the headings are for organizational purposes only and are not meant to be used to limit or interpret the description or claims. Furthermore, note that the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not a mandatory sense (i.e., must).” The term “include”, and derivations thereof, mean “including, but not limited to”. The term “connected” means “directly or indirectly connected”, and the term “coupled” means “directly or indirectly connected.”
Various embodiments of passive frequency translation (PFT) circuits may present an improvement over basic voltage-mode passive mixer circuits by maintaining the advantages of basic voltage-mode passive mixers, while also effectively circumventing the conversion loss characteristic of basic passive mixers by providing substantial voltage conversion gain. Embodiments of such improved passive frequency translation circuits disclosed herein are referred to as Passive Frequency Translators with (positive conversion voltage) Gain, or PFTWGs for short. In various embodiments of PFTWGs, the voltage conversion gain may also be variable and/or programmable. Despite the negative power gain inherent in voltage-mode and current-mode passive frequency translation, voltage gain may actually be achieved by increasing the output impedance of the mixer circuit (e.g. through upward impedance transformation), which may not be problematic for low-IF (low intermediate frequency) or direct conversion receivers configured on integrated circuits (IC), where a relatively high mixer or frequency translator output impedance is typically acceptable. Further information of certain concepts and various equations listed herein are provided in US. Patent Application entitled “Passive Wireless Receiver”, Publication No. 2010/0144305, filed Dec. 5, 2008, which is incorporated herein by reference in its entirety.
One major advantage of passive switching mixers is their capacity for achieving linearity and noise performance levels comparable with those of active mixers, while consuming less power than active mixers. Various embodiments disclosed herein incorporate a passive frequency translation technique that maintains the advantages of conventional passive switching mixers, while effectively alleviating the problem of conversion power loss by providing substantial passive voltage gain, which, in certain embodiments, may even be programmable. The voltage gain may result in increased output impedance. Thus, while power loss may be unavoidable when using passive switching mixers, due to energy conservation, voltage gain may indeed be achieved by means of upward impedance transformation. In some embodiments such as those integrated in semiconductor technologies, the effect of varying impedances along the signal path may be well controlled and may not adversely affect important system metrics of interest.
Various embodiments of the passive frequency translator circuits with positive conversion voltage gain (PFTWG) disclosed herein may be configured in the front-end RF receiver(s) of any system featuring a front-end RF receiver(s). For example, some embodiments may be integrated into RF transceivers (transmitter/receiver) and transceiver ICs for communications systems or receivers, and receiver ICs in devices such as global positioning system (GPS) devices. These and other embodiments may be integrated into wireless headsets, wireless headphones, wireless “smart cards”, including credit, debit, membership and promotion cards, wireless sensors like motion detectors, security cameras, pressure gauges, light meters, and thermometers, and/or human interface devices such as video game controllers, computer mice or computer keyboards. They may also be integrated into cell-phones, either for wireless personal area networks (WPAN) and/or wireless local area networks (WLAN/WiFi), or as a primary voice and/or data transceivers using cellular voice and/or data networks and protocols like GPS, GPRS (general packet radio service), EDGE (enhanced data rates for GSM evolution, global system for mobile communications), 1xEV-DO (evolution-data optimized), WCDMA (wide-band code division multiple access), HSDPA (high-speed downlink passive access), HSUPA (high-speed uplink packet access), WiMAX/802.16e/802.16m (worldwide interoperability for microwave access), or 3GPP-LTE (3rd generation partnership project).
During operation, a PFTWG may receive an RF input signal having a first frequency (f1). The PFTWG may sample the voltage of the RF input signal at a sampling frequency (f0), which may be determined by a local oscillator (LO). In some embodiments, sampling performed by the PFTWG is facilitated by driving the PFTWG with multiple preferably non-overlapping switching signals (or clock signals) having a specific duty cycle and occurring at different times. The switching (clock) signals may be generated by a clock signal generator (CSG) circuit driven at a desired frequency by a local oscillator signal. The CSG-generated signals may periodically activate one or more switches within the PFTWG to couple the RF input signal to one or more capacitors, to periodically provide a portion of the RF input signal to each capacitor. The charge provided to each capacitor may be periodically held or combined with the respective charges held by one or more other capacitors, to effectively store voltage samples on the capacitors. The voltage samples stored on the capacitors may then be used to construct an output signal having a second frequency (f2) different than the local oscillator frequency and the RF input signal frequency. Various embodiments of PFTWGs disclosed herein may perform full rate sampling or sub sampling. For example, in some embodiments, the absolute value of the frequency of the generated output signal may be the absolute value of the difference between the frequency of the local oscillator and the frequency of the RF input signal. In other embodiments, the absolute value of the frequency of the generated output signal may be the absolute value of the difference between the frequency of the RF input signal and a multiple of the frequency of the local oscillator.
The output signal obtained by combining charge or transferring charge between the storage capacitors may exhibit a positive net voltage gain (in dB) relative to the RF input signal, while the energy of the output signal is derived primarily from the energy of the input signal. As used herein, a net positive voltage gain (in dB) produced in a system refers to the voltage amplitude of any single ended output signal—that is, the voltage amplitude of a signal at any one output terminal of the system—being greater than the voltage amplitude of any single ended input signal—that is, the voltage amplitude of a signal at any one of the system's input terminals. A bandpass filter may also be coupled to the input of the PFTWG to improve performance. Some embodiments may incorporate two PFTWGs, a first PFTWG operated as In-phase mixer, and a second PFTWG operated as Quadrature (I&Q) mixer, with both PFTWGs driven from a single RF input source.
In a first set of embodiments, a first type of dedicated frequency translator circuit is constructed from transistor/capacitor circuits that may be used in charge pumps. The component transistor/capacitor circuits may individually produce an output signal having the same frequency as the input signal. The first type of dedicated frequency translator receives an RF input signal and input clock signals. The fundamental mixing frequency fm of the first type frequency translator may be determined by the respective frequency of the input clock signals (mixing frequency). The output signal (which may be a baseband signal) produced by the first type translator circuit may have a frequency that is the difference of an integer multiple of the mixing frequency and the RF signal frequency, or it may have a frequency that is the difference of the mixing frequency and the RF signal frequency. The basic operation of the first type frequency translator circuit may include sampling the same input signal on two different phases of the input clock, with one sub-circuit having positive gain to the output, and the other sub-circuit having a negative gain to the output.
In a second set of embodiments, a second type of dedicated frequency translator circuit is constructed from switches and capacitors, and may be operated using multi-phase sequential switching. The input signal may undergo only a single sampling operation from input to output. The second type translation circuit is structured with a fixed stack of capacitors arranged to sum at the output the voltage samples collected on each individual capacitor, to produce the output signal. The RF input signal may be sampled onto just one of the capacitors on every one-half (½) cycle of the local oscillator (LO). The number of sampling phases delivered from the LO circuitry is equal to the total number of capacitors (n), and each sample may be stored and held on a capacitor for (n−1) ½ cycle of the LO before its voltage gets refreshed. The polarity of the RF input may be flipped every ½ cycle of the LO in order to implement a DC balanced mixing function. The second type translation circuit provides a voltage gain between output and input, based on the duty-cycle of the sampling clock signals and the number of capacitors.
In a third set of embodiments, a third type of dedicated frequency translator is constructed from switches and capacitors, and may be operated using multi-phase sequential switching and a reduced output refresh rate. The input voltage (of the input RF signal) may be captured at twice the rate of a local oscillator (LO) frequency (i.e. 2*fm), while the output voltage is refreshed at a frequency n times lower than twice the LO frequency (i.e. 2fm/n). The total number of capacitors in the circuit may be either 2n+2 for producing a serial output, or 2n+1 for a producing parallel output. The third type frequency translator circuit features 2n sampling phases and 2 evaluate phases, each having a fundamental frequency of fm/n. The capacitors may include a group of sampling capacitors and a holding capacitor. At the end of the n-th switching phase, the sampling capacitors may be switchably coupled to the holding capacitor in an anti-series configuration (that is, when the sampling capacitors and the holding capacitor are polar capacitors, the respective terminals of like polarity of the sampling capacitors are switchably coupled to each other) to obtain the output voltage. As a result of the anti-series coupling, the frequency translation may be performed with a DC balanced mixing configuration. The output refresh rate may be reduced to 2fm/n and fm/n, respectively, by combining the last n or 2n captured input samples prior to refreshing the output voltage.
In a fourth set of embodiments, another type of dedicated frequency translator, referred to as a “zigzag” mixer, is constructed from switches and capacitors, implemented using n stages, having either a single-ended input or differential inputs. The circuit with a single-ended input may have either a single-ended output or differential outputs. The single-ended input/output circuit may include 2n switches and 2n capacitors, while the single-ended input/differential output circuit may include 4n switches and 4n capacitors. Both circuits may operate with a 2-phase input clock. The maximum voltage gain of the circuit is 2n for the single-ended input/output circuit and 4n for the single-ended input/differential output circuit. A DC bias reference may be provided as a reference potential for the output voltage signal Vo. One distinguishing feature of this circuit is the input voltage connecting into the mixer through the capacitors and not through the switches, resulting in the DC level of the input voltage (of the input RF signal) and the DC level of the generated output voltage remaining independent of each other, allowing for DC biasing flexibility. In addition, since each even numbered node carries a baseband signal with substantially zero RF content, the effective voltage gain can be varied. In one set of embodiments, the effective voltage gain may be varied by using an analog multiplexer to select the node with the appropriate signal amplitude. For example, a multi-bit digital control signal may be used to select the desired node within the mixer circuit.
The same circuit described above may also be configured with a differential input, which may achieve slightly different voltage gain for a given number of stages. The primary difference in circuit topology may be implemented in the output stage, where, in order to extract a baseband signal with substantially zero RF content, the output capacitor may be referenced to a non-RF node, such as ground, or driven differentially. This circuit may be referred to as fully differential zigzag mixer circuit. Each numbered stage may contribute a gain of up to 2 V/V, while the output stage may add a gain up to 1 V/V, resulting in a fully differential circuit that can achieve a maximum voltage gain of 2n+1. Versions of a fully differential zigzag circuit that implement an unbalanced mixing function may be modified to implement a balanced mixing function by balancing the circuit dynamically with respect to the switching phases, and making it asymmetric statically with respect to the input terminals. The parasitics associated with the switches and capacitors may cause the balanced fully differential zigzag circuit to present an unbalanced load to the RF input. The two balanced, fully differential zigzag circuits may be arranged to present a quasi-symmetric load to the input by driving the two balanced, fully differential zigzag circuits from a single RF input in order to generate both, in-phase and Quadrature (I&Q) baseband output signals. Such a circuit may be symmetric in a dynamic sense, providing a balanced mixing function, but it may still be slightly asymmetric statically. A truly symmetric implementation may be constructed using two fully differential zigzag circuits with complementary local oscillator (LO) drives. The two complementary-clocked instances of the fully differential zigzag circuits have their inputs connected in parallel, while the outputs may be connected in parallel or in series.
Programmable gain and a distributed LO drive may also be implemented in the various embodiments that use the fully differential zigzag circuits. In one embodiment of such a circuit, the switching signal may be gated (for example by using an AND gate) into the respective control terminal of the switching transistors to effect switching only in the desired switches to adjust the overall output gain. The actual gain achieved in each setting may depend upon the duty cycle of the switching signal waveforms, among other factors. A digital input may be used to select the desired gain setting, using logic gates to decode the gain setting input and enable the appropriate portions of the circuit. The output capacitor may be varied in accordance with the selected gain input value in order to equalize the bandwidth of the circuit with respect to gain settings.
In a fifth set of embodiments, a dedicated frequency translator circuit may be constructed from switches and capacitors using n stages and having differential inputs and outputs. The circuit may comprise 2n+2 switches and 2n+1 capacitors, and may achieve a maximum voltage gain approaching 2n+1 for small values of D (where D is the duty-cycle of the switching signal). The topology of each stage of the circuit may include a pair of switches. A respective capacitor may be cross-coupled between each respective pair of switches, more specifically between a respective input terminal of a first switch of the pair of switches and a respective output terminal of the second switch of the pair of switches. Some embodiments of this circuit may not be fully symmetric with respect to the two sampling phases. For a symmetric implementation, a compound circuit may be constructed using two instances of the circuit respectively driven with complementary LO drives, with the two complementary-clocked instances of the circuit having inputs connected in parallel, and outputs connected in parallel or in series. With a parallel output connection, the maximum conversion gain of this complementary-clocked circuit is equivalent to the gain of the asymmetric version of the circuit. However, with a series output connection, the gain of the complementary-clocked circuit may increase by a factor of two.
In order to better understand operation of PFTWGs,
As shown in
When passive mixer 302 is operated in current-mode, mixer 302 receives a current signal as its input and produces a frequency translated output current (Io), as shown in
The output current Io of mixer 302 is the product of the equivalent mixing function m(t) (330, shown in
For frequency offsets that are very small relative to the LO frequency, the conversion gain of the current-mode passive switching mixer and its dependence on duty cycle (D) may be approximated by averaging the output current that results from a sinusoidal input that is perfectly in-phase with m(t), over one complete cycle of the LO, yielding the relationship in the following equation (1):
The conversion gain given by equation (1) may vary from its minimum value of zero (as D approaches zero), to its maximum value of 2/π, or about −4 dB (as D approaches ½). For maximum conversion gain, the duty cycle D of m(t) may be set to its maximum practical value that avoids overlap between the two phases 322 and 324. For example, Dmax may be set to ½.
When operated in voltage-mode (as shown in
The frequencies of input signal Vi and LO switching waveforms 322 and 324 can be very close, and considerably greater than the frequency of the downconverted output signal. Similar to the passive switching mixer operated in current-mode, the duty cycle D of the LO waveform may affect the magnitudes of mixing products present in the output signal Vo. The same mixing products may also be significantly impacted by the effective circuit time constant τs, as a result of the combinations of resistances and capacitances present in the circuit. The effective circuit settling time constant during sampling may therefore be expressed as:
τS=Reff·Ceff, (2)
where Reff is the effective lumped series resistance for a given mixer structure, typically incorporating the resistance of the source of the RF input signal (RS) and the on-resistance (RSW) of one or more switches in the circuit, and Ceff is the effective lumped shunt capacitance loading the input signal when a given switch is asserted. Unless specified otherwise in the descriptions of embodiments that follow, the settling time constant (τS) may be assumed to be large enough such that the settling of the input voltage(s) onto storage capacitor(s) during one sampling window is incomplete. This condition will be referred to as “incomplete settling” throughout. Thus, τS can be related to the conduction duty cycle D and the LO frequency (fm) by the expression provided in the following equation (2.1):
One significant difference between voltage-mode operation and current-mode operation is that the output signal is not characterized as the product of m(t) and the input signal Vi. Hence, the relationship between D and any conversion gain during voltage-mode operation is different from the relationship between D and conversion gain obtained during current-mode operation. The conversion gain GC of a voltage-mode passive mixer at zero Hertz (0 Hz) frequency offset may be derived for 0<D<0.5, assuming incomplete settling, as described above, as provided in the following equation (3):
As seen from equation (3), GC may have a maximum value of 1 as D approaches zero, and a minimum value of 2/π as D approaches 0.5. It should be noted that passive mixer 302, operated in voltage-mode as shown in
A passive mixer may be designed to have a singled-ended input and a differential-ended output, referred to herein as a single-balanced mixer. When operating a single-balanced mixer, both polarities of the single-ended input waveform may be processed on opposite phases of the LO waveforms, resulting in the differential output exhibiting an effective conversion voltage gain greater than unity, but not greater than a factor of two. The effective doubling of the conversion gain with respect to the conversion gain of a differential-input differential-output mixer is a direct result of converting a single-ended input to a differential-ended output. There is no voltage amplification from the input to any one side of the output signal and thus, there is no positive net voltage gain (in dB). However, the gain could be effectively doubled by taking the output as the combination of both anti-phase single-ended outputs, such that Vo=Vo1−Vo2, where Vo1 and Vo2 represent the single-ended outputs corresponding to phase 1 (φ1) and phase2 (φ2), respectively. However, as mentioned above, this does not represent a net voltage gain between any single input and any single output.
Therefore, the conversion gain of a single-balanced mixer distinguishes from the conversion gain Gc of a fully differential voltage-mode operated mixer defined in equation (3). For a single-balanced passive mixer, assuming incomplete settling, the single-ended input to differential-ended output voltage conversion gain, Gc,se-de may be given by the following equation (4):
For a voltage-mode operated passive mixer, for example mixer 302 in
where RS represents the source resistance of the voltage source, e.g. impedance 318 in the circuit shown in
Turning now to
CSG circuit 654 shown in
The overall operation of PFTWG 652 is highlighted in
The charge thereby derived from the RF input signal and provided to each capacitor is periodically held or combined with the respective charges held by one or more other capacitors, to effectively store voltage samples on the capacitors (1110). The charges from one or more of the capacitors are periodically combined construct a voltage-boosted baseband signal (1112). In other words, an output signal may be constructed using the stored voltages on the capacitors, such that the output signal has a different frequency (f2) than the LO frequency (f0) and the frequency of the RF input signal (f1). The absolute value of the frequency of the generated output signal (f2) may be the absolute value of the difference between the LO frequency and the frequency of the RF input signal (i.e. |f2|=|f1−f0|. As previously mentioned, the output signal obtained by combining charge or transferring charge between the storage capacitors may have a positive net voltage gain (in dB) relative to the RF input signal, with the energy in the output signal derived predominantly from the energy of the input signal. In various embodiments, a bandpass filter may be connected to the input of the PFTWG to improve performance. Some embodiments may incorporate two PFTWGs, a first PFTWG operated as In-phase mixer, and a second PFTWG operated as Quadrature (I&Q) mixer, with both PFTWGs driven from a single RF input source. It should be noted that as used herein, (polar) capacitors are said to be coupled or connected in anti-series when the respective terminals of the capacitors that are coupled to each other have identical polarities, whereas (polar) capacitors are said be coupled or connected in series when the respective terminals of the capacitors that are coupled to each other have opposite polarities.
As shown in
Referring again to
Circuits 700 and 750 achieve a voltage gain of up to n (V/V) without performing frequency translation, if the input signal frequency fin is below fm/2. However, if the input signal frequency exceeds fm/2, then circuits 700 and 750 may be operated to downconvert the input signal via aliasing about fm. Even though circuits 700 and 750 may be operated to perform frequency translation via aliasing, during such operation the input noise and other interference at low frequencies reach the baseband output without being translated. Therefore, it may be preferable to use circuits 700 and 750 as building blocks to construct a dedicated frequency translator circuit, as shown in
PFTWG circuits constructed using circuits 700 and/or 750 as building blocks may be operated to generate a single-ended output from a single-ended input, or provide single-ended to differential, and differential to single-ended conversion. Overall, circuits 800, 820 and 840 are all illustrative of embodiments of fully symmetric n-stage passive frequency translators with DC balanced mixing function m(t). Circuit 800 is representative of an embodiment featuring a differential input/output configuration with parallel output connection, circuit 820 is representative of an embodiment featuring a differential input/output with series output connection, and circuit 840 is representative of an embodiment featuring a single-ended input/differential output. One example of the sampling waveforms or clock signals φ1 and φ2 used to operate circuits 800, 820, and 840 is shown in
where Co is the output capacitance Cout. For the relationship shown in equation (6), the conversion gain of circuits 800, 820, and 840 near the m-th harmonic of fm may be expressed as shown in the following equations (7), (8) and (9):
for circuit 820, when m is an odd integer
for circuits 800 and 840, when m is an odd integer
Gc|f
for circuits 800, 820 and 840, when m is an even integer.
In contrast to circuits 700 and 750, circuits 800, 820, and 840 have maximum conversion gain for input frequencies near fm and zero gain at DC and for even harmonics of fm. Hence, circuits 800, 820, and 840 have the potential for significantly lower noise factor than circuits 700 and 750 used singly, due to reduced noise folding from the undesired harmonics of the sampling frequency.
The conversion gain of circuits 800, 820, and 840 has been described above with the assumption of incomplete settling at each phase of the local oscillator LO. For the purpose of illustration and derivation, it is useful to examine the behavior of circuits 800, 820, and 840 when equation 6 is not satisfied and the input signal does settle completely in a single sampling window as provided in the following equation (6.1):
With the assumption that equation (6.1) above is satisfied and complete settling is achieved, it is possible to obtain a compact difference equation relating the output voltage to the input voltage. Note that complete settling is typically impractical for the preferred embodiments described herein, but permits derivation of the difference equation which expresses certain intrinsic behaviors of circuits 800, 820, and 840, such as frequency translation about fm and the reduction in baseband bandwidth resulting from charge sharing between Ci and the output holding capacitor Cout, which hold true for the incomplete settling case as well. Assuming that capacitors C1-C2n all have an equal capacitance value of CS, and that equation (6.1) is satisfied, the difference equation for circuit 800 may be given according to the following equation (10):
where the effective sampling rate is 2fm.
The term (−1)k in equation (10) accounts for the two switching circuits within circuit 800 being connected to the input with opposite polarity and complementary LO phasing, which results in circuit 800 performing frequency translation with a DC balanced m(t). Hence, circuit 800 exhibits a maximum conversion gain for input frequencies near fm, and has substantially zero conversion gain at DC and at all even harmonics of fm. Furthermore, because the current value of the output voltage (Vo[k]) depends on the input voltage as well as the previous value of the output voltage (Vo[k−1]), the baseband frequency response of circuit 800 exhibits infinite impulse response (IIR) characteristics. The IIR effect may be the result of charge sharing between Ci and the output capacitor Cout, and may cause the bandwidth of circuit 800 to decrease as Cout increases, even if the source resistance (RS) and switch resistances (RSW) are negligibly small, (i.e. equation (6.1) is satisfied). Although not included herein, using the same assumptions as above, similar expressions may be derived for circuits 820 and 840.
In one set of embodiments, circuit 820 may be implemented using NMOS transistor for the switches, with five switches (Sij) and five capacitors (Ci), i.e. with n=4. The NMOS transistors, which may be fabricated using a 65 nano-meter (nm) process, may be sized to achieve an on-resistance (i.e. the value of RSW when the transistor turns on) of about 80 Ohms (Ω) each.
The practical limits on the magnitude of the conversion gain achievable with circuits 800, 820, and 840 depend upon the bandwidth for a given application, as well as the quality of the circuit's constituent components. For example, the bottom-plate parasitic of each capacitor and the parasitic capacitances associated with each switch may reduce the bandwidth and/or conversion gain below their ideal values. For embodiments of circuits 800, 820, and 840 implemented using CMOS transistors, these limitations may be partially overcome through the use of finer geometries, which may reduce the parasitic capacitances associated with the switches, and the use of capacitors having low bottom-plate parasitics, such as metal-insulator-metal (MIM) capacitors.
The maximum voltage gain of circuit 900 is n (V/V), and assuming incomplete settling, the gain has a sampling duty-cycle dependence approximated by the following equation (11):
where n is an even integer. While the general operating principle of circuit 900 is applicable to any integer value of n, even-values of n may result in a much simpler and more practical implementation. For the purpose of illustration and derivation, it is useful to examine the behavior of circuit 900 when the input signal does settle completely in a single sampling window (equation (12) below). When the source resistance (RS) and switch resistances (RSW) are sufficiently small for the signals to completely settle during each sampling window, the effective circuit time constant (τS) may be related to the duty-cycle and frequency of the LO as shown in the following equation (12):
In this case, the voltage on each capacitor Ci within circuit 900 tracks the input during clock phase φi, and this voltage is held on Ci until it is refreshed on φi+n. If equation (12) is satisfied, the output voltage may be approximated as a function of the input voltage using the following discrete-time difference equation (13):
Vo[k]=(−1)k*(Vi[k]−Vi[k−1]+Vi[k−2] . . . −Vi[k−(n−1)]), (13)
where the sampling frequency is 2*fm. The term (−1)k in equation (13) accounts for the toggling polarity of the input voltage, resulting in circuit 900 performing frequency translation with a DC balanced m(t). As a result, circuit 900 may achieve a maximum conversion gain for input frequencies near fm and may have zero conversion gain at DC, and at all even harmonics of fm.
Because the output of circuit 900 depends on the last n collected samples, with each sample having equal weight (or weighted equally), the frequency response exhibits zero-amplitude notches occurring at the input frequencies given by the following equation (14):
However, if equation (12) is not satisfied, as will typically be the case in the context of the present disclosure, that is, when the signals do not completely settle during each sampling window, the bandwidth of circuit 900 may decrease as τS increases. In this case, the relationship between the input signal and output signal may become significantly more complex than what is provided in equation (13), but the maximum achievable gain, the balanced mixing function, and the zero-amplitude notches may still be preserved.
The impact of increasing τS (i.e. effecting incomplete signal settling) on the frequency response of circuit 900 is illustrated in
One undesired effect of circuit 900 is the transfer function of the differential RF signal input to the common-mode level of the output signal. To minimize common-mode swing at the output, the input of circuit 900 may be driven from a differential source having very high common-mode impedance to ground, while the output of circuit 900 may be configured to have low common-mode impedance to ground at high frequencies. As a result, circuit 900 may be particularly sensitive to common-mode input capacitance, especially as n becomes large. However, various embodiments of circuit 900 may still operate as low-power, low-noise PFTWGs.
Once again, assuming the signals do not completely settle during each sampling window, the relationship between 0 Hz (zero Hz) offset conversion gain and the duty-cycle of the LO may expressed as the following equation (15):
for circuit 1000 (producing a parallel output), and as the following equation (16):
for circuit 1050 (producing a series output).
Circuit 1000 is configured with 6n+2 switches 2n+1 capacitors for producing parallel output, and circuit 1050 is configured with 6n+2 switches and 2n+2 capacitors to produce a series output. As shown in the timing diagram of
As a result of the anti-series connection described above, circuits 1000 and 1050 affect frequency translation with a DC balanced mixing function m(t). In addition, because circuit 1000 combines the last n captured input samples, and circuit 1050 combines the last 2n captured input samples before refreshing the output voltage, the output refresh rate is reduced to 2fm/n for circuit 1000, and fm/n for circuit 1050. For the purpose of illustration and derivation, it is useful to examine the behavior of circuits 1000 and 1050 when the input signal does settle completely in a single sampling window. Although in practice the values of the LO frequency, source resistance (RS), and switch resistance (RSW) typically prevent the input voltage from completely settling onto Ci during a given LO phase φi, a compact difference equation relating the output voltage to the input voltage may also be obtained for the case of complete settling, because even with the simplifying assumption of complete settling, the difference equation still adequately characterizes certain fundamental behaviors of circuits 1000 and 1050, such as frequency translation about fm and the appearance of nulls in the baseband output transfer function.
Assuming that each switch in circuits 1000 and 1050 has an on-resistance RSW (i.e., the effective resistance of the switch when it turns on is RSW), capacitors C1-C2n in circuits 1000 and 1050 all have an equal capacitance value of CS, and equation (12) is satisfied, the difference equation for circuit 1000 may be given as the following equation (17):
The term (−1)j in equation (17) reflects the anti-series configuration of the capacitors Ci as they are connected to Cout, and may affect frequency translation from the input to the output about the LO frequency fm. Equation (17) also captures the IIR response of circuit 1000 resulting from charge sharing between Ci and Cout. Therefore, as the value of Cout is increased relative to Ci (i.e. relative to CS), the output bandwidth of circuit 1000 may decrease. The summation term in equation (17) captures the dependence of the output voltage on the last n voltages that were captured from the input source and stored on the respective capacitors. As a result, a first null in the baseband output transfer function coinciding with the input frequencies fin may be expressed by the following equation (18):
Under the same set of assumptions as given above, an approximate difference equation for circuit 1050 may be obtained according to the following equation (19):
Equation (19) essentially models the same behaviors as equation (17), such as frequency translation, output refresh rate reduction, and IIR effects due to charge sharing. The difference between equations (17) and (19) results from the fact that the output voltage of circuit 1050 depends on the last 2n voltages captured from the input, whereas the output voltage of circuit 1000 depends on the last n voltages captured from the input. Therefore, the first nulls in the baseband output transfer function for circuit 1050 occur at lower offset frequencies, and circuit 1050 also achieves twice the conversion gain of circuit 1000. The first null in the baseband output transfer function for circuit 1050 may be expressed as the following equation (20):
Similar to circuits 800, 820, 840, and 900, embodiments of circuits 1000 and 1050 may include switches implemented with NMOS transistors. To illustrate operation of circuits 1000 and 1050, circuit 1050 may be specified with NMOS transistors for the switches, with n=4. The value source resistor RS may be set to 50Ω, and the gate width of the 65 nm NMOS transistors may be chosen to achieve an on-resistance (RSW) value of approximately 10Ω.
The value of the two output capacitors Cout (shown as Cout(1) and Cout(2) in
Practical limits on the magnitude of the conversion gain achievable with circuits 1000 and 1050 largely depends on the bandwidth for a given application, in addition to the quality of the actual circuit components. For example, the bottom-plate parasitic of each capacitor and the various parasitic capacitors associated with each switch generally reduces bandwidth and/or conversion gain below the ideal, or nominal (calculated and/or expected) values. In the case of embodiments in which the switches are implemented using CMOS transistors, these limitations may be somewhat relaxed by using finer geometries to reduce switch parasitics, and by using capacitors with low bottom-plate parasitics, such as metal-insulator-metal (MIM) capacitors.
As previously discussed for conventional voltage-mode passive mixers, single-ended to differential conversion allows an effective doubling of voltage gain by generating two output signals with an anti-phase relationship and using them as positive and negative inputs to a differential circuit (note again that this does not represent a net voltage gain, however). Hence, the maximum voltage gain of circuit 950 will be 2n for the single-ended output circuit and 4n for the differential output circuit. The input labeled Vref is a DC bias voltage provided as a reference potential for the output signal Vo. Signal ground (GND) may be used for biasing Vref, but other voltages may equally be used, provided they do not prevent proper operation of the switches within circuit 950. Furthermore, because the input V is only connected to circuit 950 through capacitors, the DC level of Vi and Vo may remain independent. This DC biasing flexibility is one distinct advantage of circuit 950 and any variants incorporating circuit 950, or versions thereof.
Assuming incomplete settling, as expressed in the following equation (21),
the conversion gain Gc at small frequency offsets may be approximated as a function of the duty-cycle D of the sampling signal, as shown in equations (22) for a single-ended output as shown in the following equation (22),
and in the following equation (23) for a differential output:
The conversion gain of an NMOS implementation of circuit 950 may be tracked versus frequency offset from fm for various values n and τS. The NMOS switches may be configured with equal dimensions (hence, equal resistance RSW) and the capacitors may be configured with equal CS values. The bandwidth of circuit 950 decreases as n, and thus voltage gain, is increased. This reduction occurs even for small values of τS, due to charge sharing between stages within the circuit. Higher order (e.g. n>1) variations of circuit 950 may rely upon multiple charge sharing stages to generate voltage gain, resulting in slower settling and thus, reduced bandwidth as gain increases. This gain-bandwidth tradeoff is also consistent with the effects of power conservation, which predicts passive voltage gain being accompanied by an increase in impedance.
The variation of bandwidth as a function of voltage gain in circuit 950 may need to be addressed when programmable gain is desired. For example, some embodiments may be directed to designs in which the bandwidth is held constant and independent of voltage gain. There may be at least two methods for dealing with bandwidth variation. A first, simpler method may build upon the fact that the voltage at the internal nodes of circuit 950 may remain in phase with the output node, but having lower amplitude. Furthermore, since each even numbered node Vn carries a baseband signal with substantially zero RF content, the effective voltage gain may be varied by using an analog multiplexer, for example, to select the node Vn with the appropriate signal amplitude. This is illustrated in
In one set of embodiments, to prevent premature distortion in low gain modes, the portion of the circuit dedicated to generating a higher gain than the desired value may be disabled. This may be accomplished using distributed LO drive circuitry with separate branches that may be independently disabled. The bandwidth in various gain modes may be equalized by adding output load capacitance as gain is decreased. This programmable gain method is illustrated by way of circuit 960 in
Single-ended input/output and single-ended input to differential output versions of circuit 950 have been discussed in some detail above. A differential input may also be obtained through minor modifications, resulting in a slightly different voltage gain for a given number of stages. The primary difference in circuit topology may be seen in the output stage. The modifications may be motivated by the fact that due to the differential RF input, all nodes within the circuit are exposed to the RF signal. In order to extract a low frequency, or baseband signal with substantially zero RF content, the output capacitor may be referenced to a non-RF node, such as ground, or driven differentially, as illustrated by circuit 954 in
Though circuit 954 is shown having differential inputs and outputs, and appears symmetric statically with respect to the input and output, it is not fully symmetric dynamically with respect to the two sampling phases φ1 and φ2. For example, for a 1-stage implementation of circuit 954, the maximum conversion gain is 2n+1=3. Stage 1 samples on φ1, storing the downconverted baseband signal on C1 and C2 with a gain of up to 2 V/V. The output stage captures both the baseband signal and the differential RF signal on φ2, and store the result on Co. The output stage, sampling on φ2, further increases the conversion gain by up to 1 VAT, while producing a baseband output signal with substantially zero RF content. Hence, voltage samples collected on φ1 have twice the gain with respect to the output than the voltage samples collected on φ2, creating, in effect, an unbalanced mixing function m(t). This imbalance may result in nonzero conversion gain for inputs near DC, and even for harmonics of fm.
Circuit 954 may be modified in order to create a balanced function m(t), as illustrated by circuit 956 in
Circuit 956 is symmetric in a dynamic sense, providing a balanced m(t), but may remain slightly asymmetric statically. A truly symmetric implementation may be obtained by constructing a circuit using two copies of circuit 954 with complementary LO drive. A circuit symbol for such a circuit 958 is shown in
and in the following equation (25) for a series output connection:
Circuit 960 in
An additional set of switches may be incorporated to extend the range of programmable voltage gain down to 1 V/V, as illustrated by circuit 962 in
In various implementations of circuits 954-960, the parasitic capacitance associated with the constituent switches and capacitors may affect circuit performance. The effect of these parasitics is analogous to those considered for circuits 1000 and 1050. The switch parasitics and bottom plates of capacitors C1-C2n may effectively appear in parallel with the RF input, potentially reducing conversion gain and degrading noise performance. One effective way to substantially decrease this parasitic sensitivity is by incorporating the capacitance into a resonant LC network tuned to fm at the input to the mixer as also mentioned for the single-ended input zigzag mixer (circuit 950). Circuit 966 in
In order to achieve a truly symmetric implementation, a circuit may be constructed using two instances of circuit 966, with complementary LO drives applied to the two instances of circuit 966.
As also previously noted, the noise performance of various embodiments of PFTWGs disclosed herein may be enhanced by incorporating a bandpass filter tuned to fm and coupled to the input of the PFTWG, due to reduction of input noise folding from harmonics of fm. It should be noted that any improvement sought by coupling a bandpass filter to the input of the PFTWG as mentioned above may greatly depend on the loss of the bandpass filter used. In addition, the bandpass filter may incorporate passive voltage gain, which may boost the impedance of the input source and permit a reduction in the size of the switches and capacitors of the PFTWG while still achieving the desired noise reduction. Finally, achieving substantial voltage gain while using a passive frequency translator facilitates the use of more unconventional low-power RF receiver front-ends, e.g. RF receiver front ends that do not feature a low-noise amplifier (LNA—for example, alternate embodiments to the RF front-end shown in
Although the embodiments above have been described in considerable detail, other versions are possible. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. Note the section headings used herein are for organizational purposes only and are not meant to limit the description provided herein or the claims attached hereto.
Cook, Benjamin W., Berny, Axel D.
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