A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other.
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1. A method for comparing two input signals, comprising:
receiving a first input signal and a second input signal;
comparing the first and second input signals;
generating an output signal having a first logical state indicating the second input signal is greater than the first input signal and having a second logical state indicating the first input signal is greater than the second input signal;
in response to each logical state transition of the output signal, introducing a hysteresis to the first or second input signal that is the smaller input signal after the output signal switches logical states; and
keeping the hysteresis on the smaller input signal after each logical state transition of the output signal when the first and second input signals are within a predetermined signal range of each other, the predetermined signal range being a portion of the full signal range of the first and second input signals.
8. A bi-directional comparator, comprising:
a first comparison circuit configured to receive a first input signal and a second input signal and to compare the first and second input signals, the first comparator generating an output signal having a first logical state indicating the second input signal is greater than the first input signal and having a second logical state indicating the first input signal is greater than the second input signal; and
a second comparison circuit configured to receive the first and second input signals and, in response to each logical state transition of the output signal, to introduce a hysteresis to the first or second input signal that is the smaller input signal after the output signal switches logical states and to keep the hysteresis on the smaller input signal after each logical state transition of the output signal when the first and second input signals are within a predetermined signal range of each other, the predetermined signal range being a portion of the full signal range of the first and second input signals.
2. The method of
removing the hysteresis on the first input signal or the second input signal prior to the next logical state transition of the output signal when the first input signal and the second input signal are outside of the predetermined signal range of each other.
3. The method of
generating first and second comparison signals related to the first and second input signals, respectively, the first comparison signal being the first input signal or the first input signal with hysteresis added and the second comparison signal being the second input signal or the second input signal with hysteresis added;
comparing the first and second comparison signals;
when the first comparison signal becomes greater than the second comparison signal, switching the logical state of the output signal from the first logical state to the second logical state; and
when the second comparison signal becomes greater than the first comparison signal, switching the logical state of the output signal from the second logical state to the first logical state.
4. The method of
when the output signal switches to the second logical state, adding the hysteresis to the second input signal;
when the output signal switches to the first logical state, adding the hysteresis to the first input signal; and
keeping the hysteresis on the first or second input signal when the first input signal and the second input signal are within the predetermined signal range of each other.
5. The method of
6. The method of
removing the hysteresis on the first input signal or the second input signal prior to the next logical state transition of the output signal when the first input signal and the second input signal are outside of the predetermined signal range of each other.
7. The method of
9. The bi-directional comparator of
10. The bi-directional comparator of
a first comparator configured to receive a first comparison signal and a second comparison signal related to the first and second inputs, respectively, the first comparison signal being the first input signal or the first input signal with hysteresis added, and the second comparison signal being the second input signal or the second input signal with hysteresis added, the first comparator generating the output signal,
wherein the first comparator compares the first and second comparison signals; and when the first comparison signal becomes greater than the second comparison signal, the first comparator switches the logical state of the output signal from the first logical state to the second logical state; and when the second comparison signal becomes greater than the first comparison signal, the first comparator switches the logical state of the output signal from the second logical state to the first logical state.
11. The bi-directional comparator of
12. The bi-directional comparator of
13. The bi-directional comparator of
14. The bi-directional comparator of
15. The bi-directional comparator of
a second comparator configured to receive the first input signal lowered by the predetermined signal range and the second input signal, the second comparator generating an output signal indicating whether the difference between the first input signal and the second input signal is greater than the predetermined signal range;
a third comparator configured to receive the second input signal lowered by the predetermined signal range and the first input signal, the third comparator generating an output signal indicating whether the difference between the second input signal and the first input signal is greater than the predetermined signal range;
a flip-flop having a set input terminal driven by the output signal of the third comparator and a reset input terminal driven by the output signal of the second comparator, the flip-flop generating an output signal; and
a logic circuit configured to receive the output signal of the flip-flop and the output signal of the first comparator, the logic circuit generating control signals to control the addition of hysteresis to the first and second input signals.
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The invention relates to bi-directional comparators and, in particular, to a bi-directional comparator with accurate thresholds and hysteresis in both rising and falling directions
A dual input power selector, also referred to as a “diode OR'ing controller”, is typically used in a hot swap device which receive two input power supplies to select the higher of the two as the output power supply in an automatic switch over mode. For example, the two input power supplies may be a plug-in power supply, a USB power source, or battery power supply. The power selector selects the higher of the two power supplies and connects the selected input power supply to a common output node.
To avoid chattering of the output signal when the two input signals are closed in values, conventional power selectors are implemented using a hysteretic comparator.
When a power selector is implemented using a hysteretic comparator, the hysteresis ΔV added to both sides of the comparison threshold VREF creates an offset in the comparison threshold. Such comparison offset is undesirable in power selectors.
According to one embodiment of the present invention, a method for comparing two input signals includes receiving a first input signal and a second input signal; comparing the first and second input signals; generating an output signal having a first logical state indicating the second input signal is greater than the first input signal and having a second logical state indicating the first input signal is greater than the second input signal; when the output signal switches logical state, introducing a hysteresis to the first or second input signal that is the smaller input signal after the output signal switches logical states; and keeping the hysteresis on the smaller input signal when the first and second input signals are within a given signal range of each other.
According to another aspect of the present invention, a bi-directional comparator includes a first comparison circuit configured to receive a first input signal and a second input signal and to compare the first and second input signals where the first comparator generates an output signal having a first logical state indicating the second input signal is greater than the first input signal and having a second logical state indicating the first input signal is greater than the second input signal; and a second comparison circuit configured to receive the first and second input signals. When the output signal switches logical state, the second comparison circuit is configured to introduce a hysteresis to the first or second input signal that is the smaller input signal after the output signal switches logical states and to keep the hysteresis on the smaller input signal when the first and second input signals are within a predetermined signal range of each other.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
In accordance with the principles of the present invention, a bi-directional comparator compares two input signals and applies a hysteresis level only after the output signal switches logical states and when the two input signals are within a given range of each other. The hysteresis level as thus applied prevents chattering of the output signal of the comparator. In this manner, accurate comparison of the two input signals is achieved in both rising and falling directions without any comparison offset. In one embodiment, the hysteresis level is applied only to the smaller of the two input signals after the output signal switches logical states and the hysteresis level is removed after the two input signals are outside of the given range of each other. In some applications, the bi-directional comparator is applied in a power selector to select one of two input power supplies.
When signal INA_comp becomes greater than signal INB_comp, the comparison output signal OUT switches logical states from a logical low to a logical high. In that case, the method 100 introduces a hysteresis to input signal INB which is now the smaller input signal (step 108). More specifically, the hysteresis in the form of a negative threshold is added to the input signal INB by setting the comparison signal INB_comp a threshold VT lower than the input signal INB. That is, the signal INB_comp is set to INB−VT.
When signal INB_comp becomes greater than signal INA_comp, the comparison output signal OUT switches logical states from a logical high to a logical low. In that case, the method 100 introduces a hysteresis to input signal INA which is now the smaller input signal (step 110). More specifically, the hysteresis in the form of a negative threshold is added to the input signal INA by setting the comparison signal INA_comp a threshold VT lower than the input signal INA. That is, the signal INA_comp is set to INA−VT. From steps 108 and 110, the method 100 then returns to step 104 where the comparison output signals are being generated for use in the comparison step 106.
Meanwhile, method 100 proceeds to monitoring the two input signals to determine if they are within a given range of each other. To that end, from step 108, method 100 performs a second comparison step to determine if the difference between INA and INB (INA−INB) is greater than a given signal range ΔV (step 112). In some embodiments, the second comparison step 112 may be performed by a comparator COMP2. When INA−INB is greater than the given signal range ΔV, the hysteresis introduced on input signal INB is removed and the comparison signal INB_comp is now set equal to INB (step 116). When INA−INB is within the given signal range ΔV, the hysteresis applied to signal INB is kept (step 114) and method 100 continues to monitor whether INA−INB is still within the given signal range ΔV.
From step 110, method 100 performs a third comparison step to determine if the difference between INB and INA (INB−INA) is greater than the given signal range ΔV (step 118). In some embodiments, the third comparison step 118 may be performed by a comparator COMP3. When INB−INA is greater than the given signal range ΔV, the hysteresis introduced on input signal INA is removed and the comparison signal INA_comp is now equal to INA (step 122). When INB−INA is within the given signal range ΔV, the hysteresis applied to signal INA is kept (step 120) and method 100 continues to monitor whether INB−INA is still within the given signal range ΔV. When the input signals are outside of the given range ΔV of each other and the hysteresis is removed (step 116 or 122), method 100 returns to step 104 where the comparison output signals are being generated for use in the comparison step 106.
A current source 19 is connected to node 17 to supply a current IB to resistor R1. A switch S1 is connected in parallel with resistor R1. When switch S1 is open, the current IB flows in resistor R1 and the voltage level of comparison signal INA_comp (node 17) is pull down by a voltage amount VT as a function of the resistance of resistor R1 and current IB, that is VT=R1*IB. A negative threshold or hysteresis is added to the input signal INA by setting the comparison signal INA_comp a threshold level below the input signal INA. When switch S1 is closed, resistor R1 is bypassed and the comparison signal INA_comp is equal to the input signal INA. The switch S1 is controlled by a signal rm_hyA which is asserted to close switch S1 when the hysteresis on input signal INA is to be removed. In the present embodiment, the switch resistance is assumed to be 0.
A current source 18 is connected to node 16 to supply a current IB to resistor R2. A switch S2 is connected in parallel with resistor R2. When switch S2 is open, the current IB flows in resistor R2 and the voltage level of comparison signal INB_comp (node 16) is pull down by a voltage amount VT as a function of the resistance of resistor R2 and current IB, that is VT=R2*IB. A negative threshold or hysteresis is added to the input signal INB by setting the comparison signal INB_comp a threshold level below the input signal INB. When switch S2 is closed, resistor R2 is bypassed and the comparison signal INB_comp is equal to the input signal INB. The switch S2 is controlled by a signal rm_hyB which is asserted to close switch S2 when the hysteresis on input signal INB is to be removed. In the present embodiment, the switch resistance is assumed to be 0.
The comparators in the auxiliary comparison circuit are also coupled to receive the input signals INA and INB. At comparator 12, the input signal INA is coupled through a resistor R4 to the positive input terminal 22 while the input signal INB is coupled directly to the negative input terminal of the comparator 12. At comparator 13, the input signal INB is coupled through a resistor R3 to the positive input terminal 23 while the input signal INA is coupled directly to the negative input terminal of the comparator. A current source 24 is connected to node 22 to supply a current IB to resistor R4. A current source 25 is connected to node 23 to supply a current IB to resistor R3. When a current IB flows through resistor R3 or resistor R4, the voltage at the respective node (22, 23) is pull down by a voltage amount ΔV as a function of the resistance of resistor R3/4 and current IB, that is ΔV=R3/4*IB. In the embodiments of the present invention, resistors R1, R2, R3 and R4 can have the same or different resistance values. Resistors R1 and R2, together with current IB, determine the hysteresis level VT to be applied to the input signal. Resistors R3 and R4, together with current IB, determine the voltage range ΔV for applying or removing the hysteresis level VT.
The comparator 12 generates an output signal INAH driving the Reset input terminal 26 of flip-flop 30. The comparator 13 generates an output signal INBH driving the Set input terminal 27 of flip-flop 30. The flip-flop 30 generates an output Q (node 32). Thus, when the signal INBH is asserted, the output Q of flip-flop 30 is asserted (logical high). When the signal INAH is asserted, the output Q of flip-flop 30 is deasserted (logical low).
The output signal OUT of the main comparator 11 and the output signal Q of flip-flop 30 are coupled to a logic circuit including an OR gate 34 and an NAND gate 36. OR gate 34 generates the rm_hyA signal which controls the removal of the hysteresis on input signal INA. NAND gate 36 generates the rm_hyB signal which controls the removal of the hysteresis on input signal INB.
The operation of the auxiliary comparators in the bi-directional comparator 10 of
When input signals INA and INB are within the given voltage range ΔV of each other, both output signals INAH and INBH are at a logical low state. The flip-flop 30 does not change state when both of its inputs are at the logical low value. Thus, when the input signals INA and INB are within a voltage range ΔV of each other, the previously set logical state for output signal Q still applies.
The output signal Q of the flip-flop 30 together with the output signal OUT of the main comparator 11 are used to generate remove hysteresis control signals rm_hyA and rm_hyB. Referring to the logic table in
When input signal INA becomes greater than input signal INB and the two input signals are within the given voltage range ΔV, the flip-fop 30 does not change state while the comparator output OUT switches to a logical high state. The remove hysteresis control signal rm_hyA remains at a logical high while the remove hysteresis control signal rm_hyB switches to a logical low. Switch S1 remains closed while switch S2 is now open. In this manner, hysteresis is applied to the input signal INB so that the comparison signal INB_comp is now a threshold voltage level VT lower than signal INB.
When input signal INA is greater than input signal INB by more than the given voltage range ΔV, the flip-fop 30 is in the Reset state and the comparator output OUT is at a logical high. The remove hysteresis control signals rm_hyA and rm_hyB are both logical high to close switches S1 and S2. In this manner, all hysteresis on the input signals are removed and the comparison signals are the same as the input signals.
Finally, when input signal INB becomes greater than input signal INA and the two input signals are within the given voltage range ΔV, the flip-fop 30 does not change state while the comparator output OUT switches to a logical low state. The remove hysteresis control signal rm_hyB remains at a logical high while the remove hysteresis control signal rm_hyA switches to a logical low. Switch S2 remains closed while switch S1 is now open. In this manner, hysteresis is applied to the input signal INA so that the comparison signal INA_comp is now a threshold voltage level VT lower than signal INA.
The operation of the bi-directional comparator 10 of
As shown in
As input signal INA rises towards signal INB until the input signals INA and INB are within a voltage range ΔV of each other, the comparator 13 deasserts its output INBH. Flip-flop 30, with both inputs at a logical low, will not change state. Thus, the output Q remains asserted. When input signal INA crosses over input signal INB at time T1, the output signal OUT changes from a logical low state to a logical high state, selecting the input signal INA. When the output signal OUT changes state to a logical high state, the remove hysteresis control signal rm_hyB becomes deasserted so that switch S2 is now open. Current IB flows in resistor R2 so that the signal INB_comp is pulled down by a voltage value VT from the signal INB. In this manner, a hysteresis VT is introduced to the signal INB, as shown by the dip in the comparison signal INB_comp (curve 58) in
The hysteresis is applied to input signal INB until the two signals are no longer within the voltage range ΔV of each other, as denoted by time T1′. More specifically, when input signal INA increases beyond INB by the given voltage range ΔV, the comparator output INAH (comparator 12) is asserted to a logical high state. The flip-flop 30 is now in a Reset state and the output signal Q is deasserted. The remove hysteresis control signal rm_hyB becomes asserted (logical high) to close switch S2 and bypass resistor R2. The comparison signal INB_comp is now equal to the input signal INB.
Then, at time T2, the input signal INA has not changed but the input signal INB has now increased and has crossed over signal INA. The output signal OUT of the main comparator 11 switches to the logical low state, selecting input signal INB. The flip-flop 30 was previously set to the Reset state with the output Q at a logical low. When the output signal OUT changes state to a logical low state, the remove hysteresis control signal rm_hyA becomes deasserted so that switch S1 is now open. Current IB flows in resistor R1 so that the signal INA_comp is pulled down by a voltage value VT from the signal INA. In this manner, a hysteresis VT is introduced to the signal INA, as shown by the dip in the comparison signal INA_comp (curve 60) in
The hysteresis is applied to input signal INA until the two signals are no longer within the voltage range ΔV of each other, as denoted by time T2′. More specifically, when input signal INB increases beyond INA by the given voltage range ΔV, the comparator output INBH (comparator 13) is asserted to a logical high state. The flip-flop 30 is now in a Set state and the output signal Q is asserted. The remove hysteresis control signal rm_hyA becomes asserted (logical high) to close switch S1 and bypass resistor R1. The comparison signal INA_comp is now equal to the input signal INA.
The operation of the bi-directional comparator 10 continues in the same manner to apply a hysteresis to the smaller input signal after the output signal OUT changes logical state. Thus, at time T3, the input signal INB has dropped below input signal INA. The output signal OUT switches to a logical high and a hysteresis is applied to the input signal INB so that INB_comp is pulled down by a voltage value VT from the signal INB, as shown in
Finally, at time T5, the input signal INA has increased above input signal INB. The output signal OUT switches to a logical high and a hysteresis is applied to the input signal INB so that INB_comp (curve 58) is pulled down by a voltage value VT from the signal INB, as shown in
The bi-directional comparator of the present invention allows accurate comparison of the input signals in both the rising and falling directions, without any comparison offset. The comparator applies hysteresis only after the output signal changes state to prevent chattering of the output signal.
The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.
Jackson, Cameron, Casey, Charles A., Zhu, Richard
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 6229350, | Dec 30 1997 | Texas Instruments Incorporated | Accurate, fast, and user programmable hysteretic comparator |
| 7087223, | Mar 13 2000 | Hisamitsu Pharmaceutical Co., Inc. | Preventives and/or remedies for hyperphosphatemia |
| 7187223, | Feb 14 2005 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Comparator with hysteresis |
| 7236030, | Jun 30 2004 | Texas Instruments Incorporated | Method to implement hysteresis in a MOSFET differential pair input stage |
| 7595676, | Jul 23 2007 | Texas Instruments Incorporated | Comparator and method with controllable threshold and hysteresis |
| 7893768, | Mar 10 2009 | Texas Instruments Incorporated | Automatic gain control |
| 7902894, | Jun 26 2009 | Alpha and Omega Semiconductor Inc.; Alpha & Omega Semiconductor, Inc | Accurate hysteretic comparator and method |
| 8269527, | Sep 08 2009 | Ricoh Company, Ltd. | Hysteresis comparator circuit and semiconductor device incorporating same |
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