Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.
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1. A charge pump circuit comprising:
a step-up capacitor comprising a first capacitance and a second capacitance coupled in series with each other;
a capacitance driver operable to generate a step-up voltage by driving the step-up capacitor; and
a protection circuit coupled to a series coupling node of the first capacitance and the second capacitance,
wherein, when the step-up voltage is not generated, the protection circuit is set in a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, and when the step-up voltage is generated, the protection circuit is maintained in a non-conductive state,
wherein the protection circuit comprises a diode coupled to the series coupling node of the first capacitance and the second capacitance,
wherein the charge pump circuit further comprises a control circuit operable to control potential of a cathode of the diode, and
wherein, when the step-up voltage is not generated, the control circuit controls the cathode of the diode to a low level, and when the step-up voltage is generated, the control circuit controls the cathode of the diode to a high level.
2. The charge pump circuit according to
wherein the diode is a pn junction diode in which a p-type diffusion layer and an n-type diffusion layer in an n-well region are joined, and an anode of the pn junction diode is coupled to the series coupling node of the first capacitance and the second capacitance.
3. The charge pump circuit according to
wherein the protection circuit comprises a switch by means of an MOS transistor coupled to the series coupling node of the first capacitance and the second capacitance.
4. The charge pump circuit according to
a control circuit operable to control operation of the switch by means of the MOS transistor.
5. The charge pump circuit according to
wherein, when the step-up voltage is not generated, the control circuit controls the switch to a conductive state, and when the step-up voltage is generated, the control circuit controls the switch to a non-conductive state.
6. The charge pump circuit according to
wherein the step-up capacitor comprising the first capacitance and the second capacitance coupled in series with each other is formed with lamination of a first polysilicon layer and a second polysilicon layer, with an insulating film interposed therebetween, over the well region.
7. The charge pump circuit according to
wherein the first capacitance and the second capacitance are a monolayer capacitor comprised of lamination of a polysilicon layer with an interposing insulating film over the well region.
8. The charge pump circuit according to
wherein the first capacitance and the second capacitance are an MIM capacitor comprised of lamination of an upper metal layer and a lower metal layer with an insulating film interposed therebetween.
9. A nonvolatile memory comprising:
a charge pump circuit according to
a memory array in which nonvolatile memory cells are arranged; and
a circuit operable to performs a read/write to the memory array using a step-up voltage generated by the charge pump circuit.
10. A data processing apparatus comprising:
a nonvolatile memory according to
a CPU operable to access the nonvolatile memory.
11. A microcomputer application system comprising:
a microcomputer operable to execute a predetermined control program,
wherein the microcomputer comprises the data processing apparatus according to
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The disclosure of Japanese Patent Application No. 2010-159489 filed on Jul. 14, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to improvement technology of a charge pump circuit, and to technology which is effective when applied to a power supply circuit of a nonvolatile memory, for example.
A semiconductor device using a nonvolatile memory is configured by a nonvolatile memory, its peripheral circuit, and others. A nonvolatile memory is provided with a floating gate, a control gate, etc. which are stacked over a substrate. In a semiconductor device using such a nonvolatile memory, various kinds of power supply for operating the nonvolatile memory and its peripheral circuit are generated by an internal power supply voltage generating circuit. Especially, a charge pump circuit is used for a step-up of high voltage.
A charge pump circuit includes a positive voltage step-up circuit and a negative voltage step-up circuit, as described in Patent Document 1 (paragraphs 0038-0052). According to Patent Document 1, capacitor structure of a charge pump circuit of a flash memory is configured by a capacitor C1 formed by an insulating film sandwiched between a first gate FG in the same layer as a floating gate and a second gate SG in the same layer as a control gate of a nonvolatile memory cell, and a capacitor C2 formed by an insulating film sandwiched between the first gate FG and a well region nwell. The second gate SG and the well region nwell are formed at the same potential, and the capacitor C1 and the capacitor C2 are coupled in parallel. The capacitor C1 and the capacitor C2 are stacked in a tandem structure.
(Patent Document Japanese Patent Laid-open No. 2001-085633
In such a charge pump circuit, an absolute value of voltage becomes larger at a step-up stage which is located nearer an output terminal of the charge pump circuit; therefore, it is important that voltage applied to a terminal of a capacitance (a “step-up capacitor”) in the step-up stage concerned is set not to exceed the destruction withstand voltage of the step-up capacitor concerned. As a measure of relaxing the withstand voltage, it is possible to form one step-up capacitor with two capacitors coupled in series, thereby suppressing an absolute value of voltage applied to per capacitor. The inventors of the present application examined such a relaxation measure for the withstand voltage and found out the following problems.
That is, when there is no suitable leakage path for a series coupling node (it is called an “intermediate node”) of the two capacitors coupled in series to form one step-up capacitor, undesirable electrification may take place to the intermediate node, inducing a possibility of device destruction due to the electrification. When there is a leakage path for the intermediate node of the two capacitors coupled in series to form one step-up capacitor, there is a possibility that pump efficiency of the charge pump circuit may fall due to leakage current which flows through the leakage path concerned.
The present invention has been made in view of the above circumstances and provides technology in which it is possible to avoid device destruction due to electrification of the intermediate node of plural capacitors coupled in series with each other to form one step-up capacitor, and in which it is possible to avoid falling of the pump efficiency due to the leakage current which flows through a leakage path of the intermediate node concerned.
The above and other purposes and new features will become clear from description of the specification and the accompanying drawings of the present invention.
The following explains briefly an outline of typical inventions to be disclosed by the present application.
That is, a charge pump circuit is configured by a step-up capacitor including a first capacitance and a second capacitance coupled in series with each other, a capacitance driver capable of generating step-up voltage by driving the step-up capacity; and a protection circuit coupled to a series coupling node of the first capacitance and the second capacitance. The protection circuit is set in a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated.
The following explains briefly an effect obtained by the typical inventions to be disclosed in the present application.
That is, it is possible to provide technology for the purpose of avoiding device destruction due to electrification of the intermediate node of plural capacitors coupled in series with each other to form one step-up capacitor, and avoiding falling of the pump efficiency due to the leakage current which flows through a leakage path of the intermediate node concerned.
The present invention will become fully understood from the detailed description given hereinafter and the accompanying drawings, wherein:
Hereinafter, with reference to the accompanying drawings, the embodiments of the present invention are explained in detail.
1. Outline of Embodiment
First, an outline of a typical embodiment of the invention disclosed in the present application is explained. A numerical symbol of the drawing referred to in parentheses in the outline explanation about the typical embodiment only illustrates what is included in the concept of the component to which the numerical symbol is attached.
(1) A charge pump circuit (1307) according to a typical embodiment of the present invention includes a step-up capacitor (C(x−1), Cx) including a first capacitance (Ca) and a second capacitance (Cb) coupled in series with each other, a capacitance driver (DRV(x−1), DRVx) for generating step-up voltage by driving the step-up capacitor, and a protection circuit (D1, D2) coupled to a series coupling node (105,106) of the first capacitance and the second capacitance. The protection circuit is set in a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated.
According to the configuration, it is possible to suppress low an absolute value of voltage applied to per capacitor, by forming one step-up capacitor with the first capacitance and the second capacitance coupled in series with each other. In the charge pump circuit, an absolute value of voltage becomes larger at a step-up stage which is located nearer an output terminal of the charge pump circuit. However, as described above, it is possible to suppress low an absolute value of voltage applied to per capacitor, by forming one step-up capacitor with the first capacitance and the second capacitance coupled in series with each other. Accordingly, it is possible to improve the relaxation of the withstand voltage of the step-up capacitor. In such a relaxation measure for the withstand voltage of a step-up capacitor, the protection circuit is set in a conductive state when the step-up voltage is not generated, and a stored charge of the series coupling node of the first capacitance and the second capacitance is discharged. Therefore, a leakage path is formed by the protection circuit. Accordingly, it is possible to avoid device destruction resulting from electrification of the series coupling node of the first capacitance and the second capacitance. Furthermore, the protection circuit is maintained in a non-conductive state when the step-up voltage is generated. Therefore, it is possible to prevent a leakage current which flows through the leakage path of the series coupling node of the first capacitance and the second capacitance; accordingly, it is possible to avoid falling of the pump efficiency.
(2) In Paragraph (1), the protection circuit can be configured by including a diode (D1, D2) coupled to the series coupling node of the first capacitance and the second capacitance. Accordingly, the protection circuit can be formed easily.
(3) In Paragraph (2), the charge pump circuit is provided with a control circuit (101) which can control potential of a cathode of the diode. By controlling the potential of the cathode of the diode by use of the control circuit, it is possible to realize the function of the protection circuit easily.
(4) In Paragraph (3), the control circuit can be configured so as to control the cathode of the diode to a low level when the step-up voltage is not generated, and to control the cathode of the diode to a high level when the step-up voltage is generated. By such control performed in the control circuit, the diode is set in a conductive state when the step-up voltage is not generated; accordingly the diode discharges a stored charge of the series coupling node of the first capacitance and the second capacitance. The diode is maintained in a non-conductive state, when the step-up voltage is generated.
(5) In Paragraph (4), the diode is a pn junction diode in which a p-type diffusion layer (p+) and an n-type diffusion layers (n+) in an n-well region (nwell) are joined. By coupling an anode of the pn junction diode to the series coupling node of the first capacitance and the second capacitance, the function of the diode described above can be exhibited.
(6) In Paragraph (1), the protection circuit can employ devices other than the diode. For example, the protection circuit can be configured by including a switch by means of an MOS transistor (1001, 1002) coupled to the series coupling node of the first capacitance and the second capacitance.
(7) In Paragraph (6), the charge pump circuit can be provided with a control circuit (101) which can control operation of the switch by means of the MOS transistor.
(8) In Paragraph (7), the control circuit controls the switch to a conductive state when the step-up voltage is not generated, and controls the switch to a non-conductive state when the step-up voltage is generated. By such control, the switch is set in a conductive state when the step-up voltage is not generated and the switch discharges a stored charge of the series coupling node of the first capacitance and the second capacitance. The switch is maintained in a non-conductive state, when the step-up voltage is generated.
(9) In Paragraph (5), various configurations can be considered as to the first capacitance and the second capacitance coupled in series each other. For example, the step-up capacitor including the first capacitance and the second capacitance coupled in series each other can adopt lamination of a first polysilicon layer (PolySi1) and a second polysilicon layer (PolySi2) with an insulating film interposed therebetween, over a well region (pwell).
(10) In Paragraph (5), the first capacitance and the second capacitance can adopt lamination of polysilicon layers (PolySi) with an interposing insulating film, over a well region (pwell). Since the second capacitance is laminated over the first capacitance, the first capacitance and the second capacitance can be formed in area occupied by one piece of capacitance.
(11) In Paragraph (5), the first capacitance and the second capacitance can adopt lamination of an upper metal layer (501, 503) and a lower metal layer (502, 504) with an insulating film interposed therebetween.
(12) A nonvolatile memory (1103) can be configured by a charge pump circuit (1307), a memory array (1208) in which a nonvolatile memory cells are arranged, and a circuit (1209, 1210) which performs a read/write to the memory array using a step-up voltage generated by the charge pump circuit. Improvement in the reliability of the nonvolatile memory can be achieved by adopting the charge pump circuit with the working-effects as described above.
(13) A data processing apparatus can be configured by including the nonvolatile memory (1103) and a CPU (1107) which can access the nonvolatile memory. Improvement in the reliability of the data processing apparatus can be achieved by adopting the nonvolatile memory.
(14) In a microcomputer application system (1401, 1501, 1601) mounting a microcomputer which executes a predetermined control program, the data processing apparatus according to Paragraph (13) can be adopted as the microcomputer.
2. Details of Embodiment
The embodiments are explained in more detail.
A microcomputer 1100 illustrated in
The ports 1101 and 1104, the timer 1102, the sequencer 1110, the flash memory module 1103, the bus interface 1105, and the clock generator 1108 are coupled with each other via a peripheral bus 1112. The RAM 1109, the flash memory module 1103, the bus interface 1105, the DMAC 1106, and the CPU 1107 are coupled with each other via a high speed bus 1111. The ports 1101 and 1104 transfer various data to and from the exterior. The timer 1102 has a function to detect elapsing of fixed time by counting a clock. The DMAC 1106 controls direct data transfer performed among various devices, bypassing the CPU 1107. The clock generator 1108 includes an oscillator which generates a clock signal of predetermined frequency, and a PLL (Phase Locked Loop) which multiplies the generated clock signal. The microcomputer 1100 is shifted to a standby state when a standby signal STBY is asserted, and initialized when a reset signal RES is asserted. High-potential-side power source Vcc and low-potential-side power source Vss are supplied via predetermined terminals as power supply voltage for operation of the microcomputer 1100. The sequencer 1110 controls sequentially operation of the flash memory module 1103 according to a command from the CPU 1107.
The flash memory 1103 includes an I/O control circuit 1201, an oscillator (OSC) 1204, a sub sequencer (Sub Sequencer) 1205, a sense amplifier (Sense Amp) 1211, a column decoder (Y Dec) 1210, a flash memory array 1208, and a row decoder (X Dec) 1209. The flash memory 1103 also includes a distributor (Distributor) 1207 and a power supply circuit 1206.
The I/O control circuit (I/O Control) 1201 has a function for controlling signal input-output in the flash memory 1103, and includes an I/O buffer (I/O Buff) 1202 and an address buffer (Address Buff) 1203. The oscillator 1204 generates a clock signal Clock. The generated clock signal Clock is transferred to the sub sequencer 1205 and the power supply circuit 1206. The sub sequencer 1205 controls sequentially operation of the distributor 1207 and the power supply circuit 1206. The power supply circuit 1206 includes plural charge pump circuits for generating mutually different voltages. In the plural charge pump circuits, an operating state/non-operating state is controlled by an on/off control signal from the sub sequencer 1205. Voltage generated by the plural charge pump circuits is transferred to the row decoder 1209 and the column decoder 1210 via the distributor 1207. The row decoder 1209 drives a word line in the flash memory array 1208 to a selection level by decoding a row address transferred via the address buffer 1203. The sense amplifier 1211 obtains read-out data by comparing with a reference level a signal selectively outputted from the flash memory array 1208 based on an output of the column decoder 1210. The column decoder 1210 generates a selection signal of a column system by decoding a column address. The flash memory array 1208 is configured by plural flash memory cells arranged in a row direction and a column direction. This nonvolatile memory cell has electrodes of a control gate, a floating gate, a drain, and a source. The drains of the plural flash memory cells arranged in the column direction are joined together, and coupled to a bit line via a sub bit-line selector. The sources of the plural flash memory cells are coupled to a common source line. The flash memory cells coupled to the common source line composes one block, and they are formed in a common well area of the semiconductor substrate, serving as a unit of an erase. On the other hand, the control gates of plural flash memory cells arranged in the row direction are coupled to a word line in units of row.
The power supply circuit 1206 includes operational amplifiers 1301, 1312, 1313, and 1314, comparators 1308-1311, a constant voltage generating circuit 1302, an oscillator circuit (OSC) 1303, and charge pump circuits 1304-1307. Based on an output of the operational amplifier 1301, a standard voltage is outputted from the constant voltage generating circuit 1302. The operational amplifier 1301 compares an output voltage of constant voltage generating circuit 1302 with the reference voltage Vref. The reference voltage Vref is set to 1.2V. The oscillator circuit (OSC) 1303 generates a clock signal of a predetermined frequency in response to supply of the standard voltage generated in the constant voltage generating circuit 1302. The clock signal is transferred to the charge pump circuits 1304-1307. A temperature characteristics-appending circuit 1315 appends a predetermined temperature dependence characteristic to the standard voltage generated by the constant voltage generating circuit 1302. The standard voltage to which the temperature dependence characteristic has been appended by the temperature characteristics-appending circuit 1315 is transferred to the comparators 1308-1311.
The comparator 1308 compares an output voltage of the charge pump circuit 1304 with the output of the temperature characteristics-appending circuit 1315. The charge pump circuit 1304 generates a memory rewriting voltage 1 based on the comparison result of the comparator 1308. The memory rewriting voltage 1 is set to +10V. The operational amplifier 1312 adds the output of the temperature characteristics-appending circuit 1315 to the output of the charge pump circuit 1304, to generate a verify voltage 1.
The comparator 1309 compares an output voltage of the charge pump circuit 1305 with the output of the temperature characteristics-appending circuit 1315. The charge pump circuit 1305 generates a memory rewriting voltage 2 based on the comparison result of the comparator 1309. The memory rewriting voltage 2 is set to +7V.
The comparator 1310 compares an output voltage of the charge pump circuit 1306 with the output of the temperature characteristics-appending circuit 1315. The charge pump circuit 1306 generates a memory rewriting voltage 3 based on the comparison result of the comparator 1310. The memory rewriting voltage 3 is set to +4V.
The comparator 1311 compares an output voltage of the charge pump circuit 1307 with the output of the temperature characteristics-appending circuit 1315. The charge pump circuit 1307 generates a memory rewriting voltage 4 based on the comparison result of the comparator 1311. The memory rewriting voltage 4 is set to −10V. The operational amplifier 1313 adds the output of the temperature characteristics-appending circuit 1315 to the output of the charge pump circuit 1307, to generate a verify voltage 2. The operational amplifier 1314 adds the output of the temperature characteristics-appending circuit 1315 to the output of the charge pump circuit 1307, to generate a memory array control voltage.
The charge pump circuit 1307 illustrated in
A negative voltage Vp is outputted from the output terminal 104. This negative voltage Vp is compared with the standard voltage outputted from the temperature characteristics-appending circuit 1315 in the comparator 1311. The comparison result is transferred to the control circuit 101 via an input terminal 103. In order to stabilize the negative voltage Vp based on the output of the comparator 1311, the control circuit 101 controls supply of the clock signals φ1 and φ2 to the drivers DRV1-DRVx, by controlling a logical value of the control signal CNT1.
The voltage level of the output terminal of the charge pump circuit 1304 is stepped up to the negative voltage Vp, by moving a charge alternately by the even number stage and the odd number stage, in synchronization with the clock signals φ1 and φ2.
In such a charge pump circuit 1307, an absolute value of voltage becomes larger in a step-up stage which is located nearer the output terminal 104. The voltage applied to the step-up capacitor is given by a difference of Vcc as the high level output of the driver and the step-up voltage Vm. For example, if it is assumed that Vcc=6V and the step-up voltage is −10V, there is a possibility that voltage of 16V may be applied across the terminals of the step-up capacitors C(x−1) and Cx of the step-up stages near the output terminal 104. Therefore, in the present embodiment, the step-up capacitors C(x−1) and Cx are comprised of two capacitors Ca and Cb coupled in series with each other, respectively. Accordingly, it is possible to suppress low the absolute value of voltage applied to per capacitor.
Diodes D1 and D2 are provided as a device for making a suitable leakage path from series coupling nodes (intermediate nodes) 105 and 106, in the case of forming one step-up capacitor from two capacitors coupled in series with each other. These diodes D1 and D2 are pn junction diodes. The anode of the diode D1 is coupled to the series coupling node 105 of capacitors Ca and Cb of the step-up capacitor C(x−1), and the anode of the diode D2 is coupled to the series coupling node 106 of capacitors Ca and Cb of the step-up capacitor Cx. The cathodes of the diodes D1 and D2 are coupled to the control circuit 101 in common. The control circuit 101 sets the cathodes of the diodes D1 and D2 to the ground level (level of the low-potential-side power source Vss), in a non-operating state (off state) of the charge pump circuit 1307. The control circuit 101 sets the cathodes of the diodes D1 and D2 to the level of the high-potential-side power source Vcc, in an operating state (on state) of the charge pump circuit 1307. Such control will be explained later in full detail.
The step-up capacitors C(x−1) and Cx can be formed as follows.
The step-up capacitor C(x−1) illustrated in
A flash memory cell is comprised of a floating gate and a control gate laminated respectively on a well region. The step-up capacitor C(x−1) is formed by the same process as the present flash memory cell.
In the case of the laminated capacitor illustrated in
Amplitude_of—Vm=(Vcc·Ca·Cb)/(Ca·(Cb+Cpara)) (Equation 1)
When it is assumed that Ca=Cb and that the parasitic capacitance Cpara is 20% of the capacitance of the capacitor Cb, the amplitude of the step-up voltage Vm becomes 83% of Vcc, as derived by the following equation.
Amplitude_of—Vm=Vcc×1/1.2=Vcc×83% (Equation 2)
In the case of the laminated capacitor illustrated in
On the other hand, according to the configuration illustrated in
In a non-operating state (off state) of the charge pump circuit 1307, as illustrated in
In the above, the charge pump circuit which outputs a negative voltage has been explained. A charge pump circuit which outputs a positive voltage can be configured in the same manner. In the charge pump circuit which outputs a positive voltage, n-channel type MOS transistors NM0-NMz illustrated in
It is possible to apply a monolayer capacitor as illustrated in
The capacitors Ca and Cb are a monolayer capacitor, respectively, and are formed in mutually different capacity forming regions 401 and 402.
In the capacity forming region 401, a well region deep nwell is formed in a p-type substrate psub, a well region pwell is formed in the well region deep nwell, and a diffusion layer p+ is formed in the well region pwell. Over this surface, a polysilicon layer PolySi is laminated with an interposing insulating film. The capacitor Ca is formed in the capacity forming region 401, by placing the polysilicon layer PolySi in face of the well region pwell with an insulating film interposed therebetween.
In the capacity forming region 402, a well region deep nwell is formed in a p-type substrate psub, a well region pwell is formed in the well region deep nwell, and a diffusion layer p+ is formed in the well region pwell. Over this surface, a polysilicon layer PolySi is laminated with an interposing insulating film. The capacitor Cb is formed in the capacity forming region 402, by placing the polysilicon layer PolySi in face of the well region pwell with an insulating film interposed therebetween.
The output of the capacitance driver DRV(x−1) is transferred to the polysilicon layer PolySi in the capacity forming region 401. The diffusion layer p+ in the capacity forming region 401 and the polysilicon layer PolySi in the capacity forming region 402 are coupled, and the intermediate node 105 is formed. The present intermediate node 105 is coupled to the control circuit 101 via the diode D1 as is the case with Embodiment 1. The step-up voltage Vm is obtained from the diffusion layer p+ in the capacity forming region 402.
The capacitors Ca and Cb are coupled in series with each other. Assuming that parasitic capacitance between the high-potential-side power source Vcc and the intermediate node 105 is Ca_para and that parasitic capacitance between a terminal of the high-potential-side power source Vcc and a terminal of the step-up voltage Vm is Cb_para, the amplitude of the step-up voltage Vm is given by the following equation.
Amplitude_of—Vm=(Vcc·Ca·Cb)/((Ca+Ca—para)·(Cb+Cb—para)) (Equation 3)
When it is assumed that Ca=Cb and that the parasitic capacitance Ca_para is 20% of the capacitance of the capacitor Ca and the parasitic capacitance Cb_para is 20% of the capacitance of the capacitor Cb, the amplitude of the step-up voltage Vm becomes 70% of Vcc, as derived by the following equation.
Amplitude_of—Vm=Vcc×1/1.44=Vcc×70%
Since the amplitude of Vm in the case of Embodiment 1 is 83% of Vcc as derived by Equation 2, compared with that, the amplitude of Vm in the case of Embodiment 2 is reduced. In the charge pump circuit which uses the capacitor illustrated in
However, also in the case where a monolayer capacitor (Ca, Cb) as illustrated in
Therefore, also in the charge pump circuit which uses the capacitor illustrated in
In a semiconductor integrated circuit, it is possible to form a capacitor by use of laminated structure of metal-insulator-metal (the capacitor is called henceforth a Metal-Insulator-Metal capacitor (MIM capacitor)). Therefore, it is also preferable to apply an MIM capacitor as illustrated in
Also when the MIM capacitors 505 and 506 are used, by providing diodes D1 and D2 to the intermediate nodes 105 and 106, and controlling the diodes D1 and D2 by the control circuit 101, as is the case illustrated in
In place of the diodes D1 and D2 illustrated in
In
As described above, even when the switch by means of the n-channel MOS transistors 10.01 and 1002 is applied in place of the diodes D1 and D2 illustrated in
It is possible to apply the microcomputer 1100 according to Embodiment 1-Embodiment 4 to various microcomputer application systems.
The microcomputer 1100 according to Embodiment 1-Embodiment 4 can be applied to a control board 1402 of a washing machine 1401 as an example of home electric appliances, as illustrated in
The microcomputer 1100 according to Embodiment 1-Embodiment 4 can be also applied to a control board 1502 of a refrigerator 1501 as an example of home electric appliances, as illustrated in
The microcomputer 1100 according to Embodiment 1-Embodiment 4 can be further applied to a control board 1602 of a digital camera 1601 as an example of home electric appliances, as illustrated in
As described above, the invention accomplished by the present inventors has been concretely explained based on various embodiments. However, it cannot be overemphasized that the present invention is not restricted to the embodiments, and it can be changed variously in the range which does not deviate from the gist.
Kasai, Hideo, Sakurai, Ryotaro
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