A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of sio2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a sio2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the sio2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the sio2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the sio2 interfacial layer inhibits regrowth of the sio2 layer into the channel region during the annealing step.
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1. A field effect fet transistor having a gate structure comprising:
a high-K dielectric layer;
a gate electrode located on the high-K dielectric layer; and
an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor, wherein the interfacial layer comprises a layer of sio2 containing a regrowth inhibiting agent, the interfacial layer including an amount of the regrowth inhibiting agent sufficient to inhibit regrowth of the sio2 layer into the channel region of the fet during annealing, thereby maintaining a predetermined thickness of the gate structure.
9. A method of forming a gate structure of a field effect transistor (fet), the method comprising:
forming a gate stack including, in order:
a sio2 interfacial layer adjacent a channel region of the field effect transistor;
a high-K dielectric layer on the sio2 interfacial layer; and
a gate electrode on the high-K dielectric layer;
introducing a regrowth inhibiting agent of a sufficient amount into the sio2 interfacial layer; and
annealing the gate structure,
wherein the regrowth inhibiting agent inhibits regrowth of said sio2 interfacial layer into the channel region during said annealing, thereby maintaining a predetermined thickness of the gate structure.
2. The field effect transistor of
3. The field effect transistor of
4. The field effect transistor of
5. The field effect transistor of
6. The field effect transistor of any preceding claim, wherein the regrowth inhibiting agent comprises impurity ions selected from the group consisting of As and P.
7. The field effect transistor of
8. The field effect transistor of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
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This invention relates to gate structures for field effect transistors. In particular, this invention relates to gate structures that include a high-K dielectric layer and an interfacial layer located in between the high-K dielectric and a channel region of the field effect transistor.
The ever decreasing dimensions of semiconductor devices such as field effect transistors continue to present new challenges for gate design and manufacture. As gate lengths reduce, the thickness of the gate insulating layers that are used must also decrease. Conventionally, SiO2 has been used as a gate insulator. However, since SiO2 layers thinner than around 1.0-1.5 nm suffer from unacceptably strong gate leakage effects, attention in recent times has turned to alternative structures that include high-K dielectric materials.
High-K dielectric materials allow thicker insulating layer dimensions to be employed, while retaining relatively high values of gate capacitance.
As illustrated in
The purpose of the interfacial layer 2 shown in
Present high-K gate technologies are unable to meet the demands of the International Technology Roadmap for Semiconductors (ITRS), which foresees an 8 Å CETinv (Capacitance Equivalent Thickness under inversion) for high performance applications in 2011 (this is equivalent to a standard oxide (SiO2) thickness of 4-5 Å). In present high-K gate structures of the kind shown in
It is an object of this invention to address at least some of the limitations noted above in respect of existing gate structures incorporating high-K dielectrics.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
According to an aspect of the invention, there is provided a field effect transistor having a gate structure. The gate structure includes a high-K dielectric layer. The gate structure also includes a gate electrode located on the high-K dielectric layer. The gate structure further includes an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent.
According to another aspect of the invention, there is provided a method of forming a gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer. The method further includes annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.
In accordance with this invention, it has been recognised that during the manufacture of a field effect transistor including a high-K gate structure, regrowth of the SiO2 interfacial layer into the channel region of the transistor (during an anneal step), leads to an increased oxide thickness for the gate insulator. It is also recognised that by inhibiting regrowth of the interfacial layer during an annealing step of the manufacture process, the problem of reducing the overall thickness of the gate insulation provided in the gate structure (where the gate insulation thickness may be defined as the combined thickness of the interfacial layer and the high-K dielectric layer) can be at least partially addressed. It has further been recognised that regrowth of the interfacial layer can be achieved by introducing a regrowth inhibiting agent into the interfacial layer prior to any anneal processes that a performed as part of the larger manufacturing method.
In accordance with an embodiment of the invention, the regrowth inhibiting agent comprises impurity ions. In accordance with an embodiment of the invention, the regrowth inhibiting agent comprises impurity ions selected from the group consisting of As and P.
The addition of impurities such as As into the gate electrode (which may, for example, comprise a metal or poly-silicon layer) has been found to produce an n-type tuning effect on the work function of the gate electrode. This tuning effect may itself be used to tailor the characteristics of the gate. However, if n-type tuning is not desired, then p-type dopants can be added to the gate electrode or an p-type metal gate can be used to compensate.
In one embodiment, the interfacial layer has a thickness in the range 3 to 12 Å.
In one embodiment, the high-K dielectric layer has a thickness in the range 1-3 nm.
In one embodiment, the high-K dielectric layer has a value of κ greater than 15. In particular, the high-K dielectric layer can have a value of κ in the range 15-25.
In one embodiment, the As or P impurity ions are present in a concentration of between ˜1018 and ˜1020 at/cm3.
The field effect transistor can comprise, for example, a Metal Insulator Semiconductor Field Effect Transistor (MISFET), a Fin Field Effect Transistor (FinFET), or a Trench Field Effect Transistor (TrenchFET).
In accordance with an embodiment of the invention, the regrowth inhibiting agent can be introduced into the SiO2 interfacial layer using ion beam implantation techniques. The implantation energy for As impurities can be in the range 6-8 keV, while the implantation energy for P impurities can be in the range 2-6 keV. A dosage level in the range 1×1015 cm−2 to 5×1015 cm−2 can be used, depending on the layer thicknesses and material densities of the gate electrode (typically 2-15 nm thick) and any cap layer that is provided (typically 5-10 nm thick) on the gate electrode. Alternative techniques to ion beam implantation (such as plasma doping (PLAD)) may also be used to introduce the regrowth inhibiting agent into the device.
Embodiments of the present invention will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:
Embodiments of the present invention are described in the following with reference to the accompanying drawings.
Embodiments of this invention can provide gate high-K structures having thinner gate insulation than could previously be achieved. In particular, it has been found that the interfacial layer, that typically forms a seed for the growth of a high-K dielectric layer, has a tendency to regrow into the channel region of a field effect transistor during any annealing steps that are carried out as part of the larger manufacturing process. It has further been found that this regrowth can be largely prevented by introducing a regrowth inhibiting agent into the interfacial layer prior to the performance of the annealing step or steps. Both As and P impurities introduced into the interfacial layer prior to an annealing step have been found to act as regrowth inhibitors.
In the following, the invention is described with reference to the gate structure of a bulk MISFET. However, it will be appreciated that the described embodiments are merely examples of how the invention may be implemented. In particular, it will be appreciated that a gate structure of the kind described herein may be provided for field effect transistors other than bulk MISFETs. For example, the invention may be applied to other forms of field effect transistor such as FinFETs and TrenchFETs.
An example of a field effect transistor incorporating a gate structure in accordance with an embodiment of this invention is illustrated schematically in
On an upper surface of the interfacial layer 34 there is provided a high-K dielectric layer 38. The purpose of the interfacial layer 34 is to act as a seed layer for the high-K dielectric layer 38. In accordance with an embodiment of the invention, the κ value of the material used in the high-K dielectric layer 34 is greater than 15. Examples of materials that may be used to form the high-K dielectric layer 38 include HfO2, ZrO2, TiO2, Ta2O5, HfSiO, La2O3, Y2O3 and Al2O3. The high-K dielectric layer can, in some embodiments, comprise a stack of sub-layers, each comprising one or more of the high-K materials indicated above.
As described below, the interfacial layer 34 itself comprises SiO2, into which a regrowth inhibiting agent has been introduced. Typically, the regrowth inhibiting agent may take the form of impurities such as ions of As or P. The concentration in which these impurities are present can be in the range ˜1018 and ˜1020 at/cm3. After manufacture, the regrowth inhibiting agent remains within the interfacial layer. In accordance with an embodiment of the invention, the thickness of the interfacial layer 34 can be in the range 3 to 12 Å. The thickness of the high-K dielectric layer can be in the range 1 to 3 nm.
As shown in
An example method of making a gate structure of the kind described above with respect to
As is shown in
The gate stack 44 itself includes a number of layers as shown in
SiO2 interfacial layer 33=3-12 Å;
high-K dielectric layer 38=1-3 nm;
gate electrode material 40=2-15 nm;
capping layer 42=5-20 Å.
The next stage in the method of making the new gate structure in accordance with this invention is shown
Any suitable method for introducing the regrowth inhibiting agent into the layer 33 can be used. The actual method used may be tailored according the particular form the regrowth inhibiting agent takes. As described herein, and in accordance with an embodiment of this invention, the regrowth inhibiting agent can take the form of impurity ions. By way of example only, it has been shown that both As and P ions introduced into the SiO2 interfacial layer 33, can act to inhibit regrowth of the interfacial layer 33 during subsequent annealing.
In the present example, and as show in
Following the introduction of the regrowth inhibiting agent into the SiO2 interfacial layer 33 to form an interfacial layer 34 which includes the agent, the interfacial layer 34 is secured against regrowth into the channel region 26. During regrowth of this kind, a SiO2 interfacial layer (i.e. without any kind of inhibiting agent as described herein) may otherwise typically expand to consume a few Angstroms (e.g. 1-5 Å) of Si in the channel region 26 beneath the gate stack 44.
The annealing step(s) may be associated with dopant activation in the source/drain regions 22 of the transistor 20. However, it should also be noted that the annealing step(s) described herein need not necessarily be directly associated with the manufacture of the field effect transistor 20 itself. Instead, the subsequent annealing step(s) may be associated primarily with the manufacture of other components on the wafer on which the transistor 20 is formed.
The heating step(s) themselves can comprise parameters which fall within standard CMOS annealing conditions. By way of an example, the heating step(s) can comprise heating the field effect transistor to a temperature in the range 600-1100° C. for a duration of between is (for highest temperatures) to several minutes (for lowest anneal temperatures).
Following the performance of one or more annealing steps, a gate structure of the kind illustrated in
An effect of the introduction of impurity ions such as As into the gate stack 44 described in relation to
The trend line shown in
The gate stacks used in the trial comprised a 10 nm a-Si cap layer provided on a 10 nm TiN gate electrode, and a 2 nm HfO2 High-K dielectric layer provided on a SiO2 interfacial layer having a thickness of approximately 1 nm. As described herein, As impurities were introduced into three separate gate stacks using ion implantation. The leakage current and effective oxide thickness of each resulting gate stack were then measured.
The implant parameters for the data points in
Data point
Implant energy (keV)
Dose (cm−2)
50
8
2E15
52
6
4E15
54
6
2E15
Additionally, data point 56 in
The trend line shown in
The gate stacks used in the trial comprised a 10 nm a-Si cap layer provided on a 10 nm TiN gate electrode, and a 2 nm HfO2 High-K dielectric layer provided on a SiO2 interfacial layer having a thickness of approximately 1 nm. As described herein, P impurities were introduced into three separate gate stacks using ion implantation. The leakage current and effective oxide thickness of each resulting gate stack were then measured.
The implant parameters for the data points in
Data point
Implant energy (keV)
Dose (cm−2)
60
2
2E15
62
2
4E15
64
4
2E15
Additionally, data point 66 in
Accordingly, there has been described a field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.
Although particular embodiments of the invention have been described, it will be appreciated that many modifications/additions and/or substitutions may be made within the scope of the claimed invention.
Mueller, Markus, Boccardi, Guillaume, Petry, Jasmine
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