A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
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13. A method of operating a check engine, comprising:
providing a plurality of magnetic random access memory (MRAM) cells in the check engine, each of the plurality of MRAM cells including a storage magnetization and a sense magnetization;
storing a plurality of reference bits in the plurality of MRAM cells, including during a programming cycle, aligning the storage magnetization of the each of the MRAM cells to store at least one of the plurality of reference bits;
presenting a plurality of target bits to the plurality of MRAM cells, including during a pattern checking cycle, aligning the sense magnetization of the each of the plurality of MRAM cells to present at least one of the plurality of target bits; and
generating an output representing a level of matching between the plurality of target bits and the plurality of reference bits, based on a relative alignment between the storage magnetization and the sense magnetization of the each of the MRAM cells;
wherein the output represents a percentage of the plurality of target bits that match the plurality of reference bits.
1. A check engine comprising:
a plurality of comparators each including:
a first directional characteristic aligned to store at least one reference bit included in a set of reference bits; and
a second directional characteristic aligned to present at least one target bit included in a set of target bits;
wherein each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic; and
wherein the check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output;
wherein the check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators;
wherein to determine that the set of target bits matches the set of reference bits, the check engine is configured to compare the combined output of the plurality of comparators to a self-referenced output of the plurality of comparators corresponding to a full matching configuration; and
wherein the check engine is configured to determine the self-referenced output of the plurality of comparators in a separate cycle prior to determining that the set of target bits matches the set of reference bits.
2. The check engine of
3. The check engine of
4. The check engine of
5. The check engine of
6. The check engine of
if the set of target bits matches the set of reference bits, the plurality of comparators has a first combined resistance;
if the set of target bits does not match the set of reference bits, the plurality of comparators has a second combined resistance; and
the second combined resistance is not equal to the first combined resistance.
7. The check engine of
8. The check engine of
9. The check engine of
at least one of the plurality of comparators is a magnetic random access memory (MRAM) cell; and
the first directional characteristic and the second directional characteristic correspond to a storage magnetization and a sense magnetization, respectively.
10. The check engine of
a first directional characteristic aligned to store multiple reference bits included in the set of reference bits; and
a second directional characteristic aligned to present multiple target bits included in the set of target bits;
wherein the at least one of the plurality of comparators produces an output representing a level of matching between the multiple target bits and the multiple reference bits.
11. The check engine of
12. The check engine of
14. The method of
15. The method of
16. The method of
17. The method of
if the plurality of target bits matches the plurality of reference bits, the plurality of MRAM cells has a first combined resistance;
if the plurality of target bits does not match the plurality of reference bits, the plurality of MRAM cells has a second combined resistance;
the second combined resistance is not equal to the first combined resistance; and
the output is generated based on at least one of the first combined resistance and the second combined resistance.
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The present application claims the benefit of U.S. Provisional Application No. 61/418,822, filed on Dec. 1, 2010, and U.S. Provisional Application No. 61/493,890, filed on Jun. 6, 2011, the disclosures of which are incorporated herein by reference in their entirety.
The invention relates generally to pattern checking and, more particularly, to an apparatus, system, and method for matching patterns with an ultra fast check engine.
Memory technologies can be used to store information in the form of patterns. To check that a stored pattern (e.g., a reference pattern) matches a pattern provided at some input terminal (e.g., a target pattern), it is typical to first read the reference pattern and then compare the target pattern with the reference pattern. Comparison of the target pattern with the reference pattern can yield a “yes” or a “no” matching level.
It is against this background that a need arose to develop the apparatus, system, and method described herein.
Embodiments of the invention relate to an apparatus, system, and method for matching a target pattern to a previously stored reference pattern with an ultra fast check engine. A result of the comparison can yield a “yes” or a “no” matching level, such as for purposes of security, authentication, and a number of other applications. Advantageously, the comparison between the target pattern and the reference pattern can be performed in situ within the check engine, without requiring a read operation for the reference pattern, and without requiring conveyance of the reference pattern to another part of the system. As a result, the comparison can be performed in a short time, such as about 20 ns or less, while maintaining the reference pattern within the check engine so as to reduce its exposure to interception or tampering.
In one embodiment, a check engine includes a plurality of comparators each including: (1) a first directional characteristic aligned to store at least one reference bit included in a set of reference bits; and (2) a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
In one embodiment, a method of operating a check engine includes: (1) providing a plurality of magnetic random access memory (MRAM) cells in the check engine, each of the plurality of MRAM cells including a storage magnetization and a sense magnetization; (2) storing a plurality of reference bits in the plurality of MRAM cells, including during a programming cycle, aligning the storage magnetization of the each of the MRAM cells to store at least one of the plurality of reference bits; (3) presenting a plurality of target bits to the plurality of MRAM cells, including during a pattern checking cycle, aligning the sense magnetization of the each of the plurality of MRAM cells to present at least one of the plurality of target bits; and (4) generating an output representing a level of matching between the plurality of target bits and the plurality of reference bits, based on a relative alignment between the storage magnetization and the sense magnetization of the each of the MRAM cells.
Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.
For a better understanding of the nature and objects of some embodiments of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.
The following definitions apply to some of the aspects described with respect to some embodiments of the invention. These definitions may likewise be expanded upon herein.
As used herein, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to an object can include multiple objects unless the context clearly dictates otherwise.
As used herein, the term “set” refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects. Objects of a set also can be referred to as members of the set. Objects of a set can be the same or different. In some instances, objects of a set can share one or more common characteristics.
As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical manufacturing tolerances or variability of the embodiments described herein.
As used herein, the term “adjacent” refers to being near or adjoining. Adjacent objects can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent objects can be formed integrally with one another.
As used herein, the terms “connect,” “connected,” and “connection” refer to an operational coupling or linking. Connected objects can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of objects.
As used herein, the term “main group element” refers to a chemical element in any of Group IA (or Group 1), Group IIA (or Group 2), Group IIIA (or Group 13), Group IVA (or Group 14), Group VA (or Group 15), Group VIA (or Group 16), Group VIIA (or Group 17), and Group VIIIA (or Group 18). A main group element is also sometimes referred to as a s-block element or a p-block element.
As used herein, the term “transition metal” refers to a chemical element in any of Group IVB (or Group 4), Group VB (or Group 5), Group VIB (or Group 6), Group VIIB (or Group 7), Group VIIIB (or Groups 8, 9, and 10), Group IB (or Group 11), and Group IIB (or Group 12). A transition metal is also sometimes referred to as a d-block element.
As used herein, the term “rare earth element” refers to any of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
Embodiments of a check engine can be advantageously used in a number of applications involving a comparison between a target pattern and a reference pattern, whether for purposes of pattern matching, pattern recognition, pattern mining, pattern searching, or other purposes. For example, a check engine can be included within, or can operate in conjunction with, a smart card, a bank card, or another portable device to implement a security function (e.g., by checking patterns corresponding to security passwords, electronic keys, and cryptographic keys or by implementing zero knowledge proof techniques), an authentication function (e.g., by checking patterns to verify the identity of a bearer of the smart card), to facilitate commercial transactions (e.g., by checking patterns for electronic payment and electronic ticketing), and so forth. When implemented within smart cards or other portable devices, a check engine can operate in conjunction with Near Field Communication (“NFC”) or another wireless communication technology to allow input of target patterns and exchange of data. As an additional example, a check engine can be included within, or can operate in conjunction with, an identity document (e.g., an electronic passport, a driver's license, or an electronic identity card) to implement an authentication function (e.g., by checking patterns to verify the identity of a bearer of an electronic passport or to verify the authenticity of the electronic passport). As further examples, a check engine can be used to implement object navigation and tracking (e.g., by checking patterns corresponding to position or angular coordinates), mathematical calculations, data compression, cache tags, and networking functions (e.g., Ethernet address lookup, address filtering, and lookup of routing information in the context of switches, firewalls, bridges, routers, and other networking devices).
For certain applications, such as fingerprint recognition, a pattern may change slightly overtime, such as due to dry skin, finger cuts, dirt, varying angles at which the pattern is obtained, and so forth. Because a check engine can produce an analog output to measure the level of matching or the quality of a match, this analog output can be processed as part of an iterative process as illustrated in
One example of a suitable directional characteristic is a magnetization direction, which can be aligned by applying a magnetic field. Specifically, and as further explained below, the comparator can be implemented with one magnetization, namely a storage magnetization, that is aligned to represent the stored data value, and another magnetization, namely a sense magnetization, that is aligned to represent the target data value. Conventional memories can be susceptible to unauthorized data access by using techniques to derive a charge state of a capacitor. In contrast, the use of magnetization directions renders the comparator of
Still referring to
In a pattern checking mode, the comparator acts as a two terminal device, namely a “0” or a “1” is presented at an input of the comparator, and a response of “yes” or “no” based on the match is presented at an output of the comparator. In the case of a pair of magnetization directions, a “0” or a “1” can be presented by applying a magnetic field induced by a field line (e.g., extending along the Y direction). The output of the comparator can be analog in nature. For example, in the case of a pair of magnetization directions, a low resistance value (e.g., about 1 KΩ) can be presented for a “yes” match (e.g., when the magnetization directions are substantially parallel), while a high resistance value (e.g., about 2 KΩ) can be presented for a “no” match (e.g., when the magnetization directions are substantially antiparallel). Advantageously, pattern checking can be performed in situ within the comparator and with a short response time, such as within about 20 ns or less, without requiring a read operation for a stored data value, and without requiring conveyance of the stored data value to another part of the system.
As can be appreciated, the comparator of
In one embodiment, the generator 104 may evaluate the individual outputs 108A-108N to determine how many of the comparators 102A-102N individually detected a match. Alternatively, the generator 104 may aggregate (combine) the outputs 108A-108N. The output 110 may correspond to a number of the comparators 102 that individually detected a match, or a percentage of the comparators 102 that individually detected a match.
In one embodiment, the threshold 112 may be set such that a match is determined (e.g., the match output 114 is asserted) when not all of the bits of the target pattern match corresponding bits of the reference pattern, e.g., one or more bits of the target pattern does not match a corresponding one or more bits of the reference pattern. This type of processing may be helpful for applications such as fingerprint matching where identifying a “perfect” match can be less important that other applications. In another embodiment, the threshold 112 may be set such that a match is determined when all of the bits of the target pattern match the corresponding one or more bits of the reference pattern.
In the illustrated embodiment, “0's” and “1's” of a target pattern are checked in separate cycles. In one cycle, all “0's” of the target pattern are checked concurrently by presenting a “0” through the input line 202 and selecting particular ones of the comparators 200 (which are candidates for storing “0's”) through their respective bit lines (e.g., extending along the X direction) and their respective selection transistors. A result of checking for “0's” can account for an output of each selected comparator 200, or can correspond to an aggregate of some, or all, of the outputs of the selected comparators 200. For example, the result can be a “yes” if there is a positive match for each selected comparator 200, and can be a “no” otherwise. As another example, the result can be a “yes” if there is a positive match for at least a particular percentage of the selected comparators 200, and can be a “no” otherwise. If the result of checking for “0's” is a “no”, a next cycle to check “1's” can be skipped. Also, even if all “0's” are checked as a “yes”, a decision can be made to skip the next cycle and assert that a match is statistically likely. If a higher level of certainty is desired, all “1's” can be checked concurrently in the next cycle by presenting a “1” through the input line and selecting particular ones of the comparators 200 (which are candidates for storing “1's”) through their respective bit lines and their respective selection transistors. An overall result of checking can be available within about 20 ns or less if only “0's” are checked, and within about 2×20 ns if both “0's” and “1's” are checked in successive cycles.
The architecture of
Other implementations of a multi-bit serial architecture are contemplated. For example, multiple comparators can be connected together through a common bit line, rather than a common input line (or a common field line). Here, each comparator can operate with a separate, dedicated input line (or a separate, dedicated field line) and a selection transistor, which can be activated serially or concurrently during a programming cycle. During pattern checking, the comparators can be checked serially using the common bit line, with one comparator selected during a particular pattern checking cycle. Stated in another way, multiple comparators of a check engine can be located in a particular row of an array or a matrix, in a particular column of the array or the matrix, or a combination thereof.
The architecture of
TAS technology, as applied to MRAM's, provides one way of implementing the check engines explained herein.
Further details of a TAS-MRAM implementation of a check engine 900 can be appreciated with reference to
Referring to
Each of the sense layer 904 and the storage layer 906 includes, or is formed of, a magnetic material and, in particular, a magnetic material of the ferromagnetic type. A ferromagnetic material can be characterized by a substantially planar magnetization with a particular coercivity, which is indicative of a magnitude of a magnetic field to reverse the magnetization after it is driven to saturation in one direction. In general, the sense layer 904 and the storage layer 906 can include the same ferromagnetic material or different ferromagnetic materials. As illustrated in
The layer 908 functions as a tunnel barrier, and includes, or is formed of, an insulating material. Suitable insulating materials include oxides, such as aluminum oxide (e.g., Al2O3) and magnesium oxide (e.g., MgO). A thickness of the layer 908 can be in the nm range, such as from about 1 nm to about 10 nm.
In the illustrated embodiment, the magnetic cell 902 is implemented to store data corresponding to one of a pair of logic states. In other words, the magnetic cell 902 is a single-bit cell that stores a single-bit data value, although multi-bit implementations for storing multi-bit data values are also contemplated. In accordance with the single-bit implementation of the magnetic cell 902, the storage layer 906 has a storage magnetization that is switchable between a pair of directions corresponding to the pair of logic states. Referring to
Still referring to
During a TAS-type programming cycle, the magnetic cell 902 is heated by applying a heating current through the magnetic cell 902 via the bit line 916, with the transistor 918 in a saturated mode. The magnetic cell 902 is heated to a temperature above the blocking temperature TBS of the pinning layer 910, such that a magnetization of the storage layer 906 is unpinned. Simultaneously or after a short time delay, the field line 912 is activated to induce a write magnetic field to switch the storage magnetization from an initial direction to another direction. Specifically, a write current is applied through the field line 912 to induce the write magnetic field to switch the storage magnetization direction, according to a reference bit to be stored. Because the storage magnetization direction can be aligned according to the write magnetic field, the storage magnetization direction can be switched between multiple directions according to a programming encoding scheme. One possible encoding scheme is implemented with a pair of directions that are displaced by about 180°, such that a “0” is assigned to one of the pair of directions, and a “1” is assigned to another one of the pair of directions.
Once the storage magnetization is switched to a programmed direction, the transistor 918 is switched to a blocked mode to inhibit current flow through the magnetic cell 902, thereby cooling the magnetic cell 902. The write magnetic field can be maintained during cooling of the magnetic cell 902, and can be deactivated once the magnetic cell 902 has cooled below the blocking temperature TBS of the pinning layer 910. Because the storage magnetization direction is pinned by the exchange bias of the pinning layer 910, its orientation remains stable so as to retain the stored data.
Other implementations of programming cycles are contemplated. For example, the magnetic cell 902 can be implemented with an anisotropic shape having a relatively high aspect ratio, such as about 1.5 or more. In such an anisotropic-shaped implementation of the magnetic cell 902, the storage magnetization direction can be switched and can remain stable, without requiring the pinning layer 910. As another example, a programming cycle can be carried out by applying a write current through the magnetic cell 902 via the bit line 916, using the so-called spin transfer torque (“STT”) effect. In such a STT-type programming cycle, the write current can become spin polarized by passing through a polarizing magnetic layer (not illustrated) or through the sense layer 904, and a magnetization of the storage layer 906 can be switched according to a spin-polarized orientation of the write current. Switching of the storage layer magnetization with the spin-polarized write current also can be combined with a TAS-type programming cycle, such as by heating the magnetic cell 902 above the blocking temperature TBS and then applying the spin-polarized write current through the magnetic cell 902.
During a pattern checking cycle, the field line 912 is activated to induce a compare magnetic field to vary a magnetization of the sense layer 904. Specifically, a compare current is applied through the field line 912 to induce the compare magnetic field to vary the sense magnetization direction, according to a target bit to be compared with a reference bit. Because the sense layer 904 is subject to little or no exchange bias, the sense magnetization direction can be readily varied under low-intensity magnetic fields and at a temperature below the blocking temperature TBS, while the storage magnetization remains stable in a programmed direction. The field line 912 is activated to induce the compare magnetic field that is consistent with a programming encoding scheme. Because the sense magnetization direction can be aligned according to the compare magnetic field, the sense magnetization direction can be switched to a particular direction assigned to a “0” or a “1”, according to the target bit presented for comparison.
As part of the pattern checking cycle, a degree of alignment between the sense magnetization direction and the storage magnetization direction is determined by applying a sense current through the magnetic cell 902 via the bit line 916, with the transistor 918 in a saturated mode. Measuring a resulting voltage across the magnetic cell 902 when the sense current is applied yields a resistance value of the magnetic cell 902 for a particular direction of the sense magnetization corresponding to a particular target bit. Alternatively, a resistance value can be determined by applying a voltage across the magnetic cell 902 and measuring a resulting current. When the respective magnetizations of the sense layer 904 and the storage layer 906 are antiparallel, a resistance value of the magnetic cell 902 typically corresponds to a maximum value, namely Rmax, and, when the respective magnetizations are parallel, a resistance value of the magnetic cell 902 typically corresponds to a minimum value, namely Rmin. A resulting resistance value of the magnetic cell 902 can be compared with a reference resistance value Rref, which represents an in-between resistance value between Rmax and Rmin. A matching response of “yes” or “no” can be determined based on whether the resistance value of the magnetic cell 902 is greater than Rref, which indicates an antiparallel alignment between the magnetization directions, or smaller than Rref, which indicates a parallel alignment between the magnetization directions.
A TAS-MRAM implementation of a check engine can be further extended by including functionality to store and compare multiple bits per magnetic cell, such as by using magnetizations that can be rotated in two dimensions.
For certain implementations, m can be represented as m=2n, with n≧2. Here, the cell is an n-bit cell that stores an n-bit data value. One possible encoding scheme assigning m logic states to m distinct angles θ is set forth in Table 1 below. A particular encoding scheme can be selected based on an angular resolution that allows alignment and misalignment of magnetizations to be distinguished. For example, if a resolution of resistance values is 90°, one possible encoding scheme assigning four logic states to four distinct angles θ is set forth in Table 2 below. As additional examples, a 45° resolution can be implemented with an encoding scheme with m=8 and n=3, a 22.5° resolution can be implemented with an encoding scheme with m=16 and n=4, and so forth. It should be understood that other encoding schemes are contemplated. For example, and referring to Table 2, the assignment between m logic states and m angles θ can be permuted, such that the logic state “00” is assigned to 90° (instead of 0°), the logic state “01” is assigned to 0° (instead of 90°), and so forth. As another example, an offset can be added to some, or all, of the angles θ, such that the logic state “00” is assigned to 0°+offset, the logic state “01” is assigned to 90°+offset, and so forth. As further examples, an increment between successive angles θ can be variable, rather than a constant, and certain of the m logic states and certain of the m angles θ can be omitted.
TABLE 1
Logic State/
n-bit data
θ
0 . . . 00
0°
0 . . . 01
360°/2n
0 . . . 10
2(360°/2n)
0 . . . 11
3(360°/2n)
. . .
. . .
TABLE 2
Logic State/
2-bit data
θ
00
0°
01
90°
10
180°
11
270°
The multi-bit cell of
The check engine 1000 of
As described previously with reference to
In one embodiment, the comparators 1002 may be connected to the common bit line 916 for application of heating current to the comparators 1002. Application of heating current may be controlled by a transistor 1004 or another device, such as a switch, configured to allow heating current to flow to the comparators 1002. In another embodiment, multiple transistors or switches may separately control application of heating current to subsets of the comparators 1002. For example, as shown in
As described previously with reference to
Referring to
In one embodiment, the reference 1014 is configured to distinguish between a full match (match of all bits) of a stored pattern and a target pattern determined by the comparators 1002, and a mismatch of the stored pattern and the target pattern in which any one of the comparators 1002 determines a mismatch of at least one bit of the stored pattern and the target pattern. The reference 1014 may be configured to a value between a first value of the input 1010 corresponding to the full match and a second value of the input 1010 corresponding to the mismatch determined by one of the comparators 1002. In one embodiment, the reference 1014 may be configured to a value halfway between the first value and the second value. Alternatively, if it is desired to reduce the probability of a false match indication, the reference 1014 may be configured to a value closer to the second value. Alternatively, if it is desired to reduce the probability of a false mismatch indication, the reference 1014 may be configured to a value closer to the first value.
Alternatively, the reference 1014 may be configured such that a match is determined when not all of the bits of the target pattern match corresponding bits of the stored pattern, e.g., one or more bits of the target pattern does not match a corresponding one or more bits of the stored pattern.
In a first embodiment, a match of a stored pattern and a target pattern may correspond to a “yes” match at each of the comparators 1002 (e.g., when the storage magnetization and sense magnetization directions are substantially parallel at each of the comparators 1002). Alternatively, in a second embodiment, a match of a stored pattern and a target pattern may correspond to a “no” match at each of the comparators 1002 (e.g., when the storage magnetization and sense magnetization directions are substantially antiparallel at each of the comparators 1002).
In an illustrative example of the first embodiment (match corresponds to parallel magnetization directions), if there are twenty comparators 1002 connected in series and the resistance of each comparator corresponding to a match (in this embodiment, a “yes” match) is known to be an ideal value of 1 KΩ, then the combined resistance corresponding to a match of a stored pattern and a target pattern determined by the twenty comparators 1002 is ideally 20 KΩ. If one of the comparators 1002 determines a mismatch (in this embodiment, a “no” match) and the resistance of the comparator corresponding to a mismatch is known to be an ideal value of 2 KΩ, then the combined resistance is ideally 21 KΩ.
In an illustrative example of the second embodiment (match corresponds to antiparallel magnetization directions), if there are twenty comparators 1002 connected in series and the resistance of each comparator corresponding to a match (in this embodiment, a “no” match) is known to be an ideal value of 2 KΩ, then the combined resistance corresponding to a match of a stored pattern and a target pattern determined by the twenty comparators 1002 is ideally 40 KΩ. If one of the comparators 1002 determines a mismatch (in this embodiment, a “yes” match) and the resistance of the comparator corresponding to a mismatch is known to be an ideal value of 1 KΩ, then the combined resistance is ideally 39 KΩ.
However, in reality, the resistances of the comparators 1002 vary around the ideal value due to factors such as manufacturing variations, environmental variations, and aging. Due to these variations, the combined resistance corresponding to a full match by a particular set of comparators 1002 is typically unknown. To more accurately determine the reference 1014, the set of comparators 1002 within the check engine 1000 may be configured so that the comparators 1002 have a combined resistance corresponding to a full match. This is known as self-referencing of the comparators 1002 to a full matching configuration. If the number of comparators 1002 in the set is small, self-referencing may not be needed if the variations of the resistances of the comparators 1002 around the ideal value are sufficiently small. Alternatively, if the number of comparators 1002 in the set is large, such as four or more, self-referencing may be used.
In one embodiment, during self-referencing the combined resistance of the comparators 1002 corresponding to a full match may be measured. Alternatively or in addition, the input 1010 corresponding to this combined resistance of the comparators 1002 may be measured. The reference 1014 may be determined from at least one of the combined resistance of the comparators 1002 corresponding to a full match and the input 1010 corresponding to this combined resistance of the comparators 1002.
For example, continuing the example of the first embodiment (match corresponds to parallel magnetization directions), the combined resistance of the comparators 1002 corresponding to a full match may be determined to be a value between 20 KΩ and 21 KΩ, such as 20.47 KΩ. In this embodiment, once this combined resistance corresponding to a full match is determined, the reference 1014 can be more accurately determined. In this example, the resistance of a comparator 1002 corresponding to a mismatch may still have some uncertainty. For example, this resistance may range between 1.95 KΩ and 2.05 KΩ. However, this uncertainty, because it is associated with a single comparator 1002, may be significantly less than the uncertainty in the combined resistance of the comparators 1002 corresponding to a full match that has been removed by self-referencing.
In the first embodiment (match corresponds to parallel magnetization directions), to perform self-referencing of the comparators 1002 connected in series to a full matching configuration, the storage magnetization and sense magnetization directions of each of the comparators 1002 can be aligned to mimic a full matching configuration. In one embodiment, to align the stored magnetization and the sense magnetization directions of the comparators 1002 in parallel, the field lines 912 can generate an applied magnetic field Hparallel in the direction parallel to the sense magnetization that is greater than the sum of Hexchange and Hcoupling. The exchange magnetic field Hexchange corresponds to the magnetic field needed to overcome the stored magnetization (if antiparallel to the sense magnetization), in the absence of coupling between the stored magnetization and the sense magnetization. The magneto-static coupling magnetic field Hcoupling corresponds to the magnetic field needed to overcome the antiparallel component of the sense magnetization due to coupling with the stored magnetization. While applying the magnetic field Hparallel, the storage magnetization and the sense magnetization directions can be aligned in parallel, regardless of the stored data in the comparators 1002, and also without unpinning the storage magnetization direction. Because the storage magnetization direction is not unpinned, when the magnetic field Hparallel is removed, the storage magnetization can return to its stored value.
In the second embodiment (match corresponds to antiparallel magnetization directions), to perform self-referencing of the comparators 1002 connected in series to a full matching configuration, no applied magnetic field analogous to Hparallel is needed. Instead, the storage magnetization and sense magnetization directions of each of the comparators 1002 may be self-aligned in an antiparallel state by magneto-static coupling between the storage magnetization and the sense magnetization. As described previously with reference to
In one embodiment, self-referencing of the comparators 1002 can be performed when programming or configuring the check engine 1000, or on power up of the check engine 1000. In this embodiment, self-referencing is not performed as part of matching a target pattern to a stored pattern, so the matching still can occur in one cycle. Alternatively or in addition, self-referencing of the comparators 1002 can be performed on the fly. For example, self-referencing of the comparators 1002 can be performed in a separate cycle prior to matching a target pattern to a stored pattern, so that the matching (including the cycle for self-referencing) can take two cycles to complete. Alternatively or in addition, self-referencing of the comparators 1002 can be performed periodically. In one embodiment, a measured value from the self-referencing of the comparators 1002, such as a measured value of the combined resistance or a measured value of the input 1010, can be latched into a sample-and-hold circuit so that the measured value is available for a predetermined time period dependent on the design of the sample-and-hold circuit.
As described previously, when matching is configured to correspond to parallel magnetization directions, the applied magnetic field Hparallel is generated as part of self-referencing. Configuring matching to correspond to antiparallel magnetization directions may be advantageous because there is no need to generate the applied magnetic field Hparallel as part of self-referencing. This can result in reduced power consumption and reduced heat generation, and can also reduce the complexity of circuitry associated with the check engine 1000.
Referring to
The architecture of
The check engine 1100 has a parallel architecture for match-in-place (MIP) applications. In one embodiment, the comparators 1002A-1002N are connected in parallel. The comparators 1002A-1002N may each be connected to a corresponding bit line 916A-916N. In one embodiment, the comparators 1002A-1002N may each be connected to a corresponding selection transistor 1102A-1102N. Heating current through the bit lines 916A-916N can be controlled by the transistor 1004 and the selection transistors 1102. In one embodiment, each of the comparators 1002A-1002N may be connected to a corresponding field line 912A-912N.
As described previously with reference to
As compared to the embodiment of
Referring to
In one embodiment, self-referencing of the comparators 1002 can be performed when programming or configuring the check engine 1000, or on power up of the check engine 1000. However, with reference to the embodiment of
Alternatively, self-referencing of the comparators 1002 can be performed in a separate cycle prior to matching a target pattern to a stored pattern. In this approach, for example, a subset of the comparators 1002 corresponding to locations of “0's” in the target pattern are self-referenced prior to matching “0's” in the target pattern to the stored pattern. The selection transistors 1102 corresponding to this subset of the comparators 1002 are saturated to allow current to flow through each of this subset of the comparators 1002. The selection transistors 1102 corresponding to the remainder of the comparators 1002 are turned off so that current does not flow through the remainder of the comparators 1002. Self-referencing of a subset of the comparators 1002 corresponding to locations of “1's” in the target pattern may be performed in a similar way. In the embodiment of
To speed up operation of embodiments in which a match takes multiple cycles to complete, the processing associated with the match can be allocated across multiple check engines such as the check engines 1000, 1100, and 1200. For example, with reference to
Referring to
While the invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.
Cambou, Bertrand F., El Baraji, Mourad, Berger, Neal
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