Semiconductor device and method of manufacturing same

Abstract

A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 13/544,376, filed Jul. 9, 2012, which is a divisional of Ser. No. 12/877,882, filed Sep. 8, 2010, now U.S. Pat. No. 8,237,219, and is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-208306, filed on Sep. 9, 2009, the entire contents of which is incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor device including a transistor, and to a method of manufacturing the semiconductor device.

BACKGROUND

In recent years, consumers have demanded that a semiconductor device have a higher packing density and higher performance, and those demands have increased the number of MOS transistors formed on a semiconductor substrate.

A general MOS transistor has impurity regions serving as a source and a drain (hereinafter referred to as “source and drain regions” or a “source/drain region” in a representative way), a channel region, and an extension region disposed at each end of the channel region. Such a MOS transistor is formed, for example, by the method described below.

A gate insulation film and a gate electrode are formed on a silicon semiconductor substrate. Extension regions are formed by ion-implanting impurities into the semiconductor substrate with the gate electrode being used as a mask. Sidewall spacers are formed on both sides of the gate electrode. The source and drain regions are formed by ion-implanting impurities into the semiconductor substrate at a higher concentration up to a depth deeper than the extension regions with the gate electrode and the sidewall spacers being used as masks. Heat treatment (thermal processing) is performed to activate the impurities having been introduced to the semiconductor substrate. A MOS transistor having the extension regions is completed in this way.

As described above, a heat treatment operation for activating the impurities (hereinafter also referred to as an “activation heat treatment” operation) is performed in a process of manufacturing the MOS transistor. In the heat treatment operation, the impurities implanted to the source and drain regions are diffused into the interior of the semiconductor substrate under the gate electrode such that the spacing between the source and the drain (hereinafter also referred to as the “channel length”) is shortened. The shorter spacing between the source and the drain gives rise to the so-called channel shortening effect with which a threshold voltage is reduced. For that reason, the activation heat treatment is performed in a short time by using, e.g., the RTA (Rapid Thermal Annealing) process. Further, the thickness of each sidewall spacer is set to a value that is suitable to minimize the shorter channel effect caused by the diffusion of the impurities.

It is known that the diffusion distance of the impurities during the heat treatment operation is related to the impurity concentration. In view of such a point, a MOS transistor has been proposed in which the impurity concentration in the source is set higher than that in the drain and the thickness of the sidewall spacer on the same side as the source is increased to suppress an overlap between the source and the gate electrode, as disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2005-5372.

SUMMARY

A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

The object and advantages of the invention will be realized and attained by at least the feature, elements, and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a sectional view of a semiconductor substrate before activation heat treatment;

FIG. 1B is a sectional view of the semiconductor substrate after the activation heat treatment;

FIG. 2A is a chart illustrating a simulation result of an impurity concentration profile in a transistor A after the heat treatment;

FIG. 2B is a chart illustrating a simulation result of an impurity concentration profile in a transistor B after the heat treatment;

FIG. 3A is a graph illustrating impurity concentration distributions in the horizontal direction in the transistors A and B immediately after impurity implantation and after the activation heat treatment;

FIG. 3B is a graph illustrating impurity concentration distributions in the vertical direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment;

FIG. 4 is a graph illustrating the relationship between a threshold voltage Vth and a gate length L in each of the transistors A and B;

FIG. 5 is a top plan view of a semiconductor device according to a first embodiment;

FIGS. 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, and 14 are sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment;

FIG. 15A is a chart illustrating an impurity concentration profile in the transistor A after the heat treatment;

FIG. 15B is a chart illustrating an impurity concentration profile in the transistor B after the heat treatment;

FIG. 16A is a graph illustrating impurity concentration distributions in the horizontal direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment;

FIG. 16B is a graph illustrating impurity concentration distributions in the vertical direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment;

FIG. 17 is a graph illustrating the relationship between the threshold voltage Vth and the gate length L in each of the transistors A and B;

FIG. 18 is a sectional view of a semiconductor device according to a modification of the first embodiment;

FIG. 19 is a top plan view of a semiconductor device according to a second embodiment;

FIGS. 20A, 20B, 21A, 21B, and 21C are sectional views illustrating a method of manufacturing the semiconductor device according to the second embodiment;

FIG. 22 is a sectional view of a semiconductor device according to a modification of the second embodiment;

FIG. 23 is a top plan view of a semiconductor device according to a third embodiment; and

FIG. 24 is a top plan view of a semiconductor device according to a fourth embodiment.

DESCRIPTION OF EMBODIMENTS

It has been generally thought that, if the impurity concentration is the same, the diffusion distance of impurities during heat treatment may also be the same. However, experiments and studies made by the inventors of this application have proved that, when an MOS transistor having a microstructure is formed, the amount (distance) of diffusion of impurities changes depending on the size of a source/drain region even with the same impurity concentration. As a result of such a phenomenon, the channel length changes depending on the size of the source/drain region even in the MOS transistor that has been manufactured under the same conditions.

When a transistor has a large gate length, e.g., a large width of a gate electrode, the difference in the amount of diffusion of impurities depending on different sizes of the source/drain region hardly causes a problem. However, when a transistor has a small gate length, an influence of change in the channel length caused by the difference in the size of the source/drain region is so large as to make characteristics, e.g., a threshold voltage, different between the transistor having the large source/drain region and the transistor having the small source/drain region.

For convenience in layout, for example, a semiconductor device includes a plurality of MOS transistors in which the sizes of their source/drain regions differ from each other. In an electronic circuit formed by using a plurality of MOS transistors, different characteristics of the MOS transistors may cause an operation failure.

FIG. 1A is a sectional view of a semiconductor substrate before activation heat treatment, and FIG. 1B is a sectional view of the semiconductor substrate after the activation heat treatment. In FIGS. 1A and 1B, the left side represents a MOS transistor having a smaller source/drain region (hereinafter referred to as a “transistor A”), and the right side represents a MOS transistor having a larger source/drain region (hereinafter referred to as a “transistor B”).

In FIGS. 1A and 1B, reference numeral 10 denotes a semiconductor substrate, 11a and 11b denote gate insulation films, 12a and 12b denote gate electrodes, 13a and 13b denote extension regions, 14a and 14b denote source/drain regions, 15a and 15b denote sidewall spacers, and 16 denotes a device separation region. Further, in FIGS. 1A and 1B, the distance from the sidewall spacer 15a of the transistor A to the device separation region 16 is indicated by Wa, and the distance from the sidewall spacer 15b of the transistor B to the device separation region 16 is indicated by Wb. Wb is larger than Wa. Hereinafter, the distance from the sidewall spacer to the device separation region, e.g., the length of each of the source and the drain in a direction perpendicular to the gate electrode, is also called a “source/drain width”.

As illustrated in FIG. 1A, in the state before the activation heat treatment, edges of the source/drain regions 14a and 14b are substantially coincident with outer edges of the sidewall spacers 15a and 15b. When the heat treatment is carried out in such a state, the edges of the source/drain regions 14a and 14b come closer respectively to the gate electrodes 13a and 13b due to diffusion of impurities, as illustrated in FIG. 1B.

When heat treatment conditions are set to be adapted for the transistor A, the diffusion distance of the impurities is increased in the transistor B and the spacing between the source and drain regions 14b, e.g., the channel length, is shortened.

FIG. 2A is a chart illustrating an impurity concentration profile in the transistor A after the heat treatment, and FIG. 2B is a chart illustrating an impurity concentration profile in the transistor B after the heat treatment. FIG. 3A is a graph illustrating impurity concentration distributions in the horizontal direction in the transistors A and B immediately after impurity implantation and after the activation heat treatment. A horizontal axis in FIG. 3A represents the distance from the gate electrode at a position indicated by a line H in FIGS. 2A and 2B. A vertical axis in FIG. 3A represents the impurity concentration. FIG. 3B is a graph illustrating impurity concentration distributions in the vertical direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment. A horizontal axis in FIG. 3B represents the depth from the surface of the semiconductor substrate at a position indicated by a line V in FIGS. 2A and 2B. A vertical axis in FIG. 3B represents the impurity concentration.

It is here assumed that the distance Wa from the sidewall spacer 15a in the transistor A to the device separation region 16 is 100 nm, and the distance Wb from the sidewall spacer 15b in the transistor B to the device separation region 16 is 1000 nm. Further, B (boron) is ion-implanted as channel impurities into the semiconductor substrate. Still further, P (phosphorous) is ion-implanted into the source/drain regions 14a and 14b. The widths of the gate electrodes 12a and 12b, e.g., the gate lengths, are each 45 nm, and the widths of the sidewall spacers 15a and 15b are each 38 nm. The position of a pn-junction is represented by a position indicated by a dotted line in each of FIGS. 2A and 2B and by a position at which the concentration of B (boron) and the concentration of P (phosphorous) are substantially equal to each other in FIGS. 3A and 3B. The width of the sidewall spacer represents the distance from an inner side to an outer side of the sidewall spacer when the MOS transistor is viewed from above.

As seen from FIGS. 3A and 3B, the diffusion distance of the impurities in the transistor B having the larger source/drain regions is larger than that in the transistor A having the smaller source/drain regions.

FIG. 4 is a graph illustrating the relationship between a threshold voltage Vth and a gate length L in each of the transistors A and B. In FIG. 4, a horizontal axis represents the gate length L, and a vertical axis represents the threshold voltage Vth. As seen from FIG. 4, when the gate length L is about 50 nm, the difference in the threshold voltage between the transistors A and B is comparatively small. However, as the gate length L reduces, the difference in the threshold voltage between the transistors A and B increases.

The reasons for increasing the diffusion distance of the impurities during the heat treatment in the larger source/drain region have not yet been fully explained. These reasons are explained next. Impurity ions implanted into the semiconductor substrate move in pair with point defects in crystals toward the side where the impurity concentration is lower. When the source/drain region is large, a total number of the impurity ions and the point defects is large and so is the amount of impurities moving in pair with the point defects. Further, in a portion of the source/drain region near the device separation region, the impurities are taken into the device separation region and the density of the impurities is reduced. Accordingly, when the source/drain region is small, a proportion of the impurities diffused toward the device separation region is increased and a proportion of the impurities diffused toward a zone under the gate electrode is relatively reduced. For those reasons, even when the impurity concentration is the same, the diffusion distance of the impurities toward the zone under the gate electrode differs depending on the size of the source/drain region.

FIG. 5 is a top plan view of a semiconductor device according to a first embodiment. The first embodiment is described in connection with the case where two types of n-type MOS transistors A and B having difference sizes of the source/drain regions are formed as illustrated in FIG. 5. It is here assumed that Wa representing the size of the source/drain region, e.g., the source/drain width, in the transistor A is 100 nm, and Wb representing the size of the source/drain region in the transistor B is 1000 nm. The gate length L is 45 nm in each of the transistors A and B, and the gate width W is 160 nm in each of the transistors A and B.

When manufacturing the semiconductor device illustrated in FIG. 5, if the heat treatment is performed under conditions adapted for the transistor A having the smaller source/drain region, the diffusion distance of the impurities implanted into the transistor B having the larger source/drain region is increased too and the desired channel length may not be obtained. To cope with such a problem, in this first embodiment, sidewall spacers 32a are formed on both sides of a gate electrode 29a in the transistor A, while sidewall spacers 33b are formed on both sides of a gate electrode 29b in the transistor B in addition to sidewall spacers 32b each having the same width as that of the sidewall spacer 32a.

FIGS. 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, and 14 are sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment in order of successive operations. The semiconductor device includes an n-type MOS transistor and a p-type MOS transistor. The n-type MOS transistor and the p-type MOS transistor are formed through basically similar steps except that the conductivity types of impurities introduced into the semiconductor substrate differ from each other. Therefore, description of a method of manufacturing the p-type MOS transistor is omitted here.

As illustrated in FIG. 6A, a p-type silicon semiconductor substrate 20 having a resistivity of 10 Ωcm is prepared and the surface of the semiconductor substrate 20 is thermally oxidized to form a thermally-oxidized film 21 in a thickness of, e.g., 10 nm. Then, a silicon nitride film 22 is formed on the thermally-oxidized film 21 in a thickness of, e.g., 90 nm by the Chemical Vapor Deposition (CVD) process.

Operations until obtaining the structure illustrated in FIG. 6B will be described below. After forming the silicon nitride film 22 through the above-described operations, a photoresist film is formed on the silicon nitride film 22. Then, exposure and development processes are performed to leave the photoresist film on the silicon nitride film 22 that is positioned on each device region. Further, the silicon nitride film 22 and the thermally-oxidized film 21 are etched away with the photoresist film being used as a mask, wherein the surface of the semiconductor substrate 20 is exposed.

The semiconductor substrate 20 is etched up to a depth of about 260 nm to 350 nm by the dry etching process, thereby forming grooves 23. In this first embodiment, the depth of each groove 23 is set to 280 nm, for example. Then, the photoresist film is removed.

As illustrated in FIG. 7A, a silicon oxide 24 is deposited over the entire surface of the semiconductor substrate 20 by, e.g., the CVD process, wherein the grooves 23 are filled with the silicon oxide 24. Then, as illustrated in FIG. 7B, the silicon oxide 24 is polished by, e.g., the Chemical Mechanical Polishing (CMP) process to such an extent that the silicon nitride film 22 is exposed. Device separation regions 26 are thus formed while the silicon oxide 24 remains in the grooves 23. As illustrated in FIG. 8A, the silicon nitride film 22 and the thermally-oxidized film 21 are removed by, e.g., the dry etching process to make the surface of the semiconductor substrate 20 exposed.

Although the device separation regions 26 are formed by the Shallow Trench Isolation (STI) process in this first embodiment, the device separation regions may be formed by the Local Oxidation of Silicon (LOCOS) process, for example.

Operations until obtaining the structure illustrated in FIG. 8B will be described below. After forming the device separation regions 26 through the above-described steps, the substrate surface in each device region is thermally oxidized to form a sacrifice oxide film in a thickness of, e.g., 10 nm. Then, B (boron) is ion-implanted through the sacrifice oxide film into a region where the n-type MOS transistor is to be formed, thereby forming a p-well. Ion implanting conditions at that time are set, for example, to an acceleration voltage of 120 keV, a dose amount of 3×10¹³ cm⁻², and an irradiation angle of 0°, e.g., irradiation in a direction perpendicular to the substrate surface.

Into the substrate surface of the region where the n-type MOS transistor is to be formed, B (boron) is ion-implanted as channel impurities under conditions of the acceleration voltage of 10 keV, the dose amount of 1.8×10¹³ cm⁻², and the irradiation angle of 7°, for example. The sacrifice oxide film is removed to make the surface of the semiconductor substrate 20 exposed. The ion-implanted impurities are activated by performing heat treatment for 10 sec at temperature of 1000° C. by, e.g., the RTA process.

The substrate surface in each device region is thermally oxidized by the thermal oxidation process to form a gate insulation film 28 in thickness of, e.g., 1.6 nm.

Operations until obtaining the structure illustrated in FIG. 9A will be described below. After forming the gate insulation film 28 through the above-described process, a polysilicon film is formed in a thickness of 90 nm on the gate insulation film 28 by, e.g., the CVD process. A photoresist film is formed on the polysilicon film by the photolithography process, and then the polysilicon film and the gate insulation film 28 are patterned by the dry etching process with the photoresist film being used as a mask. Thereafter, the photoresist film is removed. Gate electrodes 29a and 29b made of polysilicon, for example, illustrated in FIG. 9A, are formed in such a manner.

Operations until obtaining the structure illustrated in FIG. 9B will be described below. Pocket regions 30a and 30b are formed after forming the gate electrodes 29a and 29b through the above-described process. The pocket regions 30a and 30b are formed, by way of example, as follows. In (indium) is ion-implanted into portions of the semiconductor substrate 20 under respective edges of the gate electrodes 29a and 29b four times in total under conditions of the acceleration energy (voltage) of 70 keV, the dose amount of 8×10¹² cm⁻², and the irradiation angle of 30°, for example, while the irradiation direction is changed in units of 90°. As a result, the pocket regions 30a and 30b are formed under the edges of the gate electrodes 29a and 29b.

With the gate electrodes 29a and 29b being used as masks, As (arsenic) is shallowly ion-implanted into the semiconductor substrate 20 under the conditions of the acceleration energy (voltage) of 1 keV, the dose amount of 2×10¹⁵ cm⁻², and the irradiation angle of 0°, for example, thereby forming extension regions 31a and 31b.

A silicon nitride film is formed in a thickness of, e.g., 40 nm over the entire upper surface of the semiconductor substrate 20 by the CVD process. The silicon nitride film is etched back, as illustrated in FIG. 10A, to form the sidewall spacers 32a and 32b, each having a width of, e.g., 38 nm, on both sides of each of the gate electrodes 29a and 29b. The width of each of the sidewall spacers 32a and 32b may be controlled depending on the thickness of the silicon nitride film and the conditions in etching back the silicon nitride film.

As illustrated in FIG. 10B, a silicon oxide film 33 is formed in a thickness of, e.g., 8 nm over the entire upper surface of the semiconductor substrate 20 by the CVD process. The silicon oxide film 33 is etched back, as illustrated in FIG. 11A, to form the sidewall spacers 33a and 33b, each having a width of, e.g., 5 nm, adjacent to the sidewall spacers 32a and 32b, respectively.

By using the photolithography process, as illustrated in FIG. 11B, a photoresist film 35 is formed to cover a region where the transistor B is to be formed. As illustrated in FIG. 12A, the sidewall spacers 33a in a region where the transistor A is to be formed are removed by selective etching that utilizes a difference in etching rate between the silicon nitride film and the silicon oxide film. Thereafter, the photoresist film 35 is removed.

In the above-described example, the sidewall spacers 33a and 33b are formed on both sides of each of the transistor A and the transistor B and the sidewall spacers 33a are removed while leaving the sidewall spacers 33b. As an alternative example, the process may be modified such that a photoresist film covering the transistor B is formed in the state illustrated in FIG. 10B, the silicon oxide film 33 covering the transistor A is removed, and the sidewall spacers 33b are formed over the transistor B after removing the photoresist film.

With the gate electrodes 29a and 29b and the sidewall spacers 32a, 32b and 33b being used as masks, as illustrated in FIG. 12B, P (phosphorous) is ion-implanted into the semiconductor substrate 20 under conditions of the acceleration energy (voltage) of 15 keV, the dose amount of 5×10¹³ cm⁻², and the irradiation angle of 0°, for example. P is further ion-implanted into the semiconductor substrate 20 under conditions of the acceleration energy (voltage) of 8 keV, the dose amount of 10¹⁶ cm⁻², and the irradiation angle of 0°, for example. As a result, source/drain regions 36a and 36b are formed respectively on both sides of the gate electrode 29a and the sidewall spacers 32a and on both sides of the gate electrode 29b and the sidewall spacers 32b and 33b at a depth deeper than the extension regions 31a and 31b with higher impurity concentrations than them.

Heat treatment is performed at temperature of 1030° for 1 sec by, e.g., the RTA process to activate the impurities that have been implanted into the pocket regions 30a and 30b, the extension regions 31a and 31b, and the source/drain regions 36a and 36b. The RTA process may be practiced, for example, by laser annealing or flash lamp annealing. During such an activation heat treatment step, as illustrated in FIG. 13A, the impurities implanted into the source/drain regions 36a and 36b are diffused toward the gate electrodes 29a and 29b, wherein the channel length is shortened.

As described above, the diffusion distance of the impurities changes depending on the size of the source/drain region. In this first embodiment, therefore, the diffusion distance of the impurities is larger in the source/drain region 36b than in the source/drain region 36a. This means that, if only the sidewall spacer 32b having the same width as the sidewall spacer 32a in the transistor A is formed in the transistor B and the conditions for the activation heat treatment are set to be adapted for the transistor A, the channel length may be shortened and the so-called channel shortening effect may be generated in the transistor B. In this first embodiment, however, since the sidewall spacers 32b and 33b are formed on both sides of the gate electrode 29b in the transistor B, the impurities may be suppressed from being excessively diffused toward a zone under the gate electrode 29b. Accordingly, the generation of the channel shortening effect may be impeded.

Silicide films 37a, 37b, 37c and 37d are formed as illustrated in FIG. 13B. The silicide films 37a, 37b, 37c and 37d are formed, by way of example, as follows. Co (cobalt) is deposited to form a cobalt film on the entire upper surface of the semiconductor substrate 20 by, e.g., the sputtering process, and heat treatment is then performed on the semiconductor substrate 20. With the heat treatment, the cobalt reacts with the silicon in respective upper portions of the source/drain regions 36a and 36b and the gate electrodes 29a and 29b, wherein the silicide films 37a, 37b, 37c and 37d are formed. Thereafter, the unreacted cobalt is removed by etching.

As illustrated in FIG. 14, a silicon nitride film 38 is formed in a thickness of, e.g., 80 nm over the entire upper surface of the semiconductor substrate 20 by the CVD process. An interlayer insulation film 39 made of, e.g., Undoped Silicate Glass (USG) and Tetra-Ethyl-Ortho-Silicate (TEOS), is formed in a thickness of 145 nm by the CVD process. Contact holes extending from an upper surface of the interlayer insulation film 39 so as to reach the silicide films 37a and 37b on the source/drain regions 36a and 36b are formed by performing a photolithography step and an etching step.

A Ti film and a TiN film are formed, as an adhesion layer (glue layer), in a thickness of, e.g., 14 nm over the entire upper surface of the semiconductor substrate 20 by the sputtering process, and W (tungsten) is then deposited in a thickness of about 200 nm such that the contact holes are filled with W. Thereafter, the entire surface is flattened by performing the CMP polishing until an upper surface of the interlayer insulation film 39 is exposed. As a result, contact plugs 40 are formed which are electrically connected to the source/drain regions 36a and 36b. A desired multilayered wiring structure is then formed by successively performing a wiring forming operation, an interlayer insulation film forming operation, a contact plug forming operation, and so on.

FIG. 15A is a chart illustrating an impurity concentration profile in the transistor A after the heat treatment, and FIG. 15B is a chart illustrating an impurity concentration profile in the transistor B after the heat treatment. FIG. 16A is a graph illustrating impurity concentration distributions in the horizontal direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment. A horizontal axis in FIG. 16A represents the distance from the gate electrode at a position indicated by a line H in FIGS. 15A and 15B. A vertical axis in FIG. 16A represents the impurity concentration. FIG. 16B is a graph illustrating impurity concentration distributions in the vertical direction in the transistors A and B immediately after the impurity implantation and after the activation heat treatment. A horizontal axis in FIG. 16B represents the depth from the surface of the semiconductor substrate at a position indicated by a line V in FIGS. 15A and 15B. A vertical axis in FIG. 16B represents the impurity concentration.

It is here assumed that the distance Wa from the sidewall spacer 32a in the transistor A to the device separation region 26 is 100 nm, and the distance Wb from the sidewall spacer 33b in the transistor B to the device separation region 26 is 1000 nm. Further, B (boron) is ion-implanted as channel impurities into the semiconductor substrate. Still further, P (phosphorous) is ion-implanted into the source/drain regions 36a and 36b. The widths of the gate electrodes 29a and 29b, e.g., the gate lengths, are each 45 nm. The width of the sidewall spacer 32a in the transistor A is 38 nm, and the total width of the sidewall spacers 32b and 33b in the transistor B is 43 nm, for example. The position of a pn-junction is represented by a position indicated by a dotted line in each of FIGS. 15A and 15B and by a position at which the concentration of B (boron) and the concentration of P (phosphorous) are equal to each other in FIGS. 16A and 16B.

As seen from FIGS. 16A and 16B, the distance between the pn-junction and the edge of the gate electrode after the heat treatment is substantially the same in the transistors A and B that have been manufactured according to the first embodiment.

FIG. 17 is a graph illustrating the relationship between a threshold voltage Vth and a gate length L in each of the transistors A and B that have been manufactured according to the first embodiment. In FIG. 17, a horizontal axis represents the gate length L, and a vertical axis represents the threshold voltage Vth. As seen from FIG. 17, in the transistors A and B manufactured according to the first embodiment, the threshold voltage is substantially the same over the range from 40 nm to 50 nm of the gate length.

While the width of the sidewall spacer 32a in the transistor A is 38 nm and the total width of the sidewall spacers 32b and 33b in the transistor B is 43 nm in this first embodiment, those values are given by way of example. Preferably, the widths of the sidewall spacers in the transistors A and B are set by executing simulation calculations of the impurity concentration distributions after the heat treatment with, for example, the sizes of the source/drain regions 36a and 36b being parameters, and by determining the widths of the sidewall spacers such that characteristics of the transistors A and B substantially match with each other, or that the difference in the characteristics falls within an allowable range.

In the first embodiment, as illustrated in FIGS. 12B, 13A and 13B, after ion-implanting P (phosphorous) into the semiconductor substrate 20, the silicide films 37b, e.g. are formed while the sidewall spacers 33b remain in the region where the transistor B is to be formed. Alternatively, as illustrated in FIG. 18, the silicide forming step may be carried out in a state that the sidewall spacers 33b in the region where the transistor B is to be formed have been removed, after the ion-implantation of P or after the activation heat treatment. Such a modification is advantageous in that, as illustrated in FIG. 18, an area of each silicide film 37b in contact with the source/drain region 36b is increased and an apparent resistance value of the source/drain region 36b is reduced.

FIG. 19 is a top plan view of a MOS transistor according to a second embodiment. The second embodiment is described below in FIG. 19, a pair of source and drain regions disposed on both sides the gate electrode have sizes differing from each other. In the second embodiment, as illustrated in FIG. 19, a source/drain region 54a on the left side of a gate electrode 51 has an L-shape, and a source/drain region 54b on the right side of the gate electrode 51 has a rectangular shape. It is assumed in FIG. 19 that the gate length L is 45 nm, a length denoted by W1 is 160 nm, a length denoted by W2 is 240 nm, a length denoted by Wc1 is 300 nm, and a length denoted by Wc2 is 280 nm, for example.

More specifically, in a transistor illustrated in FIG. 19, a length Wc1 from a second sidewall spacer 53 on the left side of the gate electrode 51 to a device separation region and a length Wc1 from a first sidewall spacer 52 on the right side of the gate electrode 51 to the device separation region are each 300 nm, for example. Areas of the source/drain regions 54a and 54b differ from each other. In such a case, impurities ion-implanted into the source/drain region 54a having the larger area are diffused through a larger distance during the heat treatment in comparison with impurities ion-implanted into the source/drain region 54b having the smaller area. In view of the above point, only the first sidewall spacer 52 is disposed on the right side of the gate electrode 51, and the second sidewall spacer 53 is disposed on the left side of the gate electrode 51 in addition to the first sidewall spacer 52.

FIGS. 20A, 20B, 21A, 21B, and 21C are sectional views illustrating a method of manufacturing the semiconductor device according to the second embodiment in order of successive operations.

As illustrated in FIG. 20A, a device separation region 46, a gate insulation film 41, the gate electrode 51, pocket regions 43, extension regions 44, the (first) sidewall spacers 52, and the (second) sidewall spacers 53 are formed on a semiconductor substrate 50 in a similar manner to that in the first embodiment. Operations until obtaining such a state are similar to those illustrated in FIGS. 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B and 11A. In this second embodiment, it is assumed that the sidewall spacers 52 are each formed of a silicon nitride film having a width of 38 nm, for example. Also, for example, the sidewall spacers 53 are each formed of a silicon oxide film having a width of 5 nm.

After coating a photoresist over the entire upper surface of the semiconductor substrate 50, exposure and development processes are performed to form a photoresist film 55 covering a zone where the source/drain region is to be formed on the left side of the gate electrode 51.

As illustrated in FIG. 20B, the sidewall spacer 53 on the right side of the gate electrode is removed by etching with the photoresist film 55 being used as a mask. Thereafter, the photoresist film 55 is removed.

As illustrated in FIG. 21A, P (phosphorous) is ion-implanted into the semiconductor substrate 50 with the gate electrode 51 and the sidewall spacers 52 and 53 being used as masks, thereby forming the source/drain regions 54a and 54b. Heat treatment is performed at temperature of 1030° for 1 sec by, e.g., the RTA process to activate the impurities that have been implanted into the pocket regions 43, the extension regions 44, and the source/drain regions 54a and 54b.

During the activation heat treatment operation described above, as illustrated in FIG. 21B, the impurities implanted into the source/drain regions 54a and 54b are diffused such that the source/drain region 54a and 54b come closer to the gate electrode 51. On that occasion, the diffusion distance of the impurities is larger in the source/drain region 54a having the larger area than in the source/drain region 54b having the smaller area. In this second embodiment, however, since the sidewall spacer 53 is formed on the same side as the source/drain region 54a in addition to the sidewall spacer 52, the distances from the gate electrode 51 to the source/drain region 54a and 546b are substantially equal to each other.

As illustrated in FIG. 21C, silicide films 56a, 56b and 56c are formed respectively on the source/drain regions 54a and 54b and the gate electrode 51. Alternatively, as illustrated in FIG. 22, the silicide films 56a, for example, may be formed after removing the sidewall spacer 53 on the same side as the source/drain region 54a. A subsequent operation of forming a multilayered wiring structure is similar to that in the first embodiment, and hence description of that operation is omitted here.

The second embodiment may also hinder excessive diffusion of the impurities into a zone under the gate electrode 51 and provide desired transistor characteristics as in the first embodiment.

FIG. 23 is a top plan view of a semiconductor device according to a third embodiment. In the third embodiment, as illustrated in FIG. 23, three transistors T1, T2 and T3 are formed in one rectangular device region surrounded by a device separation region 66. The source/drain widths on both sides of a gate electrode 61a of the transistor T1 are each W1. Also, the source/drain width on the left side of a gate electrode 61b of the transistor T2 is W1, and the source/drain width on the right side of the gate electrode 61b is W2 (W1<W2). Further, the source/drain width on the left side of a gate electrode 61c of the transistor T3 is W2, and the source/drain width on the right side of the gate electrode 61c is W1. Each of the transistors T1, T2 and T3 has a gate width W, for example.

The source/drain width represents the distance from a sidewall spacer to the device separation region when no other gate electrodes are present between the gate electrode and the device separation region as in the first and second embodiments. When a plurality of transistors are formed in one device region as in this third embodiment, the source/drain width also represents the distance from a midpoint between respective sidewall spacers of the adjacent transistors to each of the sidewall spacer.

In the following description, a region from a sidewall spacer 62a on the left side in the transistor T1 to the device separation region 66 is called a source/drain region 64a, and a region from a sidewall spacer 62a on the right side in the transistor T1 to a midpoint between the transistors T1 and T2 (e.g., a midpoint between respective sidewall spacers of those transistors; this is similarly applied to the term “midpoint” appearing below) is called a source/drain region 64b. A region from a sidewall spacer 62b on the left side in the transistor T2 to the midpoint between the transistors T1 and T2 is called a source/drain region 64c, and a region from sidewall spacers 62b and 63b on the right side in the transistor T2 to a midpoint between the transistors T2 and T3 is called a source/drain region 64d. A region from sidewall spacers 62c and 63c on the left side in the transistor T3 to the midpoint between the transistors T2 and T3 is called a source/drain region 64e, and a region from a sidewall spacer 62c on the right side in the transistor T3 to the device separation region 66 is called a source/drain region 64f.

In the semiconductor device illustrated in FIG. 23, areas of the source/drain regions 64d and 64e differ from areas of the other source/drain regions 64a, 64b, 64c and 64f. In such a case, impurities ion-implanted into the source/drain regions 64d and 64e having the larger areas are diffused through larger distances during the heat treatment in comparison with impurities ion-implanted into the source/drain regions 64a, 64b, 64c and 64f having the smaller areas.

In this third embodiment, the sidewall spacers 62a, 62b and 62c, which are formed by etching back silicon nitride films, are disposed on both sides of each of the gate electrode 61a, 61b and 61c of the transistors T1, T2 and T3, respectively. Further, the sidewall spacers 63b and 63c, which are formed by etching back silicon oxide films, are disposed on the right side of the gate electrode 61b of the transistor T2 and on the left side of the gate electrode 61c of the transistor T3, respectively. With such an arrangement, the distances from the gate electrodes 61b and 61c to the source/drain regions 64d and 64e are increased and the impurities are hindered from being excessively diffused into zones under the gate electrodes 61b and 61c from the source/drain regions 64d and 64e during the activation heat treatment. As a result, desired characteristics may be obtained.

The semiconductor device according to the third embodiment may be manufactured substantially in a similar manner to that in the second embodiment except for forming a plurality of transistors on one device region. More specifically, the sidewall spacers made of silicon nitride films and the sidewall spacers made of silicon oxide films are formed on both sides of each of the gate electrode 61a, 61b and 61c of the transistors T1, T2 and T3, which share one common device region. Then, the sidewall spacers made of silicon oxide films and positioned on both sides of the gate electrode 61a, on the right side of the gate electrode 61b, and on the left side of the gate electrode 61c are removed by the photolithography process and the etching process.

FIG. 24 is a top plan view of a semiconductor device according to a fourth embodiment. In the fourth embodiment, as illustrated in FIG. 24, two transistors T1 and T2 are formed while sharing one common L-shaped device region surrounded by a device separation region 76. A source/drain region 74a on the left side of a gate electrode 71a of the transistor T1 has a rectangular shape, but a source/drain region 74b on the right side of the gate electrode 71a has an L-shape and has a larger area than the source/drain region 74a on the left side. Further, in the transistor T2, a source/drain region 74c on the left side of a gate electrode 71b has a larger area than a source/drain region 74d on the right side of the gate electrode 71b.

The gate width of the transistor T1 is W2. The source/drain width of the source/drain region 74a on the left side in the transistor T1 is Wc1, and the source/drain region 74b on the right side in the transistor T1 includes two portions, e.g., one having a source/drain width Wc1 and the other having a source/drain width Wc3 (Wc1<Wc3). The gate width of the transistor T2 is W1 (W1<W2). The source/drain width of the source/drain region 74c on the left side in the transistor T2 is Wc3, and the source/drain width of the source/drain region 74d on the right side in the transistor T2 is Wc1. Further, in this fourth embodiment, a region from sidewall spacers 72a and 73a on the right side of the gate electrode 71a of the transistor T1 to a midpoint between the transistors T1 and T2 is called the source/drain region 74b on the transistor T1 side. A region from sidewall spacers 72b and 73b on the left side of the gate electrode 71b of the transistor T2 to the midpoint between the transistors T1 and T2 is called the source/drain region 74c on the transistor T2 side.

In the semiconductor device illustrated in FIG. 24, areas of the source/drain regions 74b and 74c larger than those of the other source/drain regions 74a and 74d. In such a case, impurities ion-implanted into the source/drain regions 74b and 74c having the larger areas are diffused through larger distances during the heat treatment in comparison with impurities ion-implanted into the source/drain regions 74a and 74d having the smaller areas.

In this fourth embodiment, only the sidewall spacer 72a is disposed on the left side of the gate electrode 71a of the transistor T1, and the sidewall spacers 72a and 73a are disposed on the right side of the gate electrode 71a. Further, the sidewall spacers 72b and 73b are disposed on the left side of the gate electrode 71b of the transistor T2, and only the sidewall spacer 72b is disposed on the right side of the gate electrode 71b. With such an arrangement, the distances from the gate electrodes 71a and 71b to the source/drain regions 74b and 74c are increased and the impurities are hindered from being excessively diffused into zones under the gate electrodes 71a and 71b from the source/drain regions 74b and 74c during the activation heat treatment. As a result, desired characteristics may be obtained.

The widths of the sidewall spacers in the transistors T1 and T2 are set by executing simulation calculations of the impurity concentration distributions after the heat treatment with the sizes of the source/drain regions 74a and 74d being parameters, and by determining the widths of the sidewall spacers such that characteristics of the transistors T1 and T2 substantially match with each other, or that the difference in the characteristics falls within an allowable range.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming an element isolation region in a semiconductor substrate to represent a first device region and a second device region having a larger area than the first device region;

forming a first gate electrode having a first width in the first device region;

forming a second gate electrode having a third width in the second device region;

forming a first sidewall spacer having a second width on a sidewall of the first gate electrode;

forming a second sidewall spacer having a fourth width, which is wider than the second width, on a sidewall of the second gate electrode;

implanting first impurities into the first device region, using the first gate electrode and the first sidewall spacer as masks, to form a first impurity region;

implanting second impurities into the second device region, using the second gate electrode and the second sidewall spacer as masks, to form a second impurity region; and

activating the first impurities and the second impurities by heat treatment,

wherein a first length of the first impurity region in a direction perpendicular to the first gate electrode is shorter than a second length of the second impurity region in a direction perpendicular to the second gate electrode, and an impurity concentration in the first impurity region is substantially equal to an impurity concentration in the second impurity region.

2. The method according to claim 1, wherein the first width and the third width are substantially the same.

3. The method according to claim 1, wherein the second sidewall spacer includes a first insulation film and a second insulation film, and the first sidewall spacer includes a third insulation film.

4. The method according to claim , further comprising:

forming silicide films over the first impurity region and the second impurity region after the heat treatment.

5. The method according to claim 1, further comprising:

removing the second insulation film from the second sidewall spacer after the heat treatment; and

after removing of second insulation film, forming silicide films over the first impurity region and the second impurity region.

6. The method according to claim 1, further comprising:

after forming of the first gate electrode and the second gate electrode and before forming of the first sidewall spacer and the second sidewall spacer, implanting third impurities into the first device region, using the first gate electrode as a mask, to form a first extension region, and

implanting fourth impurities into the second device region, using the second gate electrode as a mask, to form a second extension region.