A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
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1. A chip package comprising:
a base re-distribution layer having an opening formed therein in a center area of the base re-distribution layer;
an adhesive layer applied to one side of the base re-distribution layer, the adhesive layer having a window formed therein free of adhesive material;
a die having a front surface affixed to the base re-distribution layer by way of the adhesive layer, wherein the die is aligned with the window formed in the adhesive layer such that only a perimeter of the front surface of the die is in contact with the adhesive layer;
a plurality of vias and a plurality of metal interconnects formed in the base re-distribution layer to electrically connect the base re-distribution layer to the die; and
a shield element positioned between the base re-distribution layer and the adhesive layer and generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer, the shield element being separated from the die by an air gap;
wherein the shield element is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
14. A chip package comprising a die packaged within and electrically coupled to a package structure, wherein the chip package is formed by:
providing a base re-distribution layer;
depositing a shield element on one surface of the base re-distribution layer so as to cover a portion thereof;
applying an adhesive layer to the base re-distribution layer and over the shield element;
ablating a portion of the adhesive layer in an area adjacent to the shield element so as to expose at least a majority of the shield element;
applying a front surface of a die to the adhesive layer such that the die is aligned with the shield element, wherein a perimeter of the die is in contact with the adhesive layer and a center portion of the die is separated from the shield element by an air gap formed therebetween;
maintaining the shield element in place during a subsequent patterning of the base re-distribution layer, the patterning forming a plurality of vias and a plurality of metal interconnects to electrically connect the base re-distribution layer to the die;
ablating a portion of the base re-distribution layer adjacent to the shield element; and
removing the shield element and the portion of the base distribution layer so as to expose the front surface of the die.
7. A chip package comprising a die packaged within and electrically coupled to a package structure, wherein the chip package is formed by:
providing a base re-distribution layer;
depositing a shield element on one surface of the base re-distribution layer so as to cover a portion thereof;
applying an adhesive layer to the base re-distribution layer and over the shield element, the adhesive layer having a portion removed therefrom to form a window in the adhesive layer that corresponds substantially to a surface area of the shield element and aligned therewith;
adhering a die to the base re-distribution layer by way of the adhesive layer, the die being positioned over the window such a perimeter of the die is in contact with the adhesive layer and an air pocket is formed between a center portion of the die and the shield element;
patterning the base re-distribution layer to include a plurality of vias and a plurality of metal interconnects, so as to electrically connect the base re-distribution layer to the die;
defining a portion of the base re-distribution layer corresponding to the window in the adhesive layer; and
removing the portion of the base re-distribution layer and the shield element from the adhesive layer so as to expose a front surface of the die.
2. The chip package of
3. The chip package of
4. The chip package of
at least one additional re-distribution layer adhered to the base re-distribution layer on a side opposite from the die; and
a plurality of vias and a plurality of metal interconnects formed in each of the additional re-distribution layers.
6. The chip package of
8. The chip package of
9. The chip package of
10. The chip package of
11. The chip package of
12. The chip package of
13. The chip package of
adhering at least one additional dielectric layer to the base re-distribution layer; and
patterning each of the at least one additional dielectric layers to include a plurality of vias and a plurality of metal interconnects.
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The present application is a divisional of, and claims priority to, U.S. patent application Ser. No. 12/843,606, filed Jul. 26, 2010, the disclosure of which is incorporated herein by reference.
Embodiments of the invention relate generally to integrated circuit chip packages and, more particularly, to chip package build-up. Chip packages are manufactured using a technique that protects the die from contamination during a build-up process of the chip package.
Integrated circuit (IC) chip packages are typically fabricated to include one or more dies that are attached to a laminate re-distribution layer. The laminate re-distribution layer is comprised of a dielectric laminate material, such as Kapton®, and is affixed to the die by way of an adhesive layer. The die(s) are electrically connected to an input/output system by way of metal interconnects routed through a plurality of additional laminate re-distribution layers that are adhered to the base re-distribution layer.
A standard chip package manufacturing or build-up process typically begins with providing of the base laminate re-distribution layer and application of an adhesive on one surface thereof. The one or more dies are then secured relative to the base laminate re-distribution layer by applying a front or active face of the die(s) onto the adhesive layer such that a bond is formed between the active face of the die(s) and the adhesive layer across the full face of the die(s). Metal interconnects are then formed and routed through the base laminate re-distribution layer and through any additional laminate re-distribution layers that are subsequently added during build-up of the chip package.
Deposition of the die(s) onto the base re-distribution layer in this manner, however, has inherent limitations in regards to the production process and the structure and functionality of the resulting chip package that is produced. That is, in some applications it is desirable that the active face of the die(s) be protected from possible contamination during the build-up process of the chip package. For example, for application of the chip package in an imaging device such as an ultra camera or similar sensing device, it is desired that the imager area (i.e., the die) be protected from contamination during the build-up process. As the imager area/die in such an application is to be left exposed upon completion of the build-up of the chip package, it is undesirable for a bond to be formed between the active face of the die and the adhesive layer across the full face of the die during the build-up process. Such a build-up would require subsequent removal of the adhesive from the imaging area and could introduce contaminates to the imaging area, thereby negatively affecting the performance of the ultra camera/sensing device.
Accordingly there is a need for a method for chip package fabrication that protects the die from contamination during the build-up process. There is a further need for the fabrication method to be readily incorporated into an assembly process, be compatible with laser drilling, be scalable, and provide for a low cost assembly.
Embodiments of the invention overcome the aforementioned drawbacks by providing a method of chip fabrication in which the chip package is manufactured using a removable shield element that is placed over the die and separated therefrom by an air pocket. The shield element protects the die from contamination during the build-up process and can be subsequently removed therefrom to expose a clean front surface of the die.
In accordance with one aspect of the invention, a chip package includes a base re-distribution layer having an opening formed therein in a center area of the base re-distribution layer, an adhesive layer applied to one side of the base re-distribution layer having a window formed therein free of adhesive material, and a die having a front surface affixed to the base re-distribution layer by way of the adhesive layer, wherein the die is aligned with the window formed in the adhesive layer such that only a perimeter of the front surface of the die is in contact with the adhesive layer. The chip package also includes a plurality of vias and a plurality of metal interconnects formed in the base re-distribution layer to electrically connect the base re-distribution layer to the die and a shield element positioned between the base re-distribution layer and the adhesive layer and generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer, with the shield element being separated from the die by an air gap. The shield element is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
In accordance with another aspect of the invention, a method of forming a chip package includes providing an initial polymer laminate layer, depositing a metallic shield element on one surface of the initial polymer laminate layer so as to cover a portion thereof, and applying an adhesive layer to the initial polymer laminate layer and over the metallic shield element, the adhesive layer having a portion removed therefrom to form a window in the adhesive layer that corresponds substantially to a surface area of the metallic shield element and aligned therewith. The method also includes adhering a die to the initial polymer laminate layer by way of the adhesive layer, with the die being positioned over the window such a perimeter of the die is in contact with the adhesive layer and an air pocket is formed between a center portion of the die and the shield element. The method further includes patterning the initial polymer laminate layer to include a plurality of vias and a plurality of metal interconnects so as to electrically connect the initial polymer laminate layer to the die, defining a portion of the initial polymer laminate layer corresponding to the window in the adhesive layer, and removing the portion of the initial polymer laminate layer and the metallic shield element from the adhesive layer so as to expose a front surface of the die.
In accordance with yet another aspect of the invention, a method for manufacturing a chip module includes providing a base re-distribution layer, depositing a shield element on one surface of the base re-distribution layer so as to cover a portion thereof, applying an adhesive layer to the base re-distribution layer and over the shield element, ablating a portion of the adhesive layer in an area adjacent to the shield element so as to expose at least a majority of the shield element, and applying a front surface of a die to the adhesive layer such that the die is aligned with the shield element, wherein a perimeter of the die is in contact with the adhesive layer and a center portion of the die is separated from the shield element by an air gap formed therebetween. The method also includes maintaining the shield element in place during a subsequent patterning of the base re-distribution layer that forms a plurality of vias and a plurality of metal interconnects to electrically connect the base re-distribution layer to the die, ablating a portion of the base re-distribution layer adjacent to the shield element, and removing the shield element and the portion of the base distribution layer so as to expose the front surface of the die.
These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings.
The drawings illustrate embodiments presently contemplated for carrying out the invention.
In the drawings:
Embodiments of the present invention provide for a method of forming a chip package. The chip package is manufactured using a shield element or protective layer to protect the surface of a die during build-up and patterning of laminate re-distribution layers of the chip package.
Referring to
As shown in
A portion of the complete frame of the initial re-distribution layer 16, and of additional layers and components added thereto, is shown in
Referring now to
In an alternative embodiment of the manufacturing technique for build-up of chip package 10, it is recognized that a pre-cut laminate film could be applied to initial re-distribution layer 16. That is, rather than applying a continuous adhesive layer 24 via spin coating and subsequently laser ablating the adhesive layer 24 to form window 26, as shown in FIGS. 5 and 6A/6B, an adhesive film with a window pre-formed therein could be applied to initial re-distribution layer 16, such that no laser ablating of the adhesive layer is required.
Upon completion of the laser ablation of adhesive layer 24, a portion 30 of the adhesive layer 24 surrounding the ablated area (i.e., window 26) is exposed to UV light. This exposure to UV light partially cures portion 30 such that the adhesive layer 24 is prevented from encroaching into the ablated window 26.
Referring now to
Referring now to
As further shown in
Referring now to
In a next step of the chip manufacturing technique, and as shown in
As shown in
Beneficially, construction of chip package 10 according to the technique illustrated in
While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
Therefore, according to one embodiment of the invention, a chip package includes a base re-distribution layer having an opening formed therein in a center area of the base re-distribution layer, an adhesive layer applied to one side of the base re-distribution layer having a window formed therein free of adhesive material, and a die having a front surface affixed to the base re-distribution layer by way of the adhesive layer, wherein the die is aligned with the window formed in the adhesive layer such that only a perimeter of the front surface of the die is in contact with the adhesive layer. The chip package also includes a plurality of vias and a plurality of metal interconnects formed in the base re-distribution layer to electrically connect the base re-distribution layer to the die and a shield element positioned between the base re-distribution layer and the adhesive layer and generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer, with the shield element being separated from the die by an air gap. The shield element is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
According to another embodiment of the invention, a method of forming a chip package includes providing an initial polymer laminate layer, depositing a metallic shield element on one surface of the initial polymer laminate layer so as to cover a portion thereof, and applying an adhesive layer to the initial polymer laminate layer and over the metallic shield element, the adhesive layer having a portion removed therefrom to form a window in the adhesive layer that corresponds substantially to a surface area of the metallic shield element and aligned therewith. The method also includes adhering a die to the initial polymer laminate layer by way of the adhesive layer, with the die being positioned over the window such a perimeter of the die is in contact with the adhesive layer and an air pocket is formed between a center portion of the die and the shield element. The method further includes patterning the initial polymer laminate layer to include a plurality of vias and a plurality of metal interconnects so as to electrically connect the initial polymer laminate layer to the die, defining a portion of the initial polymer laminate layer corresponding to the window in the adhesive layer, and removing the portion of the initial polymer laminate layer and the metallic shield element from the adhesive layer so as to expose a front surface of the die.
According to yet another embodiment of the invention, a method for manufacturing a chip module includes providing a base re-distribution layer, depositing a shield element on one surface of the base re-distribution layer so as to cover a portion thereof, applying an adhesive layer to the base re-distribution layer and over the shield element, ablating a portion of the adhesive layer in an area adjacent to the shield element so as to expose at least a majority of the shield element, and applying a front surface of a die to the adhesive layer such that the die is aligned with the shield element, wherein a perimeter of the die is in contact with the adhesive layer and a center portion of the die is separated from the shield element by an air gap formed therebetween. The method also includes maintaining the shield element in place during a subsequent patterning of the base re-distribution layer that forms a plurality of vias and a plurality of metal interconnects to electrically connect the base re-distribution layer to the die, ablating a portion of the base re-distribution layer adjacent to the shield element, and removing the shield element and the portion of the base distribution layer so as to expose the front surface of the die.
McConnelee, Paul Alan, Smith, Scott, Durocher, Kevin Matthew, Principe, Laura A.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 23 2010 | MCCONNELEE, PAUL ALAN | General Electric Company | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031839 | /0237 | |
Jul 23 2010 | DUROCHER, KEVIN MATTHEW | General Electric Company | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031839 | /0237 | |
Jul 23 2010 | SMITH, SCOTT | General Electric Company | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031839 | /0237 | |
Jul 23 2010 | PRINCIPE, LAURA A | General Electric Company | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031839 | /0237 | |
Dec 23 2013 | General Electric Company | (assignment on the face of the patent) | / |
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